Merge with /home/wd/git/u-boot/master

master
Wolfgang Denk 20 years ago
commit 46044b4817
  1. 2
      Makefile
  2. 328
      common/miiphybb.c
  3. 2
      include/configs/MIP405.h
  4. 2
      include/configs/PIP405.h

@ -1737,7 +1737,7 @@ clean:
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
rm -f tools/env/fw_printenv tools/env/fw_setenv rm -f tools/env/fw_printenv tools/env/fw_setenv
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
rm -f board/trab/trab_fkt rm -f board/trab/trab_fkt board/voiceblue/eeprom
clobber: clean clobber: clean
find . -type f \( -name .depend \ find . -type f \( -name .depend \

@ -38,72 +38,79 @@
* Utility to send the preamble, address, and register (common to read * Utility to send the preamble, address, and register (common to read
* and write). * and write).
*/ */
static void miiphy_pre(char read, static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
unsigned char addr,
unsigned char reg)
{ {
int j; /* counter */ int j; /* counter */
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT); #ifndef CONFIG_EP8248
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
/* #endif
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
* The IEEE spec says this is a PHY optional requirement. The AMD /*
* 79C874 requires one after power up and one after a MII communications * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
* error. This means that we are doing more preambles than we need, * The IEEE spec says this is a PHY optional requirement. The AMD
* but it is safer and will be much more robust. * 79C874 requires one after power up and one after a MII communications
*/ * error. This means that we are doing more preambles than we need,
* but it is safer and will be much more robust.
MDIO_ACTIVE; */
MDIO(1);
for(j = 0; j < 32; j++) MDIO_ACTIVE;
{ MDIO (1);
MDC(0); for (j = 0; j < 32; j++) {
MIIDELAY; MDC (0);
MDC(1); MIIDELAY;
MIIDELAY; MDC (1);
} MIIDELAY;
}
/* send the start bit (01) and the read opcode (10) or write (10) */
MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY; /* send the start bit (01) and the read opcode (10) or write (10) */
MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY; MDC (0);
MDC(0); MDIO(read); MIIDELAY; MDC(1); MIIDELAY; MDIO (0);
MDC(0); MDIO(!read); MIIDELAY; MDC(1); MIIDELAY; MIIDELAY;
MDC (1);
/* send the PHY address */ MIIDELAY;
for(j = 0; j < 5; j++) MDC (0);
{ MDIO (1);
MDC(0); MIIDELAY;
if((addr & 0x10) == 0) MDC (1);
{ MIIDELAY;
MDIO(0); MDC (0);
} MDIO (read);
else MIIDELAY;
{ MDC (1);
MDIO(1); MIIDELAY;
} MDC (0);
MIIDELAY; MDIO (!read);
MDC(1); MIIDELAY;
MIIDELAY; MDC (1);
addr <<= 1; MIIDELAY;
}
/* send the PHY address */
/* send the register address */ for (j = 0; j < 5; j++) {
for(j = 0; j < 5; j++) MDC (0);
{ if ((addr & 0x10) == 0) {
MDC(0); MDIO (0);
if((reg & 0x10) == 0) } else {
{ MDIO (1);
MDIO(0); }
} MIIDELAY;
else MDC (1);
{ MIIDELAY;
MDIO(1); addr <<= 1;
} }
MIIDELAY;
MDC(1); /* send the register address */
MIIDELAY; for (j = 0; j < 5; j++) {
reg <<= 1; MDC (0);
} if ((reg & 0x10) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
reg <<= 1;
}
} }
@ -114,66 +121,63 @@ static void miiphy_pre(char read,
* Returns: * Returns:
* 0 on success * 0 on success
*/ */
int miiphy_read(unsigned char addr, int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
unsigned char reg,
unsigned short *value)
{ {
short rdreg; /* register working value */ short rdreg; /* register working value */
int j; /* counter */ int j; /* counter */
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT); #ifndef CONFIG_EP8248
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
miiphy_pre(1, addr, reg); #endif
/* tri-state our MDIO I/O pin so we can read */ miiphy_pre (1, addr, reg);
MDC(0);
MDIO_TRISTATE; /* tri-state our MDIO I/O pin so we can read */
MIIDELAY; MDC (0);
MDC(1); MDIO_TRISTATE;
MIIDELAY; MIIDELAY;
MDC (1);
/* check the turnaround bit: the PHY should be driving it to zero */ MIIDELAY;
if(MDIO_READ != 0)
{ /* check the turnaround bit: the PHY should be driving it to zero */
/* puts ("PHY didn't drive TA low\n"); */ if (MDIO_READ != 0) {
for(j = 0; j < 32; j++) /* puts ("PHY didn't drive TA low\n"); */
{ for (j = 0; j < 32; j++) {
MDC(0); MDC (0);
MIIDELAY; MIIDELAY;
MDC(1); MDC (1);
MIIDELAY; MIIDELAY;
} }
return(-1); return (-1);
} }
MDC(0); MDC (0);
MIIDELAY; MIIDELAY;
/* read 16 bits of register data, MSB first */ /* read 16 bits of register data, MSB first */
rdreg = 0; rdreg = 0;
for(j = 0; j < 16; j++) for (j = 0; j < 16; j++) {
{ MDC (1);
MDC(1); MIIDELAY;
MIIDELAY; rdreg <<= 1;
rdreg <<= 1; rdreg |= MDIO_READ;
rdreg |= MDIO_READ; MDC (0);
MDC(0); MIIDELAY;
MIIDELAY; }
}
MDC (1);
MDC(1); MIIDELAY;
MIIDELAY; MDC (0);
MDC(0); MIIDELAY;
MIIDELAY; MDC (1);
MDC(1); MIIDELAY;
MIIDELAY;
*value = rdreg;
*value = rdreg;
#ifdef DEBUG #ifdef DEBUG
printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif #endif
return 0; return 0;
} }
@ -184,47 +188,51 @@ int miiphy_read(unsigned char addr,
* Returns: * Returns:
* 0 on success * 0 on success
*/ */
int miiphy_write(unsigned char addr, int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
unsigned char reg,
unsigned short value)
{ {
int j; /* counter */ int j; /* counter */
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT); #ifndef CONFIG_EP8248
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
miiphy_pre(0, addr, reg); #endif
/* send the turnaround (10) */ miiphy_pre (0, addr, reg);
MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY; /* send the turnaround (10) */
MDC (0);
/* write 16 bits of register data, MSB first */ MDIO (1);
for(j = 0; j < 16; j++) MIIDELAY;
{ MDC (1);
MDC(0); MIIDELAY;
if((value & 0x00008000) == 0) MDC (0);
{ MDIO (0);
MDIO(0); MIIDELAY;
} MDC (1);
else MIIDELAY;
{
MDIO(1); /* write 16 bits of register data, MSB first */
} for (j = 0; j < 16; j++) {
MIIDELAY; MDC (0);
MDC(1); if ((value & 0x00008000) == 0) {
MIIDELAY; MDIO (0);
value <<= 1; } else {
} MDIO (1);
}
/* MIIDELAY;
* Tri-state the MDIO line. MDC (1);
*/ MIIDELAY;
MDIO_TRISTATE; value <<= 1;
MDC(0); }
MIIDELAY;
MDC(1); /*
MIIDELAY; * Tri-state the MDIO line.
*/
return 0; MDIO_TRISTATE;
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
return 0;
} }
#endif /* CONFIG_BITBANGMII */ #endif /* CONFIG_BITBANGMII */

@ -128,7 +128,7 @@
#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */

@ -112,7 +112,7 @@
#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */

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