Merge with /home/wd/git/u-boot/master

Makefile

@@ -1737,7 +1737,7 @@ clean:
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
-	rm -f board/trab/trab_fkt
+	rm -f board/trab/trab_fkt board/voiceblue/eeprom
 
 clobber:	clean
 	find . -type f \( -name .depend \

common/miiphybb.c

@@ -38,12 +38,12 @@
  * Utility to send the preamble, address, and register (common to read
  * and write).
  */
-static void miiphy_pre(char	      read,
-		       unsigned char  addr,
-		       unsigned char  reg)
+static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
 {
 	int j;			/* counter */
-  volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
+#ifndef CONFIG_EP8248
+	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
 
 	/*
 	 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
@@ -54,53 +54,60 @@ static void miiphy_pre(char	      read,
 	 */
 
 	MDIO_ACTIVE;
-  MDIO(1);
-  for(j = 0; j < 32; j++)
-  {
-    MDC(0);
+	MDIO (1);
+	for (j = 0; j < 32; j++) {
+		MDC (0);
 		MIIDELAY;
-    MDC(1);
+		MDC (1);
 		MIIDELAY;
 	}
 
 	/* send the start bit (01) and the read opcode (10) or write (10) */
-  MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
-  MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
-  MDC(0); MDIO(read);  MIIDELAY; MDC(1); MIIDELAY;
-  MDC(0); MDIO(!read); MIIDELAY; MDC(1); MIIDELAY;
+	MDC (0);
+	MDIO (0);
+	MIIDELAY;
+	MDC (1);
+	MIIDELAY;
+	MDC (0);
+	MDIO (1);
+	MIIDELAY;
+	MDC (1);
+	MIIDELAY;
+	MDC (0);
+	MDIO (read);
+	MIIDELAY;
+	MDC (1);
+	MIIDELAY;
+	MDC (0);
+	MDIO (!read);
+	MIIDELAY;
+	MDC (1);
+	MIIDELAY;
 
 	/* send the PHY address */
-  for(j = 0; j < 5; j++)
-  {
-    MDC(0);
-    if((addr & 0x10) == 0)
-    {
-      MDIO(0);
-    }
-    else
-    {
-      MDIO(1);
+	for (j = 0; j < 5; j++) {
+		MDC (0);
+		if ((addr & 0x10) == 0) {
+			MDIO (0);
+		} else {
+			MDIO (1);
 		}
 		MIIDELAY;
-    MDC(1);
+		MDC (1);
 		MIIDELAY;
 		addr <<= 1;
 	}
 
 	/* send the register address */
-  for(j = 0; j < 5; j++)
-  {
-    MDC(0);
-    if((reg & 0x10) == 0)
-    {
-      MDIO(0);
-    }
-    else
-    {
-      MDIO(1);
+	for (j = 0; j < 5; j++) {
+		MDC (0);
+		if ((reg & 0x10) == 0) {
+			MDIO (0);
+		} else {
+			MDIO (1);
 		}
 		MIIDELAY;
-    MDC(1);
+		MDC (1);
 		MIIDELAY;
 		reg <<= 1;
 	}
@@ -114,57 +121,54 @@ static void miiphy_pre(char	      read,
  * Returns:
  *   0 on success
  */
-int miiphy_read(unsigned char  addr,
-		unsigned char  reg,
-		unsigned short *value)
+int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
 {
 	short rdreg;		/* register working value */
 	int j;			/* counter */
-  volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
+#ifndef CONFIG_EP8248
+	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
 
-  miiphy_pre(1, addr, reg);
+	miiphy_pre (1, addr, reg);
 
 	/* tri-state our MDIO I/O pin so we can read */
-  MDC(0);
+	MDC (0);
 	MDIO_TRISTATE;
 	MIIDELAY;
-  MDC(1);
+	MDC (1);
 	MIIDELAY;
 
 	/* check the turnaround bit: the PHY should be driving it to zero */
-  if(MDIO_READ != 0)
-  {
+	if (MDIO_READ != 0) {
 		/* puts ("PHY didn't drive TA low\n"); */
-    for(j = 0; j < 32; j++)
-    {
-      MDC(0);
+		for (j = 0; j < 32; j++) {
+			MDC (0);
 			MIIDELAY;
-      MDC(1);
+			MDC (1);
 			MIIDELAY;
 		}
-    return(-1);
+		return (-1);
 	}
 
-  MDC(0);
+	MDC (0);
 	MIIDELAY;
 
 	/* read 16 bits of register data, MSB first */
 	rdreg = 0;
-  for(j = 0; j < 16; j++)
-  {
-    MDC(1);
+	for (j = 0; j < 16; j++) {
+		MDC (1);
 		MIIDELAY;
 		rdreg <<= 1;
 		rdreg |= MDIO_READ;
-    MDC(0);
+		MDC (0);
 		MIIDELAY;
 	}
 
-  MDC(1);
+	MDC (1);
 	MIIDELAY;
-  MDC(0);
+	MDC (0);
 	MIIDELAY;
-  MDC(1);
+	MDC (1);
 	MIIDELAY;
 
 	*value = rdreg;
@@ -184,33 +188,37 @@ int miiphy_read(unsigned char  addr,
  * Returns:
  *   0 on success
  */
-int miiphy_write(unsigned char  addr,
-		 unsigned char  reg,
-		 unsigned short value)
+int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
 {
 	int j;			/* counter */
-  volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
+#ifndef CONFIG_EP8248
+	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
 
-  miiphy_pre(0, addr, reg);
+	miiphy_pre (0, addr, reg);
 
 	/* send the turnaround (10) */
-  MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
-  MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
+	MDC (0);
+	MDIO (1);
+	MIIDELAY;
+	MDC (1);
+	MIIDELAY;
+	MDC (0);
+	MDIO (0);
+	MIIDELAY;
+	MDC (1);
+	MIIDELAY;
 
 	/* write 16 bits of register data, MSB first */
-  for(j = 0; j < 16; j++)
-  {
-    MDC(0);
-    if((value & 0x00008000) == 0)
-    {
-      MDIO(0);
-    }
-    else
-    {
-      MDIO(1);
+	for (j = 0; j < 16; j++) {
+		MDC (0);
+		if ((value & 0x00008000) == 0) {
+			MDIO (0);
+		} else {
+			MDIO (1);
 		}
 		MIIDELAY;
-    MDC(1);
+		MDC (1);
 		MIIDELAY;
 		value <<= 1;
 	}
@@ -219,9 +227,9 @@ int miiphy_write(unsigned char  addr,
 	 * Tri-state the MDIO line.
 	 */
 	MDIO_TRISTATE;
-  MDC(0);
+	MDC (0);
 	MIIDELAY;
-  MDC(1);
+	MDC (1);
 	MIIDELAY;
 
 	return 0;

include/configs/MIP405.h

@@ -128,7 +128,7 @@
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
 #define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME	-10	/* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
 
 #define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/

include/configs/PIP405.h

@@ -112,7 +112,7 @@
 
 #define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME	-10	/* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */