OMAP3: Enable SPL on omap3_logic

Previously, Omap3_logic assumed X-loader was present. With this patch, we can finally replace X-loader with an MLO generated by U-Boot. This requires ECC to be setup to match the Linux Kernel and the PBIAS confgured for the SD card. Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
9 years ago · 49c7303f0e
parent 7443a9c405
commit 49c7303f0e
2 changed files with 185 additions and 124 deletions
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@ -26,10 +26,15 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/mach-types.h>
+#include <linux/mtd/nand.h>
 #include "omap3logic.h"

 DECLARE_GLOBAL_DATA_PTR;

+#define CONTROL_WKUP_CTRL	0x48002a5c
+#define GPIO_IO_PWRDNZ	(1 << 6)
+#define PBIASLITEVMODE1	(1 << 8)
+
 /*
 * two dimensional array of strucures containining board name and Linux
 * machine IDs; row it selected based on CPU column is slected based
@ -73,6 +78,57 @@ static struct board_id {
 	},
 };

+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank.  This
+ * provides the timing values back to the function that configures
+ * the memory.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	timings->mr = MICRON_V_MR_165;
+	/* 256MB DDR */
+	timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+	timings->ctrla = MICRON_V_ACTIMA_200;
+	timings->ctrlb = MICRON_V_ACTIMB_200;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	t2_t *t2_base = (t2_t *)T2_BASE;
+	u32 pbias_lite;
+	/* set up dual-voltage GPIOs to 1.8V */
+	pbias_lite = readl(&t2_base->pbias_lite);
+	pbias_lite &= ~PBIASLITEVMODE1;
+	pbias_lite |= PBIASLITEPWRDNZ1;
+	writel(pbias_lite, &t2_base->pbias_lite);
+	if (get_cpu_family() == CPU_OMAP36XX)
+		writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
+				CONTROL_WKUP_CTRL);
+	twl4030_power_init();
+
+	omap_die_id_display();
+	putc('\n');
+
+	return 0;
+}
+
 /*
 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
 */
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@ -11,112 +11,113 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H

-/*
- * High Level Configuration Options
- */
+/* High Level Configuration Options */

 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define CONFIG_SYS_TEXT_BASE	0x80400000

-#include <configs/ti_omap3_common.h>
-#define CONFIG_OMAP3_LOGIC		/* working with Logic OMAP boards */
 /*
- * Display CPU and Board information
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.  We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
 */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#include <configs/ti_omap3_common.h>
+
+/* Display CPU and Board information */

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
 #define CONFIG_MISC_INIT_R		/* misc_init_r dumps the die id */
-
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
-
 #define CONFIG_CMDLINE_EDITING		/* cmd line edit/history */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress w/no delay */

-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-						/* Sector */
-/*
- * Hardware drivers
- */
+/* Hardware drivers */

 /* GPIO banks */
 #define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */

-/*
- * select serial console configuration
- */
+#define CONFIG_USB_OMAP3
+
+/* select serial console configuration */
 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
 #define CONFIG_SERIAL1			1	/* UART1 on OMAP Logic boards */

-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION
-
 /* commands to include */
+#define CONFIG_CMD_NAND
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
-#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(x-loader),"\
-					"1920k(u-boot),128k(u-boot-env),"\
-					"4m(kernel),-(fs)"
-
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP

-#define CONFIG_SYS_NO_FLASH
+#define CONFIG_YAFFS2

-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+/* I2C */
 #define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM AT24C64      */
+#define EXPANSION_EEPROM_I2C_BUS	2	/* I2C Bus for AT24C64 */
+#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID

-/*
- * TWL4030
- */
-
+/* TWL4030 */
+#define CONFIG_TWL4030_PWM

-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_BASE            NAND_BASE
+/* Board NAND Info. */
+#ifdef CONFIG_NAND
 #define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
-							/* to access nand */

+#define CONFIG_CMD_UBI			/* UBI-formated MTD partition support */
+#define CONFIG_CMD_UBIFS		/* Read-only UBI volume operations */
+#define CONFIG_RBTREE			/* required by CONFIG_CMD_UBI */
+#define CONFIG_LZO			/* required by CONFIG_CMD_UBIFS */

+#define CONFIG_SYS_NAND_ADDR		NAND_BASE /* physical address */
+						  /* to access nand */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	  /* Max number of */
 						  /* NAND devices */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
-
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					 52, 53, 54, 55, 56}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_BCH
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS		/* required for UBI partition support */
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(MLO),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+#endif

 /* Environment information */

@ -142,15 +143,18 @@
 	"echo \"Defaulting to 4.3 LCD panel (display=15).\";"		\
 	"setenv display 15;"						\
 	"setenv preboot;"						\
+	"nand unlock;"							\
 	"saveenv;"

-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x81000000\0" \
-	"bootfile=uImage\0" \
+	"uimage=uImage\0" \
+	"zimage=zImage\0" \
 	"mtdids=" MTDIDS_DEFAULT "\0"	\
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
 	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 			"if run loadbootscript; then " \
 				"run bootscript; " \
@ -168,79 +172,77 @@
 		"setenv bootargs ${bootargs} omapfb.vrfb=y " \
 		"omapfb.rotate=${rotation}; " \
 		"fi\0" \
-	"otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+	"optargs=ignore_loglevel early_printk no_console_suspend\0" \
 	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
 	"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
-		"${otherbootargs};" \
+		"${optargs};" \
 		"run addmtdparts; " \
 		"run vrfb_arg\0" \
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo 'Running bootscript from mmc ...'; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=mmc rescan ${mmcdev}; " \
-		"fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=mmc rescan; " \
+		"fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \
+	"loadzimage=mmc rescan; " \
+		"fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \
 	"ramdisksize=64000\0" \
 	"ramdiskaddr=0x82000000\0" \
 	"ramdiskimage=rootfs.ext2.gz.uboot\0" \
+	"loadramdisk=mmc rescan; " \
+		"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \
 	"ramargs=run setconsole; setenv bootargs console=${console} " \
 		"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
-	"mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+	"mmcargs=run setconsole; setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"fdtaddr=0x86000000\0" \
+	"loadfdtimage=mmc rescan; " \
+		"fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
+	"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"run loadzimage; " \
+		"run loadfdtimage; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \
 		"run ramargs; " \
 		"run common_bootargs; " \
 		"run dump_bootargs; " \
 		"run loaduimage; " \
-		"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+		"run loadramdisk; " \
 		"bootm ${loadaddr} ${ramdiskaddr}\0" \
-	"ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
+	"mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \
 		"run ramargs; " \
 		"run common_bootargs; " \
 		"run dump_bootargs; " \
-		"tftpboot ${loadaddr} ${bootfile}; "\
-		"tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
+		"run loadzimage; " \
+		"run loadramdisk; " \
+		"run loadfdtimage; " \
+		"bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \
+	"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
+		"run ramargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"tftpboot ${loadaddr} ${uimage}; " \
+		"tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
 		"bootm ${loadaddr} ${ramdiskaddr}\0"

 #define CONFIG_BOOTCOMMAND \
 	"run autoboot"

+/* Miscellaneous configurable options */
 #define CONFIG_AUTO_COMPLETE
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-

 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
 					0x01F00000) /* 31MB */

-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
+/* FLASH and environment organization */

 /* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #elif defined(CONFIG_CMD_ONENAND)
@ -250,29 +252,32 @@
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
-#endif
-
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800

-/*
- * SMSC922x Ethernet
- */
+/* SMSC922x Ethernet */
 #if defined(CONFIG_CMD_NET)
-
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_16_BIT
 #define CONFIG_SMC911X_BASE	0x08000000
-
 #endif /* (CONFIG_CMD_NET) */

+/* Defines for SPL */
+
+#define CONFIG_SPL_OMAP3_ID_NAND
+
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
+
 #endif /* __CONFIG_H */