Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Peter Pearse <peter.pearse@arm.com>master
Jean-Christophe PLAGNIOL-VILLARD
16 years ago
parent
46937b2742
commit
576afd4fae
@ -1,2 +0,0 @@ |
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/integratorap/u-boot.lds |
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/integratorcp/u-boot.lds |
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@ -0,0 +1,235 @@ |
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#!/bin/sh |
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mkdir -p ${obj}include |
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mkdir -p ${obj}board/armltd/integrator |
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config_file=${obj}include/config.h |
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if [ "$1" = "ap" ] |
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then |
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# --------------------------------------------------------- |
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# Set the platform defines |
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# --------------------------------------------------------- |
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echo -n "/* Integrator configuration implied " > ${config_file} |
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echo " by Makefile target */" >> ${config_file} |
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echo -n "#define CONFIG_INTEGRATOR" >> ${config_file} |
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echo " /* Integrator board */" >> ${config_file} |
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echo -n "#define CONFIG_ARCH_INTEGRATOR" >> ${config_file} |
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echo " 1 /* Integrator/AP */" >> ${config_file} |
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# --------------------------------------------------------- |
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# Set the core module defines according to Core Module |
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# --------------------------------------------------------- |
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cpu="arm_intcm" |
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variant="unknown core module" |
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if [ "$2" = "" ] |
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then |
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echo "$0:: No parameters - using arm_intcm" |
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else |
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case "$2" in |
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ap7_config) |
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cpu="arm_intcm" |
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variant="unported core module CM7TDMI" |
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;; |
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ap966) |
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cpu="arm_intcm" |
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variant="unported core module CM966E-S" |
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;; |
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ap922_config) |
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cpu="arm_intcm" |
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variant="unported core module CM922T" |
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;; |
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integratorap_config | \ |
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ap_config) |
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cpu="arm_intcm" |
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variant="unspecified core module" |
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;; |
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ap720t_config) |
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cpu="arm720t" |
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echo -n "#define CONFIG_CM720T" >> ${config_file} |
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echo " 1 /* CPU core is ARM720T */ " >> ${config_file} |
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variant="Core module CM720T" |
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;; |
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ap922_XA10_config) |
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cpu="arm_intcm" |
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variant="unported core module CM922T_XA10" |
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echo -n "#define CONFIG_CM922T_XA10" >> ${config_file} |
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echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file} |
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;; |
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ap920t_config) |
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cpu="arm920t" |
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variant="Core module CM920T" |
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echo -n "#define CONFIG_CM920T" >> ${config_file} |
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echo " 1 /* CPU core is ARM920T */" >> ${config_file} |
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;; |
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ap926ejs_config) |
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cpu="arm926ejs" |
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variant="Core module CM926EJ-S" |
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echo -n "#define CONFIG_CM926EJ_S" >> ${config_file} |
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echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file} |
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;; |
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ap946es_config) |
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cpu="arm946es" |
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variant="Core module CM946E-S" |
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echo -n "#define CONFIG_CM946E_S" >> ${config_file} |
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echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file} |
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;; |
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*) |
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echo "$0:: Unknown core module" |
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variant="unknown core module" |
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cpu="arm_intcm" |
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;; |
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esac |
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fi |
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case "$cpu" in |
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arm_intcm) |
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echo "/* Core module undefined/not ported */" >> ${config_file} |
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echo "#define CONFIG_ARM_INTCM 1" >> ${config_file} |
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echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file} |
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echo -n " /* CM may not have " >> ${config_file} |
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echo "multiple SSRAM mapping */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file} |
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echo -n " /* CM may not support SPD " >> ${config_file} |
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echo "query */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_REMAP " >> ${config_file} |
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echo -n " /* CM may not support " >> ${config_file} |
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echo "remapping */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_INIT " >> ${config_file} |
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echo -n " /* CM may not have " >> ${config_file} |
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echo "initialization reg */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file} |
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echo " /* CM may not have TCRAM */" >> ${config_file} |
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echo -n " /* May not be processor " >> ${config_file} |
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echo "without cache support */" >> ${config_file} |
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echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file} |
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echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file} |
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;; |
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arm720t) |
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echo -n " /* May not be processor " >> ${config_file} |
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echo "without cache support */" >> ${config_file} |
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echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file} |
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echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file} |
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;; |
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esac |
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else |
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# --------------------------------------------------------- |
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# Set the platform defines |
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# --------------------------------------------------------- |
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echo -n "/* Integrator configuration implied " > ${config_file} |
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echo " by Makefile target */" >> ${config_file} |
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echo -n "#define CONFIG_INTEGRATOR" >> ${config_file} |
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echo " /* Integrator board */" >> ${config_file} |
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echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> ${config_file} |
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echo " 1 /* Integrator/CP */" >> ${config_file} |
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cpu="arm_intcm" |
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variant="unknown core module" |
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if [ "$2" = "" ] |
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then |
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echo "$0:: No parameters - using arm_intcm" |
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else |
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case "$2" in |
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ap966) |
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cpu="arm_intcm" |
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variant="unported core module CM966E-S" |
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;; |
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ap922_config) |
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cpu="arm_intcm" |
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variant="unported core module CM922T" |
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;; |
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integratorcp_config | \ |
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cp_config) |
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cpu="arm_intcm" |
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variant="unspecified core module" |
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;; |
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cp922_XA10_config) |
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cpu="arm_intcm" |
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variant="unported core module CM922T_XA10" |
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echo -n "#define CONFIG_CM922T_XA10" >> ${config_file} |
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echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file} |
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;; |
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cp920t_config) |
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cpu="arm920t" |
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variant="Core module CM920T" |
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echo -n "#define CONFIG_CM920T" >> ${config_file} |
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echo " 1 /* CPU core is ARM920T */" >> ${config_file} |
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;; |
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cp926ejs_config) |
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cpu="arm926ejs" |
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variant="Core module CM926EJ-S" |
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echo -n "#define CONFIG_CM926EJ_S" >> ${config_file} |
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echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file} |
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;; |
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cp946es_config) |
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cpu="arm946es" |
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variant="Core module CM946E-S" |
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echo -n "#define CONFIG_CM946E_S" >> ${config_file} |
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echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file} |
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;; |
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cp1136_config) |
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cpu="arm1136" |
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variant="Core module CM1136EJF-S" |
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echo -n "#define CONFIG_CM1136EJF_S" >> ${config_file} |
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echo " 1 /* CPU core is ARM1136JF-S */ " >> ${config_file} |
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;; |
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*) |
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echo "$0:: Unknown core module" |
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variant="unknown core module" |
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cpu="arm_intcm" |
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;; |
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esac |
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fi |
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if [ "$cpu" = "arm_intcm" ] |
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then |
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echo "/* Core module undefined/not ported */" >> ${config_file} |
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echo "#define CONFIG_ARM_INTCM 1" >> ${config_file} |
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echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file} |
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echo -n " /* CM may not have " >> ${config_file} |
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echo "multiple SSRAM mapping */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file} |
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echo -n " /* CM may not support SPD " >> ${config_file} |
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echo "query */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_REMAP " >> ${config_file} |
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echo -n " /* CM may not support " >> ${config_file} |
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echo "remapping */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_INIT " >> ${config_file} |
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echo -n " /* CM may not have " >> ${config_file} |
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echo "initialization reg */" >> ${config_file} |
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echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file} |
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echo " /* CM may not have TCRAM */" >> ${config_file} |
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fi |
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fi # ap |
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# --------------------------------------------------------- |
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# Complete the configuration |
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# --------------------------------------------------------- |
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$MKCONFIG -a integrator$1 arm $cpu integrator armltd; |
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echo "Variant:: $variant with core $cpu" |
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@ -1,127 +0,0 @@ |
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#!/bin/sh |
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# --------------------------------------------------------- |
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# Set the platform defines |
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# --------------------------------------------------------- |
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echo -n "/* Integrator configuration implied " > tmp.fil |
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echo " by Makefile target */" >> tmp.fil |
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echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil |
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echo " /* Integrator board */" >> tmp.fil |
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echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil |
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echo " 1 /* Integrator/AP */" >> tmp.fil |
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# --------------------------------------------------------- |
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# Set the core module defines according to Core Module |
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# --------------------------------------------------------- |
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cpu="arm_intcm" |
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variant="unknown core module" |
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if [ "$1" = "" ] |
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then |
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echo "$0:: No parameters - using arm_intcm" |
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else |
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case "$1" in |
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ap7_config) |
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cpu="arm_intcm" |
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variant="unported core module CM7TDMI" |
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;; |
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ap966) |
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cpu="arm_intcm" |
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variant="unported core module CM966E-S" |
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;; |
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ap922_config) |
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cpu="arm_intcm" |
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variant="unported core module CM922T" |
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;; |
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integratorap_config | \ |
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ap_config) |
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cpu="arm_intcm" |
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variant="unspecified core module" |
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;; |
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ap720t_config) |
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cpu="arm720t" |
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echo -n "#define CONFIG_CM720T" >> tmp.fil |
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echo " 1 /* CPU core is ARM720T */ " >> tmp.fil |
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variant="Core module CM720T" |
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;; |
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ap922_XA10_config) |
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cpu="arm_intcm" |
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variant="unported core module CM922T_XA10" |
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echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil |
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echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil |
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;; |
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ap920t_config) |
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cpu="arm920t" |
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variant="Core module CM920T" |
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echo -n "#define CONFIG_CM920T" >> tmp.fil |
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echo " 1 /* CPU core is ARM920T */" >> tmp.fil |
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;; |
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ap926ejs_config) |
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cpu="arm926ejs" |
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variant="Core module CM926EJ-S" |
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echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil |
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echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil |
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;; |
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ap946es_config) |
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cpu="arm946es" |
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variant="Core module CM946E-S" |
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echo -n "#define CONFIG_CM946E_S" >> tmp.fil |
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echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil |
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;; |
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*) |
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echo "$0:: Unknown core module" |
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variant="unknown core module" |
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cpu="arm_intcm" |
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;; |
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esac |
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fi |
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case "$cpu" in |
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arm_intcm) |
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echo "/* Core module undefined/not ported */" >> tmp.fil |
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echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil |
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echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil |
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echo -n " /* CM may not have " >> tmp.fil |
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echo "multiple SSRAM mapping */" >> tmp.fil |
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echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil |
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echo -n " /* CM may not support SPD " >> tmp.fil |
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echo "query */" >> tmp.fil |
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echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil |
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echo -n " /* CM may not support " >> tmp.fil |
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echo "remapping */" >> tmp.fil |
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echo -n "#undef CONFIG_CM_INIT " >> tmp.fil |
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echo -n " /* CM may not have " >> tmp.fil |
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echo "initialization reg */" >> tmp.fil |
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echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil |
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echo " /* CM may not have TCRAM */" >> tmp.fil |
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echo -n " /* May not be processor " >> tmp.fil |
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echo "without cache support */" >> tmp.fil |
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echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil |
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echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil |
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;; |
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arm720t) |
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echo -n " /* May not be processor " >> tmp.fil |
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echo "without cache support */" >> tmp.fil |
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echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil |
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echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil |
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;; |
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esac |
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mkdir -p ${obj}include |
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mkdir -p ${obj}board/armltd/integratorap |
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mv tmp.fil ${obj}include/config.h |
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# --------------------------------------------------------- |
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# Complete the configuration |
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# --------------------------------------------------------- |
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$MKCONFIG -a integratorap arm $cpu integratorap armltd; |
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echo "Variant:: $variant with core $cpu" |
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@ -1,171 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
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* |
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* (C) Copyright 2003 |
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* Texas Instruments, <www.ti.com> |
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* Kshitij Gupta <Kshitij@ti.com> |
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* |
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* (C) Copyright 2004 |
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* ARM Ltd. |
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* Philippe Robin, <philippe.robin@arm.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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/* The Integrator/AP timer1 is clocked at 24MHz
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* can be divided by 16 or 256 |
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* and is a 16-bit counter |
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*/ |
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/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/ |
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static ulong timestamp; /* U-Boot ticks since startup */ |
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static ulong total_count = 0; /* Total timer count */ |
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static ulong lastdec; /* Timer reading at last call */ |
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static ulong div_clock = 256; /* Divisor applied to the timer clock */ |
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static ulong div_timer = 1; /* Divisor to convert timer reading
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|
||||||
* change to U-Boot ticks |
|
||||||
*/ |
|
||||||
/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */ |
|
||||||
|
|
||||||
#define TIMER_LOAD_VAL 0x0000FFFFL |
|
||||||
#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL) |
|
||||||
|
|
||||||
/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
|
|
||||||
* - unless otherwise stated |
|
||||||
*/ |
|
||||||
|
|
||||||
/* starts a counter
|
|
||||||
* - the Integrator/AP timer issues an interrupt |
|
||||||
* each time it reaches zero |
|
||||||
*/ |
|
||||||
int timer_init (void) |
|
||||||
{ |
|
||||||
/* Load timer with initial value */ |
|
||||||
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; |
|
||||||
/* Set timer to be
|
|
||||||
* enabled 1 |
|
||||||
* free-running 0 |
|
||||||
* XX 00 |
|
||||||
* divider 256 10 |
|
||||||
* XX 00 |
|
||||||
*/ |
|
||||||
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088; |
|
||||||
total_count = 0; |
|
||||||
/* init the timestamp and lastdec value */ |
|
||||||
reset_timer_masked(); |
|
||||||
|
|
||||||
div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ; |
|
||||||
div_timer /= div_clock; |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* timer without interrupts |
|
||||||
*/ |
|
||||||
void reset_timer (void) |
|
||||||
{ |
|
||||||
reset_timer_masked (); |
|
||||||
} |
|
||||||
|
|
||||||
ulong get_timer (ulong base_ticks) |
|
||||||
{ |
|
||||||
return get_timer_masked () - base_ticks; |
|
||||||
} |
|
||||||
|
|
||||||
void set_timer (ulong ticks) |
|
||||||
{ |
|
||||||
timestamp = ticks; |
|
||||||
total_count = ticks * div_timer; |
|
||||||
reset_timer_masked(); |
|
||||||
} |
|
||||||
|
|
||||||
/* delay x useconds */ |
|
||||||
void udelay (unsigned long usec) |
|
||||||
{ |
|
||||||
ulong tmo, tmp; |
|
||||||
|
|
||||||
/* Convert to U-Boot ticks */ |
|
||||||
tmo = usec * CONFIG_SYS_HZ; |
|
||||||
tmo /= (1000000L); |
|
||||||
|
|
||||||
tmp = get_timer_masked(); /* get current timestamp */ |
|
||||||
tmo += tmp; /* wake up timestamp */ |
|
||||||
|
|
||||||
while (get_timer_masked () < tmo) { /* loop till event */ |
|
||||||
/*NOP*/; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
void reset_timer_masked (void) |
|
||||||
{ |
|
||||||
/* reset time */ |
|
||||||
lastdec = READ_TIMER; /* capture current decrementer value */ |
|
||||||
timestamp = 0; /* start "advancing" time stamp from 0 */ |
|
||||||
} |
|
||||||
|
|
||||||
/* converts the timer reading to U-Boot ticks */ |
|
||||||
/* the timestamp is the number of ticks since reset */ |
|
||||||
/* This routine does not detect wraps unless called regularly
|
|
||||||
ASSUMES a call at least every 16 seconds to detect every reload */ |
|
||||||
ulong get_timer_masked (void) |
|
||||||
{ |
|
||||||
ulong now = READ_TIMER; /* current count */ |
|
||||||
|
|
||||||
if (now > lastdec) { |
|
||||||
/* Must have wrapped */ |
|
||||||
total_count += lastdec + TIMER_LOAD_VAL + 1 - now; |
|
||||||
} else { |
|
||||||
total_count += lastdec - now; |
|
||||||
} |
|
||||||
lastdec = now; |
|
||||||
timestamp = total_count/div_timer; |
|
||||||
|
|
||||||
return timestamp; |
|
||||||
} |
|
||||||
|
|
||||||
/* waits specified delay value and resets timestamp */ |
|
||||||
void udelay_masked (unsigned long usec) |
|
||||||
{ |
|
||||||
udelay(usec); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* This function is derived from PowerPC code (read timebase as long long). |
|
||||||
* On ARM it just returns the timer value. |
|
||||||
*/ |
|
||||||
unsigned long long get_ticks(void) |
|
||||||
{ |
|
||||||
return get_timer(0); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Return the timebase clock frequency |
|
||||||
* i.e. how often the timer decrements |
|
||||||
*/ |
|
||||||
ulong get_tbclk (void) |
|
||||||
{ |
|
||||||
return CONFIG_SYS_HZ_CLOCK/div_clock; |
|
||||||
} |
|
||||||
@ -1,53 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2000-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# See file CREDITS for list of people who contributed to this
|
|
||||||
# project.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or
|
|
||||||
# modify it under the terms of the GNU General Public License as
|
|
||||||
# published by the Free Software Foundation; either version 2 of
|
|
||||||
# the License, or (at your option) any later version.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
# You should have received a copy of the GNU General Public License
|
|
||||||
# along with this program; if not, write to the Free Software
|
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
# MA 02111-1307 USA
|
|
||||||
#
|
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk |
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
|
||||||
|
|
||||||
SOBJS := lowlevel_init.o
|
|
||||||
|
|
||||||
COBJS := integratorcp.o
|
|
||||||
COBJS += timer.o
|
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
|
||||||
|
|
||||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
|
||||||
|
|
||||||
clean: |
|
||||||
rm -f $(SOBJS) $(OBJS)
|
|
||||||
|
|
||||||
distclean: clean |
|
||||||
rm -f $(LIB) core *.bak $(obj).depend
|
|
||||||
|
|
||||||
#########################################################################
|
|
||||||
|
|
||||||
# defines $(obj).depend target
|
|
||||||
include $(SRCTREE)/rules.mk |
|
||||||
|
|
||||||
sinclude $(obj).depend |
|
||||||
|
|
||||||
#########################################################################
|
|
||||||
@ -1,5 +0,0 @@ |
|||||||
#
|
|
||||||
# image should be loaded at 0x01000000
|
|
||||||
#
|
|
||||||
|
|
||||||
TEXT_BASE = 0x01000000
|
|
||||||
@ -1,118 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2002 |
|
||||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
|
||||||
* Marius Groeger <mgroeger@sysgo.de> |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
|
||||||
* |
|
||||||
* (C) Copyright 2003 |
|
||||||
* Texas Instruments, <www.ti.com> |
|
||||||
* Kshitij Gupta <Kshitij@ti.com> |
|
||||||
* |
|
||||||
* (C) Copyright 2004 |
|
||||||
* ARM Ltd. |
|
||||||
* Philippe Robin, <philippe.robin@arm.com> |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR; |
|
||||||
|
|
||||||
void peripheral_power_enable (void); |
|
||||||
|
|
||||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS) |
|
||||||
void show_boot_progress(int progress) |
|
||||||
{ |
|
||||||
printf("Boot reached stage %d\n", progress); |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous platform dependent initialisations |
|
||||||
*/ |
|
||||||
|
|
||||||
int board_init (void) |
|
||||||
{ |
|
||||||
/* arch number of Integrator Board */ |
|
||||||
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; |
|
||||||
|
|
||||||
/* adress of boot parameters */ |
|
||||||
gd->bd->bi_boot_params = 0x00000100; |
|
||||||
|
|
||||||
gd->flags = 0; |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_REMAP |
|
||||||
extern void cm_remap(void); |
|
||||||
cm_remap(); /* remaps writeable memory to 0x00000000 */ |
|
||||||
#endif |
|
||||||
|
|
||||||
icache_enable (); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
int misc_init_r (void) |
|
||||||
{ |
|
||||||
setenv("verify", "n"); |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/******************************
|
|
||||||
Routine: |
|
||||||
Description: |
|
||||||
******************************/ |
|
||||||
int dram_init (void) |
|
||||||
{ |
|
||||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
|
||||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_SPD_DETECT |
|
||||||
{ |
|
||||||
extern void dram_query(void); |
|
||||||
unsigned long cm_reg_sdram; |
|
||||||
unsigned long sdram_shift; |
|
||||||
|
|
||||||
dram_query(); /* Assembler accesses to CM registers */ |
|
||||||
/* Queries the SPD values */ |
|
||||||
|
|
||||||
/* Obtain the SDRAM size from the CM SDRAM register */ |
|
||||||
|
|
||||||
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); |
|
||||||
/* Register SDRAM size
|
|
||||||
* |
|
||||||
* 0xXXXXXXbbb000bb 16 MB |
|
||||||
* 0xXXXXXXbbb001bb 32 MB |
|
||||||
* 0xXXXXXXbbb010bb 64 MB |
|
||||||
* 0xXXXXXXbbb011bb 128 MB |
|
||||||
* 0xXXXXXXbbb100bb 256 MB |
|
||||||
* |
|
||||||
*/ |
|
||||||
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; |
|
||||||
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; |
|
||||||
|
|
||||||
} |
|
||||||
#endif /* CM_SPD_DETECT */ |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
@ -1,214 +0,0 @@ |
|||||||
/* |
|
||||||
* Board specific setup info |
|
||||||
* |
|
||||||
* (C) Copyright 2003, ARM Ltd. |
|
||||||
* Philippe Robin, <philippe.robin@arm.com>
|
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <config.h> |
|
||||||
#include <version.h> |
|
||||||
|
|
||||||
/* Reset using CM control register */ |
|
||||||
.global reset_cpu
|
|
||||||
reset_cpu: |
|
||||||
mov r0, #CM_BASE |
|
||||||
ldr r1,[r0,#OS_CTRL] |
|
||||||
orr r1,r1,#CMMASK_RESET |
|
||||||
str r1,[r0,#OS_CTRL] |
|
||||||
|
|
||||||
reset_failed: |
|
||||||
b reset_failed |
|
||||||
|
|
||||||
/* Set up the platform, once the cpu has been initialized */ |
|
||||||
.globl lowlevel_init
|
|
||||||
lowlevel_init: |
|
||||||
/* If U-Boot has been run after the ARM boot monitor |
|
||||||
* then all the necessary actions have been done |
|
||||||
* otherwise we are running from user flash mapped to 0x00000000 |
|
||||||
* --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- |
|
||||||
* Changes to the (possibly soft) reset defaults of the processor |
|
||||||
* itself should be performed in cpu/arm<>/start.S |
|
||||||
* This function affects only the core module or board settings |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_INIT |
|
||||||
/* CM has an initialization register |
|
||||||
* - bits in it are wired into test-chip pins to force |
|
||||||
* reset defaults |
|
||||||
* - may need to change its contents for U-Boot |
|
||||||
*/ |
|
||||||
|
|
||||||
/* set the desired CM specific value */ |
|
||||||
mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ |
|
||||||
|
|
||||||
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) |
|
||||||
orr r2,r2,#CMMASK_INIT_102 |
|
||||||
#else |
|
||||||
|
|
||||||
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ |
|
||||||
!defined (CONFIG_CM940T) |
|
||||||
/* CMxx6 code */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_MULTIPLE_SSRAM |
|
||||||
/* set simple mapping */ |
|
||||||
and r2,r2,#CMMASK_MAP_SIMPLE |
|
||||||
#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_TCRAM |
|
||||||
/* disable TCRAM */ |
|
||||||
and r2,r2,#CMMASK_TCRAM_DISABLE |
|
||||||
#endif /* #ifdef CONFIG_CM_TCRAM */ |
|
||||||
|
|
||||||
#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ |
|
||||||
defined (CONFIG_CM1136JF_S) |
|
||||||
|
|
||||||
and r2,r2,#CMMASK_LE |
|
||||||
|
|
||||||
#endif /* cpu with little endian initialization */ |
|
||||||
|
|
||||||
orr r2,r2,#CMMASK_CMxx6_COMMON |
|
||||||
|
|
||||||
#endif /* CMxx6 code */ |
|
||||||
|
|
||||||
#endif /* ARM102xxE value */ |
|
||||||
|
|
||||||
/* read CM_INIT */ |
|
||||||
mov r0, #CM_BASE |
|
||||||
ldr r1, [r0, #OS_INIT] |
|
||||||
/* check against desired bit setting */ |
|
||||||
and r3,r1,r2 |
|
||||||
cmp r3,r2 |
|
||||||
beq init_reg_OK |
|
||||||
|
|
||||||
/* lock for change */ |
|
||||||
mov r3, #CMVAL_LOCK1 |
|
||||||
and r3, r3, #CMVAL_LOCK2 |
|
||||||
str r3, [r0, #OS_LOCK] |
|
||||||
/* set desired value */ |
|
||||||
orr r1,r1,r2 |
|
||||||
/* write & relock CM_INIT */ |
|
||||||
str r1, [r0, #OS_INIT] |
|
||||||
mov r1, #CMVAL_UNLOCK |
|
||||||
str r1, [r0, #OS_LOCK] |
|
||||||
|
|
||||||
/* soft reset so new values used */ |
|
||||||
b reset_cpu |
|
||||||
|
|
||||||
init_reg_OK: |
|
||||||
|
|
||||||
#endif /* CONFIG_CM_INIT */ |
|
||||||
|
|
||||||
mov pc, lr |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_SPD_DETECT |
|
||||||
/* Fast memory is available for the DRAM data |
|
||||||
* - ensure it has been transferred, then summarize the data |
|
||||||
* into a CM register |
|
||||||
*/ |
|
||||||
.globl dram_query
|
|
||||||
dram_query: |
|
||||||
stmfd r13!,{r4-r6,lr} |
|
||||||
/* set up SDRAM info */ |
|
||||||
/* - based on example code from the CM User Guide */ |
|
||||||
mov r0, #CM_BASE |
|
||||||
|
|
||||||
readspdbit: |
|
||||||
ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ |
|
||||||
and r1, r1, #0x20 /* mask SPD bit (5) */ |
|
||||||
cmp r1, #0x20 /* test if set */ |
|
||||||
bne readspdbit |
|
||||||
|
|
||||||
setupsdram: |
|
||||||
add r0, r0, #OS_SPD /* address the copy of the SDP data */ |
|
||||||
ldrb r1, [r0, #3] /* number of row address lines */ |
|
||||||
ldrb r2, [r0, #4] /* number of column address lines */ |
|
||||||
ldrb r3, [r0, #5] /* number of banks */ |
|
||||||
ldrb r4, [r0, #31] /* module bank density */ |
|
||||||
mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ |
|
||||||
mov r5, r5, ASL#2 /* size in MB */ |
|
||||||
mov r0, #CM_BASE /* reload for later code */ |
|
||||||
cmp r5, #0x10 /* is it 16MB? */ |
|
||||||
bne not16 |
|
||||||
mov r6, #0x2 /* store size and CAS latency of 2 */ |
|
||||||
b writesize |
|
||||||
|
|
||||||
not16: |
|
||||||
cmp r5, #0x20 /* is it 32MB? */ |
|
||||||
bne not32 |
|
||||||
mov r6, #0x6 |
|
||||||
b writesize |
|
||||||
|
|
||||||
not32: |
|
||||||
cmp r5, #0x40 /* is it 64MB? */ |
|
||||||
bne not64 |
|
||||||
mov r6, #0xa |
|
||||||
b writesize |
|
||||||
|
|
||||||
not64: |
|
||||||
cmp r5, #0x80 /* is it 128MB? */ |
|
||||||
bne not128 |
|
||||||
mov r6, #0xe |
|
||||||
b writesize |
|
||||||
|
|
||||||
not128: |
|
||||||
/* if it is none of these sizes then it is either 256MB, or |
|
||||||
* there is no SDRAM fitted so default to 256MB |
|
||||||
*/ |
|
||||||
mov r6, #0x12 |
|
||||||
|
|
||||||
writesize: |
|
||||||
mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ |
|
||||||
orr r2, r1, r2, ASL#12 /* OR in column address lines */ |
|
||||||
orr r3, r2, r3, ASL#16 /* OR in number of banks */ |
|
||||||
orr r6, r6, r3 /* OR in size and CAS latency */ |
|
||||||
str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ |
|
||||||
|
|
||||||
#endif /* #ifdef CONFIG_CM_SPD_DETECT */ |
|
||||||
|
|
||||||
ldmfd r13!,{r4-r6,pc} /* back to caller */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CM_REMAP |
|
||||||
/* CM remap bit is operational |
|
||||||
* - use it to map writeable memory at 0x00000000, in place of flash |
|
||||||
*/ |
|
||||||
.globl cm_remap
|
|
||||||
cm_remap: |
|
||||||
stmfd r13!,{r4-r10,lr} |
|
||||||
|
|
||||||
mov r0, #CM_BASE |
|
||||||
ldr r1, [r0, #OS_CTRL] |
|
||||||
orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ |
|
||||||
str r1, [r0, #OS_CTRL] |
|
||||||
|
|
||||||
/* Now 0x00000000 is writeable, replace the vectors */ |
|
||||||
ldr r0, =_start /* r0 <- start of vectors */ |
|
||||||
ldr r2, =_armboot_start /* r2 <- past vectors */ |
|
||||||
sub r1,r1,r1 /* destination 0x00000000 */ |
|
||||||
|
|
||||||
copy_vec: |
|
||||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
|
||||||
stmia r1!, {r3-r10} /* copy to target address [r1] */ |
|
||||||
cmp r0, r2 /* until source end address [r2] */ |
|
||||||
ble copy_vec |
|
||||||
|
|
||||||
ldmfd r13!,{r4-r10,pc} /* back to caller */ |
|
||||||
|
|
||||||
#endif /* #ifdef CONFIG_CM_REMAP */ |
|
||||||
@ -1,110 +0,0 @@ |
|||||||
#!/bin/sh |
|
||||||
# --------------------------------------------------------- |
|
||||||
# Set the platform defines |
|
||||||
# --------------------------------------------------------- |
|
||||||
echo -n "/* Integrator configuration implied " > tmp.fil |
|
||||||
echo " by Makefile target */" >> tmp.fil |
|
||||||
echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil |
|
||||||
echo " /* Integrator board */" >> tmp.fil |
|
||||||
echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil |
|
||||||
echo " 1 /* Integrator/CP */" >> tmp.fil |
|
||||||
|
|
||||||
cpu="arm_intcm" |
|
||||||
variant="unknown core module" |
|
||||||
|
|
||||||
if [ "$1" = "" ] |
|
||||||
then |
|
||||||
echo "$0:: No parameters - using arm_intcm" |
|
||||||
else |
|
||||||
case "$1" in |
|
||||||
ap966) |
|
||||||
cpu="arm_intcm" |
|
||||||
variant="unported core module CM966E-S" |
|
||||||
;; |
|
||||||
|
|
||||||
ap922_config) |
|
||||||
cpu="arm_intcm" |
|
||||||
variant="unported core module CM922T" |
|
||||||
;; |
|
||||||
|
|
||||||
integratorcp_config | \ |
|
||||||
cp_config) |
|
||||||
cpu="arm_intcm" |
|
||||||
variant="unspecified core module" |
|
||||||
;; |
|
||||||
|
|
||||||
cp922_XA10_config) |
|
||||||
cpu="arm_intcm" |
|
||||||
variant="unported core module CM922T_XA10" |
|
||||||
echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil |
|
||||||
echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil |
|
||||||
;; |
|
||||||
|
|
||||||
cp920t_config) |
|
||||||
cpu="arm920t" |
|
||||||
variant="Core module CM920T" |
|
||||||
echo -n "#define CONFIG_CM920T" >> tmp.fil |
|
||||||
echo " 1 /* CPU core is ARM920T */" >> tmp.fil |
|
||||||
;; |
|
||||||
|
|
||||||
cp926ejs_config) |
|
||||||
cpu="arm926ejs" |
|
||||||
variant="Core module CM926EJ-S" |
|
||||||
echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil |
|
||||||
echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil |
|
||||||
;; |
|
||||||
|
|
||||||
|
|
||||||
cp946es_config) |
|
||||||
cpu="arm946es" |
|
||||||
variant="Core module CM946E-S" |
|
||||||
echo -n "#define CONFIG_CM946E_S" >> tmp.fil |
|
||||||
echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil |
|
||||||
;; |
|
||||||
|
|
||||||
cp1136_config) |
|
||||||
cpu="arm1136" |
|
||||||
variant="Core module CM1136EJF-S" |
|
||||||
echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil |
|
||||||
echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil |
|
||||||
;; |
|
||||||
|
|
||||||
*) |
|
||||||
echo "$0:: Unknown core module" |
|
||||||
variant="unknown core module" |
|
||||||
cpu="arm_intcm" |
|
||||||
;; |
|
||||||
|
|
||||||
esac |
|
||||||
|
|
||||||
fi |
|
||||||
|
|
||||||
if [ "$cpu" = "arm_intcm" ] |
|
||||||
then |
|
||||||
echo "/* Core module undefined/not ported */" >> tmp.fil |
|
||||||
echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil |
|
||||||
echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil |
|
||||||
echo -n " /* CM may not have " >> tmp.fil |
|
||||||
echo "multiple SSRAM mapping */" >> tmp.fil |
|
||||||
echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil |
|
||||||
echo -n " /* CM may not support SPD " >> tmp.fil |
|
||||||
echo "query */" >> tmp.fil |
|
||||||
echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil |
|
||||||
echo -n " /* CM may not support " >> tmp.fil |
|
||||||
echo "remapping */" >> tmp.fil |
|
||||||
echo -n "#undef CONFIG_CM_INIT " >> tmp.fil |
|
||||||
echo -n " /* CM may not have " >> tmp.fil |
|
||||||
echo "initialization reg */" >> tmp.fil |
|
||||||
echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil |
|
||||||
echo " /* CM may not have TCRAM */" >> tmp.fil |
|
||||||
fi |
|
||||||
|
|
||||||
mkdir -p ${obj}include |
|
||||||
mkdir -p ${obj}board/armltd/integratorcp |
|
||||||
mv tmp.fil ${obj}include/config.h |
|
||||||
# --------------------------------------------------------- |
|
||||||
# Complete the configuration |
|
||||||
# --------------------------------------------------------- |
|
||||||
$MKCONFIG -a integratorcp arm $cpu integratorcp armltd; |
|
||||||
echo "Variant:: $variant with core $cpu" |
|
||||||
|
|
||||||
Loading…
Reference in new issue