Add evaluation board "adp-ag101" configuration file adp-ag101.h. Add adp-ag101.c board config and related settings. Add board adp-ag101 into boards.cfg Signed-off-by: Macpaul Lin <macpaul@andestech.com>master
Macpaul Lin
13 years ago
committed by
Wolfgang Denk
parent
64d614617f
commit
5f1719c105
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#
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# Copyright (C) 2011 Andes Technology Corporation
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# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := adp-ag101.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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/*
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <faraday/ftsdc010.h> |
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#include <faraday/ftsmc020.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscellaneous platform dependent initializations |
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*/ |
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int board_init(void) |
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{ |
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/*
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* refer to BOOT_PARAMETER_PA_BASE within |
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* "linux/arch/nds32/include/asm/misc_spec.h" |
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*/ |
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gd->bd->bi_arch_number = MACH_TYPE_ADPAG101; |
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gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; |
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ftsmc020_init(); /* initialize Flash */ |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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unsigned long sdram_base = PHYS_SDRAM_0; |
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unsigned long expected_size = PHYS_SDRAM_0_SIZE; |
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unsigned long actual_size; |
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actual_size = get_ram_size((void *)sdram_base, expected_size); |
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gd->ram_size = actual_size; |
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if (expected_size != actual_size) { |
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n", |
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actual_size >> 20, expected_size >> 20); |
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} |
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return 0; |
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} |
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int board_eth_init(bd_t *bd) |
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{ |
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return ftmac100_initialize(bd); |
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} |
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) |
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{ |
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if (banknum == 0) { /* non-CFI boot flash */ |
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info->portwidth = FLASH_CFI_8BIT; |
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info->chipwidth = FLASH_CFI_BY8; |
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info->interface = FLASH_CFI_X8; |
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return 1; |
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} else { |
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return 0; |
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} |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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ftsdc010_mmc_init(0); |
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return 0; |
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} |
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@ -0,0 +1,406 @@ |
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/*
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/arch/ag101.h> |
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/*
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* CPU and Board Configuration Options |
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*/ |
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#define CONFIG_ADP_AG101 |
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#define CONFIG_USE_INTERRUPT |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_MEM_REMAP |
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#endif |
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_SYS_TEXT_BASE 0x03200000 |
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#else |
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#define CONFIG_SYS_TEXT_BASE 0x00000000 |
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#endif |
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/*
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* Timer |
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*/ |
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/*
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* According to the discussion in u-boot mailing list before, |
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* CONFIG_SYS_HZ at 1000 is mandatory. |
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*/ |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_SYS_CLK_FREQ 48000000 |
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#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ |
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/*
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* Use Externel CLOCK or PCLK |
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*/ |
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#undef CONFIG_FTRTC010_EXTCLK |
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#ifndef CONFIG_FTRTC010_EXTCLK |
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#define CONFIG_FTRTC010_PCLK |
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#endif |
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#ifdef CONFIG_FTRTC010_EXTCLK |
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#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ |
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#else |
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#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ |
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#endif |
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#define TIMER_LOAD_VAL 0xffffffff |
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/*
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* Real Time Clock |
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*/ |
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#define CONFIG_RTC_FTRTC010 |
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/*
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* Real Time Clock Divider |
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* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
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*/ |
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#define OSC_5MHZ (5*1000000) |
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#define OSC_CLK (2*OSC_5MHZ) |
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#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
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/*
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* Serial console configuration |
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*/ |
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/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ |
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#define CONFIG_BAUDRATE 38400 |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE |
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#define CONFIG_SYS_NS16550_REG_SIZE -4 |
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#define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */ |
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/* valid baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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/*
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* Ethernet |
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*/ |
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#define CONFIG_FTMAC100 |
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#define CONFIG_BOOTDELAY 3 |
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/*
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* SD (MMC) controller |
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*/ |
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#define CONFIG_MMC |
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#define CONFIG_CMD_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_FTSDC010 |
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#define CONFIG_FTSDC010_NUMBER 1 |
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#define CONFIG_CMD_FAT |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_PING |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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/* Print Buffer Size */ |
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#define CONFIG_SYS_PBSIZE \ |
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
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/* max number of command args */ |
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#define CONFIG_SYS_MAXARGS 16 |
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/* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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/*
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* Stack sizes |
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* |
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* The stack sizes are set up in start.S using the settings below |
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*/ |
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ |
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/*
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* Size of malloc() pool |
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*/ |
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/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ |
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#define CONFIG_SYS_MALLOC_LEN (512 << 10) |
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/*
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* size in bytes reserved for initial data |
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*/ |
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#define CONFIG_SYS_GBL_DATA_SIZE 128 |
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/*
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* AHB Controller configuration |
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*/ |
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#define CONFIG_FTAHBC020S |
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#ifdef CONFIG_FTAHBC020S |
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#include <faraday/ftahbc020s.h> |
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/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ |
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#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 |
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/*
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* CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, |
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* hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote |
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* in C language. |
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*/ |
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#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ |
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(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
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FTAHBC020S_SLAVE_BSR_SIZE(0xb)) |
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#endif |
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/*
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* Watchdog |
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*/ |
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#define CONFIG_FTWDT010_WATCHDOG |
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/*
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* PMU Power controller configuration |
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*/ |
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#define CONFIG_PMU |
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#define CONFIG_FTPMU010_POWER |
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#ifdef CONFIG_FTPMU010_POWER |
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#include <faraday/ftpmu010.h> |
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#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E |
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#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ |
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FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
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FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
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FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
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FTPMU010_SDRAMHTC_CKE_DCSR | \
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FTPMU010_SDRAMHTC_DQM_DCSR | \
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FTPMU010_SDRAMHTC_SDCLK_DCSR) |
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#endif |
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/*
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* SDRAM controller configuration |
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*/ |
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#define CONFIG_FTSDMC021 |
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#ifdef CONFIG_FTSDMC021 |
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#include <faraday/ftsdmc021.h> |
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#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \ |
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FTSDMC021_TP1_TRCD(1) | \
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FTSDMC021_TP1_TRF(3) | \
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FTSDMC021_TP1_TWR(1) | \
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FTSDMC021_TP1_TCL(2)) |
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#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ |
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FTSDMC021_TP2_INI_REFT(8) | \
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FTSDMC021_TP2_REF_INTV(0x180)) |
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/*
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* CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, |
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* hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in |
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* C language. |
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*/ |
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#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ |
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FTSDMC021_CR1_DSZ(3) | \
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FTSDMC021_CR1_MBW(2) | \
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FTSDMC021_CR1_BNKSIZE(6)) |
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#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ |
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FTSDMC021_CR2_IREF | \
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FTSDMC021_CR2_ISMR) |
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#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE |
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#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ |
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CONFIG_SYS_FTSDMC021_BANK0_BASE) |
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#endif |
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/*
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* Physical Memory Map |
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*/ |
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#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) |
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#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ |
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#if defined(CONFIG_MEM_REMAP) |
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#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ |
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#endif |
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#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ |
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#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ |
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#endif |
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
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#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ |
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 |
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#ifdef CONFIG_MEM_REMAP |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ |
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GENERATED_GBL_DATA_SIZE) |
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#else |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ |
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GENERATED_GBL_DATA_SIZE) |
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#endif /* CONFIG_MEM_REMAP */ |
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/*
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* Load address and memory test area should agree with |
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* arch/nds32/config.mk. Be careful not to overwrite U-boot itself. |
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*/ |
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#define CONFIG_SYS_LOAD_ADDR 0x300000 |
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/* memtest works on 63 MB in DRAM */ |
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 |
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) |
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/*
|
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* Static memory controller configuration |
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*/ |
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#define CONFIG_FTSMC020 |
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#ifdef CONFIG_FTSMC020 |
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#include <faraday/ftsmc020.h> |
||||||
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_SYS_FTSMC020_CONFIGS { \ |
||||||
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{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
|
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{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
|
||||||
|
} |
||||||
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#else |
||||||
|
#define CONFIG_SYS_FTSMC020_CONFIGS { \ |
||||||
|
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
|
||||||
|
} |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* There are 2 bank connected to FTSMC020 on ADP-AG101. |
||||||
|
* You can use jumper and switch to force it booted from ROM or FLASH. |
||||||
|
* MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH. |
||||||
|
* MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled. |
||||||
|
*/ |
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ |
||||||
|
#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ |
||||||
|
FTSMC020_BANK_SIZE_32M | \
|
||||||
|
FTSMC020_BANK_MBW_32) |
||||||
|
|
||||||
|
#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ |
||||||
|
FTSMC020_TPR_AST(1) | \
|
||||||
|
FTSMC020_TPR_CTW(1) | \
|
||||||
|
FTSMC020_TPR_ATI(1) | \
|
||||||
|
FTSMC020_TPR_AT2(1) | \
|
||||||
|
FTSMC020_TPR_WTC(1) | \
|
||||||
|
FTSMC020_TPR_AHT(1) | \
|
||||||
|
FTSMC020_TPR_TRNA(1)) |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* This FTSMC020_BANK0_CONFIG indecates the setting of BANK0. |
||||||
|
* 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM, |
||||||
|
* Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition. |
||||||
|
* 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH. |
||||||
|
*/ |
||||||
|
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_SIZE_32M | \ |
||||||
|
FTSMC020_BANK_MBW_32) |
||||||
|
|
||||||
|
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ |
||||||
|
FTSMC020_TPR_AST(3) | \
|
||||||
|
FTSMC020_TPR_CTW(3) | \
|
||||||
|
FTSMC020_TPR_ATI(0xf) | \
|
||||||
|
FTSMC020_TPR_AT2(3) | \
|
||||||
|
FTSMC020_TPR_WTC(3) | \
|
||||||
|
FTSMC020_TPR_AHT(3) | \
|
||||||
|
FTSMC020_TPR_TRNA(0xf)) |
||||||
|
|
||||||
|
#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ |
||||||
|
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
|
||||||
|
FTSMC020_BANK_SIZE_32M | \
|
||||||
|
FTSMC020_BANK_MBW_32) |
||||||
|
|
||||||
|
#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_RBE | \ |
||||||
|
FTSMC020_TPR_AST(1) | \
|
||||||
|
FTSMC020_TPR_CTW(1) | \
|
||||||
|
FTSMC020_TPR_ATI(1) | \
|
||||||
|
FTSMC020_TPR_AT2(1) | \
|
||||||
|
FTSMC020_TPR_WTC(1) | \
|
||||||
|
FTSMC020_TPR_AHT(1) | \
|
||||||
|
FTSMC020_TPR_TRNA(1)) |
||||||
|
#endif /* CONFIG_FTSMC020 */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH and environment organization |
||||||
|
*/ |
||||||
|
/* use CFI framework */ |
||||||
|
#define CONFIG_SYS_FLASH_CFI |
||||||
|
#define CONFIG_FLASH_CFI_DRIVER |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||||
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||||
|
|
||||||
|
/* support JEDEC */ |
||||||
|
|
||||||
|
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ |
||||||
|
#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
||||||
|
#define PHYS_FLASH_1 0x80400000 /* BANK 1 */ |
||||||
|
#else /* !CONFIG_SKIP_LOWLEVEL_INIT */ |
||||||
|
#ifdef CONFIG_MEM_REMAP |
||||||
|
#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ |
||||||
|
#else |
||||||
|
#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ |
||||||
|
#endif /* CONFIG_MEM_REMAP */ |
||||||
|
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||||
|
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } |
||||||
|
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ |
||||||
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ |
||||||
|
|
||||||
|
/* max number of memory banks */ |
||||||
|
/*
|
||||||
|
* There are 4 banks supported for this Controller, |
||||||
|
* but we have only 1 bank connected to flash on board |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||||
|
|
||||||
|
/* max number of sectors on one chip */ |
||||||
|
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) |
||||||
|
#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE |
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 128 |
||||||
|
|
||||||
|
/* environments */ |
||||||
|
#define CONFIG_ENV_IS_IN_FLASH |
||||||
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
||||||
|
#define CONFIG_ENV_SIZE 8192 |
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue