Tom Rini
7 years ago
commit
5f78786499
@ -0,0 +1,135 @@ |
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/* |
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* Copyright 2018 |
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
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* |
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* SPDX-License-Identifier: GPL-2.0+ or X11 |
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*/ |
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|
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/dts-v1/; |
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#include <dt-bindings/gpio/gpio.h> |
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#include "imx53.dtsi" |
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#include "imx53-pinfunc.h" |
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|
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/ { |
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model = "K+P iMX53"; |
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compatible = "kp,imx53-kp", "fsl,imx53"; |
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|
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chosen { |
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stdout-path = &uart2; |
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}; |
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}; |
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&fec { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_eth>; |
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phy-mode = "rmii"; |
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phy-reset-gpios = <&gpio7 6 0>; |
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status = "okay"; |
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}; |
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|
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&i2c2 { |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c2>; |
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pinctrl-1 = <&pinctrl_i2c2_gpio>; |
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clock_frequency = <100000>; |
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|
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scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; |
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sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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pmic: mc34708@8 { |
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compatible = "fsl,mc34708"; |
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reg = <0x8>; |
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}; |
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}; |
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|
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&i2c3 { |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c3>; |
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pinctrl-1 = <&pinctrl_i2c3_gpio>; |
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clock_frequency = <100000>; |
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|
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scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
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sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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}; |
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|
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&iomuxc { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_hog>; |
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|
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imx53-kp { |
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pinctrl_eth: ethgrp { |
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fsl,pins = < |
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc |
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MX53_PAD_FEC_MDC__FEC_MDC 0x4 |
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 |
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 |
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 |
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 |
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 |
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 |
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/* The RX_ER pin needs to be pull down */ |
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/* for this device */ |
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0 |
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 |
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>; |
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}; |
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|
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pinctrl_hog: hoggrp { |
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fsl,pins = < |
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/* PHY RESET */ |
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MX53_PAD_PATA_DA_0__GPIO7_6 0x182 |
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/* VBUS_PWR_EN */ |
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MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4 |
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/* BOOSTER_OFF */ |
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MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 |
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>; |
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}; |
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|
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pinctrl_i2c2: i2c2grp { |
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fsl,pins = < |
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MX53_PAD_KEY_ROW3__I2C2_SDA |
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(0x1ee | IMX_PAD_SION) |
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MX53_PAD_KEY_COL3__I2C2_SCL |
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(0x1ee | IMX_PAD_SION) |
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>; |
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}; |
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|
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pinctrl_i2c2_gpio: i2c2grpgpio { |
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fsl,pins = < |
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MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4 |
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MX53_PAD_KEY_COL3__GPIO4_12 0x1e4 |
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>; |
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}; |
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|
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pinctrl_i2c3: i2c3grp { |
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fsl,pins = < |
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MX53_PAD_GPIO_6__I2C3_SDA (0x1ee | IMX_PAD_SION) |
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MX53_PAD_GPIO_5__I2C3_SCL (0x1ee | IMX_PAD_SION) |
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>; |
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}; |
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|
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pinctrl_i2c3_gpio: i2c3grpgpio { |
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fsl,pins = < |
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MX53_PAD_GPIO_6__GPIO1_6 0x1e4 |
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MX53_PAD_GPIO_5__GPIO1_5 0x1e4 |
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>; |
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}; |
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|
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pinctrl_uart2: uart2grp { |
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fsl,pins = < |
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 |
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 |
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>; |
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}; |
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}; |
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}; |
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|
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&uart2 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart2>; |
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status = "okay"; |
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}; |
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@ -0,0 +1,11 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-icore-u-boot.dtsi" |
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|
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&usdhc3 { |
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u-boot,dm-spl; |
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}; |
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@ -0,0 +1,7 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-icore-rqs-u-boot.dtsi" |
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@ -0,0 +1,7 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-icore-u-boot.dtsi" |
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@ -0,0 +1,15 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include "imx6qdl-u-boot.dtsi" |
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&usdhc3 { |
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u-boot,dm-spl; |
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}; |
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&pinctrl_usdhc3 { |
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u-boot,dm-spl; |
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}; |
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@ -0,0 +1,225 @@ |
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright (C) 2018 BTicino |
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* Copyright (C) 2018 Amarula Solutions B.V. |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/gpio/gpio.h> |
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#include "imx6dl.dtsi" |
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/ { |
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model = "BTicino i.MX6DL Mamoj board"; |
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compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; |
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}; |
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&fec { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_enet>; |
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phy-mode = "mii"; |
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status = "okay"; |
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}; |
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&i2c3 { |
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clock-frequency = <400000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c3>; |
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status = "okay"; |
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}; |
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&i2c4 { |
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clock-frequency = <100000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c4>; |
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status = "okay"; |
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pmic: pfuze100@08 { |
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compatible = "fsl,pfuze100"; |
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reg = <0x08>; |
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regulators { |
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/* CPU vdd_arm core */ |
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sw1a_reg: sw1ab { |
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regulator-min-microvolt = <300000>; |
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regulator-max-microvolt = <1875000>; |
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regulator-boot-on; |
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regulator-always-on; |
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regulator-ramp-delay = <6250>; |
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}; |
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|
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/* SOC vdd_soc */ |
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sw1c_reg: sw1c { |
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regulator-min-microvolt = <300000>; |
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regulator-max-microvolt = <1875000>; |
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regulator-boot-on; |
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regulator-always-on; |
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regulator-ramp-delay = <6250>; |
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}; |
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|
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/* I/O power GEN_3V3 */ |
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sw2_reg: sw2 { |
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regulator-min-microvolt = <800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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/* DDR memory */ |
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sw3a_reg: sw3a { |
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regulator-min-microvolt = <400000>; |
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regulator-max-microvolt = <1975000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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/* DDR memory */ |
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sw3b_reg: sw3b { |
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regulator-min-microvolt = <400000>; |
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regulator-max-microvolt = <1975000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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/* not used */ |
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sw4_reg: sw4 { |
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regulator-min-microvolt = <800000>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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/* not used */ |
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swbst_reg: swbst { |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5150000>; |
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}; |
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/* PMIC vsnvs. EX boot mode */ |
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snvs_reg: vsnvs { |
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regulator-min-microvolt = <1000000>; |
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regulator-max-microvolt = <3000000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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vref_reg: vrefddr { |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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/* not used */ |
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vgen1_reg: vgen1 { |
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regulator-min-microvolt = <800000>; |
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regulator-max-microvolt = <1550000>; |
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}; |
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/* not used */ |
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vgen2_reg: vgen2 { |
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regulator-min-microvolt = <800000>; |
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regulator-max-microvolt = <1550000>; |
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}; |
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|
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/* not used */ |
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vgen3_reg: vgen3 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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|
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/* 1v8 general power */ |
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vgen4_reg: vgen4 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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/* 2v8 general power IMX6 */ |
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vgen5_reg: vgen5 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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/* 3v3 Ethernet */ |
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vgen6_reg: vgen6 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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}; |
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}; |
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}; |
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|
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&uart3 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart3>; |
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status = "okay"; |
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}; |
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|
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&usdhc3 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usdhc3>; |
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bus-width = <8>; |
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non-removable; |
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keep-power-in-suspend; |
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status = "okay"; |
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}; |
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|
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&iomuxc { |
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pinctrl_enet: enetgrp { |
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fsl,pins = < |
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 |
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 |
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 |
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MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 |
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MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 |
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 |
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MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 |
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MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 |
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 |
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 |
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MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 |
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MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 |
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 |
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 |
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MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 |
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MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 |
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>; |
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}; |
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|
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pinctrl_i2c3: i2c3grp { |
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fsl,pins = < |
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MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 |
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>; |
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}; |
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|
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pinctrl_i2c4: i2c4grp { |
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fsl,pins = < |
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MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 |
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MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 |
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>; |
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}; |
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|
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pinctrl_uart3: uart3grp { |
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fsl,pins = < |
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MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
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MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 |
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>; |
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}; |
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|
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pinctrl_usdhc3: usdhc3grp { |
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fsl,pins = < |
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
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MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
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MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
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MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
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MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
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>; |
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}; |
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}; |
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@ -0,0 +1,11 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-icore-u-boot.dtsi" |
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|
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&usdhc3 { |
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u-boot,dm-spl; |
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}; |
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@ -0,0 +1,7 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-icore-rqs-u-boot.dtsi" |
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@ -0,0 +1,7 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-icore-u-boot.dtsi" |
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@ -0,0 +1,23 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-u-boot.dtsi" |
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|
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&usdhc3 { |
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u-boot,dm-spl; |
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}; |
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|
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&usdhc4 { |
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u-boot,dm-spl; |
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}; |
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|
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&pinctrl_usdhc3 { |
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u-boot,dm-spl; |
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}; |
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|
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&pinctrl_usdhc4 { |
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u-boot,dm-spl; |
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}; |
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@ -0,0 +1,19 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6qdl-u-boot.dtsi" |
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|
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&usdhc1 { |
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u-boot,dm-spl; |
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}; |
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|
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&pinctrl_usdhc1 { |
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u-boot,dm-spl; |
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}; |
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|
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&pinctrl_usdhc3 { |
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u-boot,dm-spl; |
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}; |
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@ -0,0 +1,27 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/ { |
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soc { |
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u-boot,dm-spl; |
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|
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aips-bus@02000000 { |
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u-boot,dm-spl; |
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}; |
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|
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aips-bus@02100000 { |
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u-boot,dm-spl; |
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}; |
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}; |
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}; |
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|
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&gpio1 { |
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u-boot,dm-spl; |
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}; |
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|
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&iomuxc { |
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u-boot,dm-spl; |
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}; |
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@ -0,0 +1,25 @@ |
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/* |
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include "imx6ul-u-boot.dtsi" |
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|
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&usdhc1 { |
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u-boot,dm-spl; |
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}; |
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|
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&iomuxc { |
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pinctrl_usdhc1: usdhc1grp { |
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u-boot,dm-spl; |
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}; |
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|
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
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u-boot,dm-spl; |
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}; |
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|
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
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u-boot,dm-spl; |
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}; |
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}; |
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@ -0,0 +1,11 @@ |
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/* |
||||
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "imx6ul-isiot-u-boot.dtsi" |
||||
|
||||
&usdhc2 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
@ -0,0 +1,19 @@ |
||||
/* |
||||
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "imx6ul-u-boot.dtsi" |
||||
|
||||
&usdhc1 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
|
||||
&pinctrl_usdhc1 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
|
||||
&pinctrl_usdhc2 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
@ -0,0 +1,31 @@ |
||||
/* |
||||
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/ { |
||||
soc { |
||||
u-boot,dm-spl; |
||||
}; |
||||
}; |
||||
|
||||
&aips1 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
|
||||
&gpio1 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
|
||||
&gpio4 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
|
||||
&iomuxc { |
||||
u-boot,dm-spl; |
||||
}; |
||||
|
||||
&aips2 { |
||||
u-boot,dm-spl; |
||||
}; |
||||
@ -0,0 +1,34 @@ |
||||
if ARCH_MX31 |
||||
|
||||
config MX31 |
||||
bool |
||||
default y |
||||
choice |
||||
prompt "MX31 board select" |
||||
optional |
||||
|
||||
config TARGET_MX31PDK |
||||
bool "Support the i.MX31 PDK board from Freescale/NXP" |
||||
select BOARD_LATE_INIT |
||||
select SUPPORT_SPL |
||||
select BOARD_EARLY_INIT_F |
||||
|
||||
endchoice |
||||
|
||||
config MX31_HCLK_FREQ |
||||
int "i.MX31 HCLK frequency" |
||||
default 26000000 |
||||
help |
||||
Frequency in Hz of the high frequency input clock. Typically |
||||
26000000 Hz. |
||||
|
||||
config MX31_CLK32 |
||||
int "i.MX31 CLK32 Frequency" |
||||
default 32768 |
||||
help |
||||
Frequency in Hz of the low frequency input clock. Typically |
||||
32768 or 32000 Hz. |
||||
|
||||
source "board/freescale/mx31pdk/Kconfig" |
||||
|
||||
endif |
||||
@ -0,0 +1,12 @@ |
||||
if TARGET_MX6DL_MAMOJ |
||||
|
||||
config SYS_BOARD |
||||
default "mamoj" |
||||
|
||||
config SYS_VENDOR |
||||
default "bticino" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "imx6dl-mamoj" |
||||
|
||||
endif |
||||
@ -0,0 +1,10 @@ |
||||
MX6DL_MAMOJ BOARD |
||||
M: Jagan Teki <jagan@amarulasolutions.com> |
||||
M: Raffaele RECALCATI <raffaele.recalcati@bticino.it> |
||||
M: Simone CIANNI <simone.cianni@bticino.it> |
||||
S: Maintained |
||||
F: board/bticino/mamoj |
||||
F: include/configs/imx6dl-mamoj.h |
||||
F: configs/imx6dl_mamoj_defconfig |
||||
F: arch/arm/dts/imx6dl-mamoj.dts |
||||
F: arch/arm/dts/imx6dl-mamoj-u-boot.dtsi |
||||
@ -0,0 +1,8 @@ |
||||
# Copyright (C) 2018 BTicino
|
||||
# Copyright (C) 2017 Amarula Solutions B.V.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mamoj.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
@ -0,0 +1,124 @@ |
||||
BTicino Mamoj board: |
||||
=================== |
||||
|
||||
Build: |
||||
|
||||
$ make mrproper |
||||
$ make imx6dl_mamoj_defconfig |
||||
$ make |
||||
|
||||
This will generate the SPL image called SPL and the u-boot-dtb.img. |
||||
|
||||
The following methods can be used for booting Mamoj boards: |
||||
|
||||
1. USB SDP boot |
||||
|
||||
2. eMMC boot (via DFU) |
||||
|
||||
3. Falcon mode |
||||
|
||||
1. USB SDP boot: |
||||
--------------- |
||||
|
||||
- Build imx_usb_loader |
||||
|
||||
$ git clone git://github.com/boundarydevices/imx_usb_loader.git |
||||
$ cd imx_usb_loader |
||||
$ make |
||||
|
||||
- Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory |
||||
|
||||
- Put the board in "Serial Download Mode" |
||||
|
||||
- Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host |
||||
|
||||
- Turn-on board |
||||
|
||||
- Identify VID/PID using lsusb |
||||
|
||||
Bus 001 Device 010: ID 15a2:0061 Freescale Semiconductor, Inc. i.MX 6Solo/6DualLite SystemOnChip in RecoveryMode |
||||
|
||||
- Update the conf files |
||||
|
||||
imx_usb.conf |
||||
0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf |
||||
|
||||
mx6_usb_rom.conf |
||||
mx6_usb |
||||
hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000 |
||||
SPL:jump header2 |
||||
|
||||
mx6_usb_sdp_spl.conf |
||||
mx6_spl_sdp |
||||
hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000 |
||||
u-boot-dtb.img:jump header2 |
||||
|
||||
- Launch the loader |
||||
|
||||
$ ./imx_usb |
||||
|
||||
We can see U-Boot boot from USB SDP on minicom |
||||
|
||||
2. eMMC boot via DFU: |
||||
-------------------- |
||||
|
||||
Once booted from USB SDP, program the eMMC as below(make sure to connect USB OTG) |
||||
|
||||
- Change eMMC partition config |
||||
|
||||
=> mmc partconf 2 1 0 0 |
||||
|
||||
- Partition eMMC on host |
||||
|
||||
=> ums 0 mmc 2 |
||||
|
||||
Host will able to detect the eMMC disk as UMS, partition the same. |
||||
|
||||
- Program SPL |
||||
|
||||
=> setenv dfu_alt_info $dfu_alt_info_spl |
||||
=> dfu 0 mmc 2 |
||||
|
||||
At Host |
||||
|
||||
# dfu-util -D SPL -a spl |
||||
|
||||
- Program u-boot-dtb.img |
||||
|
||||
=> setenv dfu_alt_info $dfu_alt_info_uboot |
||||
=> dfu 0 mmc 2 |
||||
|
||||
At Host |
||||
|
||||
# dfu-util -D u-boot-dtb.img -a u-boot |
||||
|
||||
Poweroff and Poweron the board and see U-Boot booting from eMMC. |
||||
|
||||
3. Falcon mode: |
||||
-------------- |
||||
|
||||
- Skip 10M space and create dual partitions for eMMC, start sector is 20480 |
||||
|
||||
Partition Map for MMC device 2 -- Partition Type: DOS |
||||
|
||||
Part Start Sector Num Sectors UUID Type |
||||
1 20480 131072 c52e78be-01 83 |
||||
2 151552 7581696 c52e78be-02 83 |
||||
|
||||
- Write uImage |
||||
|
||||
=> fatload mmc 2:1 $kernel_addr_r uImage |
||||
=> mmc write $kernel_addr_r 0x1000 0x4000 |
||||
|
||||
- Write dtb and args |
||||
|
||||
=> setenv bootargs console=ttymxc2,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw quiet |
||||
=> fatload mmc 2:1 $fdt_addr_r imx6dl-mamoj.dtb |
||||
=> spl export fdt $kernel_addr_r - $fdt_addr_r |
||||
=> mmc write 0x13000000 0x800 0x800 |
||||
|
||||
Poweroff and Poweron the board and see Linux booting directly after SPL. |
||||
|
||||
-- |
||||
Jagan Teki <jagan@amarulasolutions.com> |
||||
03/12/18 |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it> |
||||
* Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it> |
||||
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = imx_ddr_size(); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,172 @@ |
||||
/*
|
||||
* Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it> |
||||
* Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it> |
||||
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
|
||||
#include <asm/io.h> |
||||
#include <linux/sizes.h> |
||||
|
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define IMX6SDL_DRIVE_STRENGTH 0x28 |
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
static iomux_v3_cfg_t const uart3_pads[] = { |
||||
IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
}; |
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT |
||||
int spl_start_uboot(void) |
||||
{ |
||||
/* break into full u-boot on 'c' */ |
||||
if (serial_tstc() && serial_getc() == 'c') |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
||||
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_cas = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_ras = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_reset = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdba2 = 0x00000000, |
||||
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
||||
.grp_ddr_type = 0x000c0000, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
.grp_ddrpke = 0x00000000, |
||||
.grp_addds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
static struct mx6_ddr3_cfg mt41k128m16jt_125 = { |
||||
.mem_speed = 1600, |
||||
.density = 4, |
||||
.width = 32, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
.SRT = 0, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { |
||||
.p0_mpwldectrl0 = 0x0042004b, |
||||
.p0_mpwldectrl1 = 0x0038003c, |
||||
.p0_mpdgctrl0 = 0x42340230, |
||||
.p0_mpdgctrl1 = 0x0228022c, |
||||
.p0_mprddlctl = 0x42444646, |
||||
.p0_mpwrdlctl = 0x38382e2e, |
||||
}; |
||||
|
||||
static struct mx6_ddr_sysinfo mem_dl = { |
||||
.dsize = 1, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 1, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
.refsel = 1, |
||||
.refr = 7, |
||||
}; |
||||
|
||||
static void spl_dram_init(void) |
||||
{ |
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125); |
||||
|
||||
udelay(100); |
||||
} |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
writel(0x00003f3f, &ccm->CCGR0); |
||||
writel(0x0030fc00, &ccm->CCGR1); |
||||
writel(0x000fc000, &ccm->CCGR2); |
||||
writel(0x3f300000, &ccm->CCGR3); |
||||
writel(0xff00f300, &ccm->CCGR4); |
||||
writel(0x0f0000c3, &ccm->CCGR5); |
||||
writel(0x000003cc, &ccm->CCGR6); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
ccgr_init(); |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
gpr_init(); |
||||
|
||||
/* iomux */ |
||||
SETUP_IOMUX_PADS(uart3_pads); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* DDR initialization */ |
||||
spl_dram_init(); |
||||
} |
||||
@ -0,0 +1,15 @@ |
||||
if TARGET_KP_IMX53 |
||||
|
||||
config SYS_BOARD |
||||
default "kp_imx53" |
||||
|
||||
config SYS_VENDOR |
||||
default "k+p" |
||||
|
||||
config SYS_SOC |
||||
default "mx5" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "kp_imx53" |
||||
|
||||
endif |
||||
@ -0,0 +1,6 @@ |
||||
KP_IMX53_HSC BOARD |
||||
M: Lukasz Majewski <lukma@denx.de> |
||||
S: Maintained |
||||
F: board/k+p/kp_imx53/ |
||||
F: include/configs/kp_imx53.h |
||||
F: configs/kp_imx53_defconfig |
||||
@ -0,0 +1,8 @@ |
||||
#
|
||||
# Copyright (C) 2018, DENX Software Engineering
|
||||
# Lukasz Majewski <lukma@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += kp_imx53.o kp_id_rev.o
|
||||
@ -0,0 +1,121 @@ |
||||
/*
|
||||
* Copyright (C) 2018 |
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
||||
* |
||||
* Based on code developed by: |
||||
* |
||||
* Copyright (C) 2012 TQ-Systems GmbH |
||||
* Daniel Gericke <daniel.gericke@tqs.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <environment.h> |
||||
#include <i2c.h> |
||||
#include "kp_id_rev.h" |
||||
|
||||
static int eeprom_has_been_read; |
||||
static struct id_eeprom eeprom; |
||||
|
||||
void show_eeprom(void) |
||||
{ |
||||
char safe_string[33]; |
||||
int i; |
||||
u8 *p; |
||||
|
||||
puts("Module EEPROM:\n"); |
||||
/* ID */ |
||||
for (i = 0; i <= sizeof(eeprom.id) && 0xff != eeprom.id[i]; ++i) |
||||
safe_string[i] = eeprom.id[i]; |
||||
safe_string[i] = '\0'; |
||||
|
||||
if (!strncmp(safe_string, "TQM", 3)) { |
||||
printf(" ID: %s\n", safe_string); |
||||
env_set("boardtype", safe_string); |
||||
} else { |
||||
puts(" unknown hardware variant\n"); |
||||
} |
||||
|
||||
/* Serial number */ |
||||
for (i = 0; (sizeof(eeprom.serial) >= i) && |
||||
(eeprom.serial[i] >= 0x30) && |
||||
(eeprom.serial[i] <= 0x39); ++i) |
||||
safe_string[i] = eeprom.serial[i]; |
||||
safe_string[i] = '\0'; |
||||
|
||||
if (strlen(safe_string) == 8) { |
||||
printf(" SN: %s\n", safe_string); |
||||
env_set("serial#", safe_string); |
||||
} else { |
||||
puts(" unknown serial number\n"); |
||||
} |
||||
|
||||
/* MAC address */ |
||||
p = eeprom.mac; |
||||
if (!is_valid_ethaddr(p)) { |
||||
printf(" Not valid ETH EEPROM addr!\n"); |
||||
return; |
||||
} |
||||
|
||||
printf(" MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", |
||||
p[0], p[1], p[2], p[3], p[4], p[5]); |
||||
|
||||
eth_env_set_enetaddr("ethaddr", p); |
||||
} |
||||
|
||||
int read_eeprom(void) |
||||
{ |
||||
struct udevice *dev; |
||||
int ret; |
||||
|
||||
if (eeprom_has_been_read) |
||||
return 0; |
||||
|
||||
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, |
||||
CONFIG_SYS_I2C_EEPROM_ADDR, |
||||
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); |
||||
if (ret) { |
||||
printf("Cannot find EEPROM !\n"); |
||||
return ret; |
||||
} |
||||
|
||||
ret = dm_i2c_read(dev, 0x0, (uchar *)&eeprom, sizeof(eeprom)); |
||||
|
||||
eeprom_has_been_read = (ret == 0) ? 1 : 0; |
||||
return ret; |
||||
} |
||||
|
||||
int read_board_id(void) |
||||
{ |
||||
unsigned char rev_id = 0x42; |
||||
char rev_str[32], buf[8]; |
||||
struct udevice *dev; |
||||
int ret; |
||||
|
||||
ret = i2c_get_chip_for_busnum(2, 0x22, 1, &dev); |
||||
if (ret) { |
||||
printf("Cannot find pcf8574 IO expander !\n"); |
||||
return ret; |
||||
} |
||||
|
||||
dm_i2c_read(dev, 0x0, &rev_id, sizeof(rev_id)); |
||||
|
||||
sprintf(rev_str, "%02X", rev_id); |
||||
if (rev_id & 0x80) { |
||||
printf("BBoard:4x00 Rev:%s\n", rev_str); |
||||
env_set("boardtype", "ddc"); |
||||
env_set("fit_config", "imx53_kb_conf"); |
||||
} else { |
||||
printf("BBoard:40x0 Rev:%s\n", rev_str); |
||||
env_set("boardtype", "hsc"); |
||||
env_set("fit_config", "imx53_kb_40x0_conf"); |
||||
} |
||||
|
||||
sprintf(buf, "kp-%s", env_get("boardtype")); |
||||
env_set("boardname", buf); |
||||
env_set("boardsoc", "imx53"); |
||||
env_set("kb53_rev", rev_str); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,28 @@ |
||||
/*
|
||||
* Copyright (C) 2018 |
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
||||
* |
||||
* Based on code developed by: |
||||
* |
||||
* Copyright (C) 2012 TQ-Systems GmbH |
||||
* Daniel Gericke <daniel.gericke@tqs.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __KP_ID_REV_H_ |
||||
#define __KP_ID_REV_H_ |
||||
|
||||
struct id_eeprom { |
||||
u8 hrcw_primary[0x20]; |
||||
u8 mac[6]; /* 0x20 ... 0x25 */ |
||||
u8 rsv1[10]; |
||||
u8 serial[8]; /* 0x30 ... 0x37 */ |
||||
u8 rsv2[8]; |
||||
u8 id[0x40]; /* 0x40 ... 0x7f */ |
||||
} __packed; |
||||
|
||||
void show_eeprom(void); |
||||
int read_eeprom(void); |
||||
int read_board_id(void); |
||||
#endif /* __KP_ID_REV_H_ */ |
||||
@ -0,0 +1,212 @@ |
||||
/*
|
||||
* Copyright (C) 2018 |
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/iomux-mx53.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/gpio.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <power/pmic.h> |
||||
#include <fsl_pmic.h> |
||||
#include "kp_id_rev.h" |
||||
|
||||
#define VBUS_PWR_EN IMX_GPIO_NR(7, 8) |
||||
#define PHY_nRST IMX_GPIO_NR(7, 6) |
||||
#define BOOSTER_OFF IMX_GPIO_NR(2, 23) |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
u32 size; |
||||
|
||||
size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
||||
gd->ram_size = size; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; |
||||
struct fuse_bank *bank = &iim->bank[0]; |
||||
struct fuse_bank0_regs *fuse = |
||||
(struct fuse_bank0_regs *)bank->fuse_regs; |
||||
|
||||
int rev = readl(&fuse->gp[6]); |
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; |
||||
} |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX5 |
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN"); |
||||
gpio_direction_output(VBUS_PWR_EN, 1); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
struct fsl_esdhc_cfg esdhc_cfg[] = { |
||||
{MMC_SDHC3_BASE_ADDR}, |
||||
}; |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
return 1; /* eMMC is always present */ |
||||
} |
||||
|
||||
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ |
||||
PAD_CTL_PUS_100K_UP) |
||||
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ |
||||
PAD_CTL_DSE_HIGH) |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int ret; |
||||
|
||||
static const iomux_v3_cfg_t sd3_pads[] = { |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, |
||||
SD_CMD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), |
||||
}; |
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
||||
imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
static int power_init(void) |
||||
{ |
||||
struct udevice *dev; |
||||
int ret; |
||||
|
||||
ret = pmic_get("mc34708", &dev); |
||||
if (ret) { |
||||
printf("%s: mc34708 not found !\n", __func__); |
||||
return ret; |
||||
} |
||||
|
||||
/* Set VDDGP to 1.110V for 800 MHz on SW1 */ |
||||
pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708, |
||||
SWx_1_110V_MC34708); |
||||
|
||||
/* Set VCC as 1.30V on SW2 */ |
||||
pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708, |
||||
SWx_1_300V_MC34708); |
||||
|
||||
/* Set global reset timer to 4s */ |
||||
pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708, |
||||
TIMER_4S_MC34708); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void setup_clocks(void) |
||||
{ |
||||
int ret; |
||||
u32 ref_clk = MXC_HCLK; |
||||
/*
|
||||
* CPU clock set to 800MHz and DDR to 400MHz |
||||
*/ |
||||
ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK); |
||||
if (ret) |
||||
printf("CPU: Switch CPU clock to 800MHZ failed\n"); |
||||
|
||||
ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); |
||||
ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); |
||||
if (ret) |
||||
printf("CPU: Switch DDR clock to 400MHz failed\n"); |
||||
} |
||||
|
||||
static void setup_ups(void) |
||||
{ |
||||
gpio_request(BOOSTER_OFF, "BOOSTER_OFF"); |
||||
gpio_direction_output(BOOSTER_OFF, 0); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Do not overwrite the console |
||||
* Use always serial for U-Boot console |
||||
*/ |
||||
int overwrite_console(void) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void eth_phy_reset(void) |
||||
{ |
||||
gpio_request(PHY_nRST, "PHY_nRST"); |
||||
gpio_direction_output(PHY_nRST, 1); |
||||
udelay(50); |
||||
gpio_set_value(PHY_nRST, 0); |
||||
udelay(400); |
||||
gpio_set_value(PHY_nRST, 1); |
||||
udelay(50); |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
int ret = 0; |
||||
|
||||
setup_ups(); |
||||
|
||||
if (!power_init()) |
||||
setup_clocks(); |
||||
|
||||
ret = read_eeprom(); |
||||
if (ret) |
||||
printf("Error %d reading EEPROM content!\n", ret); |
||||
|
||||
eth_phy_reset(); |
||||
|
||||
show_eeprom(); |
||||
read_board_id(); |
||||
|
||||
return ret; |
||||
} |
||||
@ -1,43 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SYS_TEXT_BASE=0x17800000 |
||||
CONFIG_TARGET_GE_B650V3=y |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_FIT=y |
||||
CONFIG_BOOTDELAY=1 |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y |
||||
CONFIG_SUPPORT_RAW_INITRD=y |
||||
CONFIG_DEFAULT_FDT_FILE="imx6q-b650v3.dtb" |
||||
CONFIG_BOARD_EARLY_INIT_F=y |
||||
CONFIG_LAST_STAGE_INIT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_PCI=y |
||||
CONFIG_CMD_SF=y |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_DOS_PARTITION=y |
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y |
||||
CONFIG_BOOTCOUNT_LIMIT=y |
||||
CONFIG_BOOTCOUNT_EXT=y |
||||
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" |
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 |
||||
CONFIG_FSL_ESDHC=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_CMD_E1000=y |
||||
CONFIG_SPI=y |
||||
CONFIG_MXC_SPI=y |
||||
CONFIG_OF_LIBFDT=y |
||||
# CONFIG_EFI_LOADER is not set |
||||
@ -1,43 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SYS_TEXT_BASE=0x17800000 |
||||
CONFIG_TARGET_GE_B850V3=y |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_FIT=y |
||||
CONFIG_BOOTDELAY=1 |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y |
||||
CONFIG_SUPPORT_RAW_INITRD=y |
||||
CONFIG_DEFAULT_FDT_FILE="imx6q-b850v3.dtb" |
||||
CONFIG_BOARD_EARLY_INIT_F=y |
||||
CONFIG_LAST_STAGE_INIT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_PCI=y |
||||
CONFIG_CMD_SF=y |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_DOS_PARTITION=y |
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y |
||||
CONFIG_BOOTCOUNT_LIMIT=y |
||||
CONFIG_BOOTCOUNT_EXT=y |
||||
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" |
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 |
||||
CONFIG_FSL_ESDHC=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_CMD_E1000=y |
||||
CONFIG_SPI=y |
||||
CONFIG_MXC_SPI=y |
||||
CONFIG_OF_LIBFDT=y |
||||
# CONFIG_EFI_LOADER is not set |
||||
@ -0,0 +1,52 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SYS_TEXT_BASE=0x17800000 |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_TARGET_MX6DL_MAMOJ=y |
||||
CONFIG_SPL_OS_BOOT=y |
||||
# CONFIG_CMD_BMODE is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj" |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_FASTBOOT=y |
||||
CONFIG_FASTBOOT_BUF_ADDR=0x12000000 |
||||
CONFIG_FASTBOOT_BUF_SIZE=0x10000000 |
||||
CONFIG_FASTBOOT_FLASH=y |
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
||||
CONFIG_SYS_PROMPT="=> " |
||||
CONFIG_CRC32_VERIFY=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_PMIC=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_DISTRO_DEFAULTS=y |
||||
CONFIG_ENV_IS_IN_MMC=y |
||||
CONFIG_PHYLIB=y |
||||
CONFIG_PHY_MICREL=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_FSL_ESDHC=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL" |
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_DFU_MMC=y |
||||
CONFIG_IMX_THERMAL=y |
||||
CONFIG_SYS_I2C_MXC=y |
||||
CONFIG_SECURE_BOOT=y |
||||
@ -0,0 +1,40 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX5=y |
||||
CONFIG_SYS_TEXT_BASE=0x77800000 |
||||
CONFIG_TARGET_KP_IMX53=y |
||||
# CONFIG_CMD_BMODE is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" |
||||
CONFIG_FIT=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y |
||||
CONFIG_SUPPORT_RAW_INITRD=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_PART=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_ENV_IS_IN_MMC=y |
||||
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
||||
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 |
||||
CONFIG_PHYLIB=y |
||||
CONFIG_PHY_ADDR=1 |
||||
CONFIG_PHY_SMSC=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX5=y |
||||
# CONFIG_SPL_PMIC_CHILDREN is not set |
||||
CONFIG_DM_PMIC_MC34708=y |
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y |
||||
CONFIG_CONS_INDEX=2 |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_STORAGE=y |
||||
@ -0,0 +1,105 @@ |
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 |
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <fsl_pmic.h> |
||||
#include <i2c.h> |
||||
#include <power/pmic.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static int mc34708_reg_count(struct udevice *dev) |
||||
{ |
||||
return PMIC_NUM_OF_REGS; |
||||
} |
||||
|
||||
static int mc34708_write(struct udevice *dev, uint reg, const u8 *buff, |
||||
int len) |
||||
{ |
||||
u8 buf[3] = { 0 }; |
||||
int ret; |
||||
|
||||
if (len != MC34708_TRANSFER_SIZE) |
||||
return -EINVAL; |
||||
|
||||
/*
|
||||
* The MC34708 sends data with big endian format, hence we need to |
||||
* perform manual byte swap. |
||||
*/ |
||||
buf[0] = buff[2]; |
||||
buf[1] = buff[1]; |
||||
buf[2] = buff[0]; |
||||
|
||||
ret = dm_i2c_write(dev, reg, buf, len); |
||||
if (ret) |
||||
printf("write error to device: %p register: %#x!", dev, reg); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int mc34708_read(struct udevice *dev, uint reg, u8 *buff, int len) |
||||
{ |
||||
u8 buf[3] = { 0 }; |
||||
int ret; |
||||
|
||||
if (len != MC34708_TRANSFER_SIZE) |
||||
return -EINVAL; |
||||
|
||||
ret = dm_i2c_read(dev, reg, buf, len); |
||||
if (ret) |
||||
printf("read error from device: %p register: %#x!", dev, reg); |
||||
|
||||
buff[0] = buf[2]; |
||||
buff[1] = buf[1]; |
||||
buff[2] = buf[0]; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int mc34708_probe(struct udevice *dev) |
||||
{ |
||||
struct uc_pmic_priv *priv = dev_get_uclass_priv(dev); |
||||
|
||||
priv->trans_len = MC34708_TRANSFER_SIZE; |
||||
|
||||
/*
|
||||
* Handle PMIC Errata 37: APS mode not fully functional, |
||||
* use explicit PWM or PFM instead |
||||
*/ |
||||
pmic_clrsetbits(dev, MC34708_REG_SW12_OPMODE, |
||||
MC34708_SW1AMODE_MASK | MC34708_SW2MODE_MASK, |
||||
SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 14u)); |
||||
|
||||
pmic_clrsetbits(dev, MC34708_REG_SW345_OPMODE, |
||||
MC34708_SW3MODE_MASK | MC34708_SW4AMODE_MASK | |
||||
MC34708_SW4BMODE_MASK | MC34708_SW5MODE_MASK, |
||||
SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 6u) | |
||||
(SW_MODE_PWMPWM << 12u) | (SW_MODE_PWMPWM << 18u)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct dm_pmic_ops mc34708_ops = { |
||||
.reg_count = mc34708_reg_count, |
||||
.read = mc34708_read, |
||||
.write = mc34708_write, |
||||
}; |
||||
|
||||
static const struct udevice_id mc34708_ids[] = { |
||||
{ .compatible = "fsl,mc34708" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(pmic_mc34708) = { |
||||
.name = "mc34708_pmic", |
||||
.id = UCLASS_PMIC, |
||||
.of_match = mc34708_ids, |
||||
.probe = mc34708_probe, |
||||
.ops = &mc34708_ops, |
||||
}; |
||||
@ -0,0 +1,102 @@ |
||||
/*
|
||||
* Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it> |
||||
* Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it> |
||||
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* Configuration settings for the BTicion i.MX6DL Mamoj board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __IMX6DL_MAMOJ_CONFIG_H |
||||
#define __IMX6DL_MAMOJ_CONFIG_H |
||||
|
||||
#include <linux/sizes.h> |
||||
#include "mx6_common.h" |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) |
||||
|
||||
/* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE SZ_128K |
||||
|
||||
/* Allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* Environment */ |
||||
#ifndef CONFIG_ENV_IS_NOWHERE |
||||
/* Environment in MMC */ |
||||
# if defined(CONFIG_ENV_IS_IN_MMC) |
||||
# define CONFIG_ENV_OFFSET 0x100000 |
||||
# endif |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"scriptaddr=0x14000000\0" \
|
||||
"fdt_addr_r=0x13000000\0" \
|
||||
"kernel_addr_r=0x10008000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"dfu_alt_info_spl=spl raw 0x2 0x400\0" \
|
||||
"dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
|
||||
BOOTENV |
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \ |
||||
func(MMC, mmc, 2) |
||||
|
||||
#include <config_distro_bootcmd.h> |
||||
#endif |
||||
|
||||
/* UART */ |
||||
#define CONFIG_MXC_UART_BASE UART3_BASE |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_SYS_MMC_ENV_DEV 2 |
||||
#define CONFIG_SUPPORT_EMMC_BOOT |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_FEC_MXC_PHYADDR 1 |
||||
#define CONFIG_MII |
||||
|
||||
/* USB */ |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
|
||||
/* Falcon */ |
||||
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" |
||||
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" |
||||
#define CONFIG_CMD_SPL |
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 |
||||
#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) |
||||
|
||||
/* MMC support: args@1MB kernel@2MB */ |
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ |
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) |
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* SPL */ |
||||
#include "imx6_spl.h" |
||||
|
||||
#endif /* __IMX6DL_MAMOJ_CONFIG_H */ |
||||
@ -0,0 +1,113 @@ |
||||
/*
|
||||
* Copyright (C) 2018 |
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H_ |
||||
#define __CONFIG_H_ |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <linux/sizes.h> |
||||
|
||||
#define CONFIG_SYS_FSL_CLK |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) |
||||
|
||||
/* MMC Configs */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1 |
||||
|
||||
/* Eth Configs */ |
||||
#define CONFIG_MII |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_USB_EHCI_MX5 |
||||
#define CONFIG_MXC_USB_PORT 1 |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
|
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* Command definition */ |
||||
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"console=ttymxc1,115200\0" \
|
||||
"fdt_addr=0x75000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"scriptaddr=0x74000000\0" \
|
||||
"kernel_file=fitImage\0"\
|
||||
"rdinit=/sbin/init\0" \
|
||||
"addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
|
||||
"upd_image=st.4k\0" \
|
||||
"uboot_file=u-boot.imx\0" \
|
||||
"updargs=setenv bootargs console=${console} ${smp}"\
|
||||
"rdinit=${rdinit} ${debug} ${displayargs}\0" \
|
||||
"loadusb=usb start; " \
|
||||
"fatload usb 0 ${loadaddr} ${upd_image}\0" \
|
||||
"up=if tftp ${loadaddr} ${uboot_file}; then " \
|
||||
"setexpr blkc ${filesize} / 0x200; " \
|
||||
"setexpr blkc ${blkc} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${blkc}" \
|
||||
"; fi\0" \
|
||||
"upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
|
||||
"if tftp ${loadaddr} ${wic_file}; then " \
|
||||
"setexpr blkc ${filesize} / 0x200; " \
|
||||
"setexpr blkc ${blkc} + 1; " \
|
||||
"mmc write ${loadaddr} 0x0 ${blkc}" \
|
||||
"; fi\0" \
|
||||
"usbupd=echo Booting update from usb ...; " \
|
||||
"setenv bootargs; " \
|
||||
"run updargs; " \
|
||||
"run loadusb; " \
|
||||
"bootm ${loadaddr}#${fit_config}\0" \
|
||||
BOOTENV |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" |
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \ |
||||
func(MMC, mmc, 0) \
|
||||
func(DHCP, dhcp, na) |
||||
|
||||
#include <config_distro_bootcmd.h> |
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR |
||||
#define PHYS_SDRAM_1_SIZE (512 * SZ_1M) |
||||
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* environment organization */ |
||||
#define CONFIG_ENV_OFFSET (SZ_1M) |
||||
#define CONFIG_ENV_SIZE (SZ_8K) |
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
|
||||
#endif /* __CONFIG_H_ */ |
||||
Loading…
Reference in new issue