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@ -25,6 +25,12 @@ |
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#include <ioports.h> |
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#include <ioports.h> |
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#include <mpc8260.h> |
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#include <mpc8260.h> |
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#if defined(CONFIG_OF_LIBFDT) |
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#include <libfdt.h> |
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#include <libfdt_env.h> |
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#include <fdt_support.h> |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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/*
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@ -38,12 +44,12 @@ const iop_conf_t iop_conf_tab[4][32] = { |
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/* Port A configuration */ |
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/* Port A configuration */ |
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{ /* conf ppar psor pdir podr pdat */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ |
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/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ |
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/* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ |
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/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ |
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/* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ |
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/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ |
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/* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ |
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/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ |
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/* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ |
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/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ |
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/* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ |
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/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ |
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/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ |
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/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ |
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#if defined(CONFIG_SOFT_I2C) |
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#if defined(CONFIG_SOFT_I2C) |
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/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ |
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/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ |
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@ -53,14 +59,14 @@ const iop_conf_t iop_conf_tab[4][32] = { |
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/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ |
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/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ |
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#endif |
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#endif |
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/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ |
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/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ |
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ |
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/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ |
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ |
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/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ |
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ |
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/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ |
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ |
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/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ |
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ |
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/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ |
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ |
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/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ |
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ |
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/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ |
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ |
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/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ |
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/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ |
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/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ |
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/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ |
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/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ |
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/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ |
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/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ |
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@ -79,20 +85,20 @@ const iop_conf_t iop_conf_tab[4][32] = { |
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/* Port B configuration */ |
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/* Port B configuration */ |
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{ /* conf ppar psor pdir podr pdat */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
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/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
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/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
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/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
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/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
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/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
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/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
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/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
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/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
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/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
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/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
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/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
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/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
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/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
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/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ |
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ |
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ |
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ |
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ |
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ |
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@ -123,8 +129,8 @@ const iop_conf_t iop_conf_tab[4][32] = { |
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
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/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ |
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/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ |
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
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/* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ |
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
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/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ |
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ |
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ |
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@ -180,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = { |
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
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/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ |
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/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ |
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/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ |
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/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ |
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ |
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/* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ |
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
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@ -224,7 +230,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, |
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* mapped by the controller. That means, that the initial mapping has |
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* mapped by the controller. That means, that the initial mapping has |
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* to be (at least) twice as large as the maximum expected size. |
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* to be (at least) twice as large as the maximum expected size. |
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*/ |
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*/ |
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maxsize = (1 + (~orx | 0x7fff)) / 2; |
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maxsize = (1 + (~orx | 0x7fff))/* / 2*/; |
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sdmr_ptr = &memctl->memc_psdmr; |
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sdmr_ptr = &memctl->memc_psdmr; |
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orx_ptr = &memctl->memc_or2; |
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orx_ptr = &memctl->memc_or2; |
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@ -315,4 +321,38 @@ nand_init (void) |
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printf ("%4lu MB\n", totlen >>20); |
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printf ("%4lu MB\n", totlen >>20); |
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} |
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} |
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#endif |
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#endif /* CFG_CMD_NAND */ |
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) |
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/*
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* update "memory" property in the blob |
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*/ |
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void ft_blob_update(void *blob, bd_t *bd) |
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{ |
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int ret, nodeoffset = 0; |
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ulong memory_data[2] = {0}; |
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memory_data[0] = cpu_to_be32(bd->bi_memstart); |
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memory_data[1] = cpu_to_be32(bd->bi_memsize); |
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nodeoffset = fdt_find_node_by_path (blob, "/memory"); |
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if (nodeoffset >= 0) { |
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ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, |
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sizeof(memory_data)); |
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if (ret < 0) |
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printf("ft_blob_update): cannot set /memory/reg " |
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"property err:%s\n", fdt_strerror(ret)); |
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} |
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else { |
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/* memory node is required in dts */ |
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printf("ft_blob_update(): cannot find /memory node " |
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"err:%s\n", fdt_strerror(nodeoffset)); |
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} |
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} |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup( blob, bd); |
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ft_blob_update(blob, bd); |
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} |
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ |
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