Rafal Jaworowski
19 years ago
committed by
Rafal Jaworowski
parent
edd6cf20e1
commit
692519b1ed
@ -0,0 +1,593 @@ |
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/*
|
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* (C) Copyright 2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (c) 2005 Cisco Systems. All rights reserved. |
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* Roland Dreier <rolandd@cisco.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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|
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#include <asm/processor.h> |
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#include <asm-ppc/io.h> |
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#include <ppc4xx.h> |
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#include <common.h> |
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#include <pci.h> |
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#include "440spe_pcie.h" |
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#if defined(CONFIG_440SPE) |
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#if defined(CONFIG_PCI) |
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enum { |
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PTYPE_ENDPOINT = 0x0, |
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PTYPE_LEGACY_ENDPOINT = 0x1, |
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PTYPE_ROOT_PORT = 0x4, |
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LNKW_X1 = 0x1, |
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LNKW_X4 = 0x4, |
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LNKW_X8 = 0x8 |
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}; |
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static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, |
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int offset, int len, u32 *val) { |
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*val = 0; |
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/*
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* 440SPE implements only one function per port |
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*/ |
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if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) |
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return 0; |
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devfn = PCI_BDF(0,0,0); |
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offset += devfn << 4; |
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switch (len) { |
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case 1: |
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*val = in_8(hose->cfg_data + offset); |
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break; |
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case 2: |
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*val = in_le16((u16 *)(hose->cfg_data + offset)); |
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break; |
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default: |
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*val = in_le32((u32 *)(hose->cfg_data + offset)); |
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break; |
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} |
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return 0; |
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} |
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static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, |
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int offset, int len, u32 val) { |
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/*
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* 440SPE implements only one function per port |
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*/ |
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if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) |
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return 0; |
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devfn = PCI_BDF(0,0,0); |
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offset += devfn << 4; |
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switch (len) { |
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case 1: |
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out_8(hose->cfg_data + offset, val); |
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break; |
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case 2: |
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out_le16((u16 *)(hose->cfg_data + offset), val); |
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break; |
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default: |
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out_le32((u32 *)(hose->cfg_data + offset), val); |
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break; |
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} |
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return 0; |
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} |
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int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) |
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{ |
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u32 v; |
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int rv; |
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rv = pcie_read_config(hose, dev, offset, 1, &v); |
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*val = (u8)v; |
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return rv; |
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} |
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int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) |
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{ |
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u32 v; |
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int rv; |
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rv = pcie_read_config(hose, dev, offset, 2, &v); |
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*val = (u16)v; |
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return rv; |
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} |
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int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) |
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{ |
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u32 v; |
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int rv; |
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rv = pcie_read_config(hose, dev, offset, 3, &v); |
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*val = (u32)v; |
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return rv; |
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} |
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int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) |
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{ |
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return pcie_write_config(hose,(u32)dev,offset,1,val); |
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} |
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int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) |
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{ |
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return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); |
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} |
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int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) |
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{ |
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return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); |
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} |
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static void ppc440spe_setup_utl(u32 port) { |
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volatile void *utl_base = NULL; |
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/*
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* Map UTL registers |
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*/ |
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switch (port) { |
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case 0: |
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mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d); |
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mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400); |
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mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01); |
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); |
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utl_base = (unsigned int *)(CFG_PCIE1_REGBASE); |
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break; |
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case 1: |
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mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d); |
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mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400); |
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mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01); |
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); |
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utl_base = (unsigned int *)(CFG_PCIE3_REGBASE); |
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break; |
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case 2: |
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mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d); |
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mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400); |
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mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01); |
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); |
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utl_base = (unsigned int *)(CFG_PCIE5_REGBASE); |
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break; |
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} |
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/*
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* Set buffer allocations and then assert VRB and TXE. |
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*/ |
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out_be32(utl_base + PEUTL_OUTTR, 0x08000000); |
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out_be32(utl_base + PEUTL_INTR, 0x02000000); |
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out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); |
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out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); |
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out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); |
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out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); |
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out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); |
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out_be32(utl_base + PEUTL_PCTL, 0x8080007d); |
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} |
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static int check_error(void) |
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{ |
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u32 valPE0, valPE1, valPE2; |
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int err = 0; |
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/* SDR0_PEGPLLLCT1 reset */ |
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if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { |
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printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); |
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} |
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valPE0 = SDR_READ(PESDR0_RCSSET); |
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valPE1 = SDR_READ(PESDR1_RCSSET); |
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valPE2 = SDR_READ(PESDR2_RCSSET); |
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/* SDR0_PExRCSSET rstgu */ |
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if (!(valPE0 & 0x01000000) || |
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!(valPE1 & 0x01000000) || |
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!(valPE2 & 0x01000000)) { |
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printf("PCIE: SDR0_PExRCSSET rstgu error\n"); |
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err = -1; |
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} |
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/* SDR0_PExRCSSET rstdl */ |
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if (!(valPE0 & 0x00010000) || |
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!(valPE1 & 0x00010000) || |
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!(valPE2 & 0x00010000)) { |
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printf("PCIE: SDR0_PExRCSSET rstdl error\n"); |
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err = -1; |
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} |
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/* SDR0_PExRCSSET rstpyn */ |
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if ((valPE0 & 0x00001000) || |
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(valPE1 & 0x00001000) || |
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(valPE2 & 0x00001000)) { |
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printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); |
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err = -1; |
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} |
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/* SDR0_PExRCSSET hldplb */ |
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if ((valPE0 & 0x10000000) || |
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(valPE1 & 0x10000000) || |
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(valPE2 & 0x10000000)) { |
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printf("PCIE: SDR0_PExRCSSET hldplb error\n"); |
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err = -1; |
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} |
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/* SDR0_PExRCSSET rdy */ |
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if ((valPE0 & 0x00100000) || |
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(valPE1 & 0x00100000) || |
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(valPE2 & 0x00100000)) { |
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printf("PCIE: SDR0_PExRCSSET rdy error\n"); |
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err = -1; |
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} |
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/* SDR0_PExRCSSET shutdown */ |
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if ((valPE0 & 0x00000100) || |
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(valPE1 & 0x00000100) || |
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(valPE2 & 0x00000100)) { |
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printf("PCIE: SDR0_PExRCSSET shutdown error\n"); |
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err = -1; |
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} |
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return err; |
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} |
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/*
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* Initialize PCI Express core |
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*/ |
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int ppc440spe_init_pcie(void) |
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{ |
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int time_out = 20; |
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/* Set PLL clock receiver to LVPECL */ |
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SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); |
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if (check_error()) |
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return -1; |
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if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) |
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{ |
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printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", |
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SDR_READ(PESDR0_PLLLCT2)); |
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return -1; |
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} |
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/* De-assert reset of PCIe PLL, wait for lock */ |
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SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); |
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udelay(3); |
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while(time_out) { |
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if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { |
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time_out--; |
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udelay(1); |
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} else |
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break; |
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} |
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if (!time_out) { |
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printf("PCIE: VCO output not locked\n"); |
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return -1; |
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} |
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return 0; |
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} |
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int ppc440spe_init_pcie_rootport(int port) |
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{ |
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static int core_init; |
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volatile u32 val = 0; |
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int attempts; |
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if (!core_init) { |
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++core_init; |
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if (ppc440spe_init_pcie()) |
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return -1; |
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} |
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/*
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* Initialize various parts of the PCI Express core for our port: |
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* |
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* - Set as a root port and enable max width |
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* (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). |
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* - Set up UTL configuration. |
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* - Increase SERDES drive strength to levels suggested by AMCC. |
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* - De-assert RSTPYN, RSTDL and RSTGU. |
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* |
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* NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with |
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* default setting 0x11310000. The register has new fields, |
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* PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core |
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* hang. |
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*/ |
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switch (port) { |
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case 0: |
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SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); |
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SDR_WRITE(PESDR0_UTLSET1, 0x21222222); |
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if (!ppc440spe_revB()) |
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SDR_WRITE(PESDR0_UTLSET2, 0x11000000); |
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SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); |
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SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); |
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SDR_WRITE(PESDR0_RCSSET, |
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(SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); |
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break; |
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case 1: |
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SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); |
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SDR_WRITE(PESDR1_UTLSET1, 0x21222222); |
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if (!ppc440spe_revB()) |
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SDR_WRITE(PESDR1_UTLSET2, 0x11000000); |
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SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); |
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SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); |
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SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); |
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SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); |
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SDR_WRITE(PESDR1_RCSSET, |
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(SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); |
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break; |
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case 2: |
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SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); |
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SDR_WRITE(PESDR2_UTLSET1, 0x21222222); |
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if (!ppc440spe_revB()) |
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SDR_WRITE(PESDR2_UTLSET2, 0x11000000); |
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SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); |
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SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); |
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SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); |
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SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); |
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SDR_WRITE(PESDR2_RCSSET, |
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(SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); |
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break; |
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} |
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/*
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* Notice: the following delay has critical impact on device |
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* initialization - if too short (<50ms) the link doesn't get up. |
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*/ |
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mdelay(100); |
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switch (port) { |
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case 0: val = SDR_READ(PESDR0_RCSSTS); break; |
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case 1: val = SDR_READ(PESDR1_RCSSTS); break; |
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case 2: val = SDR_READ(PESDR2_RCSSTS); break; |
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} |
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if (val & (1 << 20)) { |
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printf("PCIE%d: PGRST failed %08x\n", port, val); |
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return -1; |
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} |
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/*
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* Verify link is up |
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*/ |
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val = 0; |
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switch (port) |
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{ |
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case 0: |
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val = SDR_READ(PESDR0_LOOP); |
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break; |
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case 1: |
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val = SDR_READ(PESDR1_LOOP); |
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break; |
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case 2: |
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val = SDR_READ(PESDR2_LOOP); |
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break; |
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} |
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if (!(val & 0x00001000)) { |
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printf("PCIE%d: link is not up.\n", port); |
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return -1; |
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} |
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/*
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* Setup UTL registers - but only on revA! |
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* We use default settings for revB chip. |
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*/ |
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if (!ppc440spe_revB()) |
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ppc440spe_setup_utl(port); |
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|
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/*
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* We map PCI Express configuration access into the 512MB regions |
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* |
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* NOTICE: revB is very strict about PLB real addressess and ranges to |
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* be mapped for config space; it seems to only work with d_nnnn_nnnn |
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* range (hangs the core upon config transaction attempts when set |
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* otherwise) while revA uses c_nnnn_nnnn. |
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* |
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* For revA: |
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* PCIE0: 0xc_4000_0000 |
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* PCIE1: 0xc_8000_0000 |
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* PCIE2: 0xc_c000_0000 |
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* |
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* For revB: |
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* PCIE0: 0xd_0000_0000 |
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* PCIE1: 0xd_2000_0000 |
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* PCIE2: 0xd_4000_0000 |
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*/ |
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switch (port) { |
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case 0: |
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if (ppc440spe_revB()) { |
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); |
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); |
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} else { |
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/* revA */ |
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); |
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); |
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} |
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ |
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break; |
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|
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case 1: |
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if (ppc440spe_revB()) { |
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); |
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); |
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} else { |
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); |
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); |
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} |
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ |
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break; |
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|
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case 2: |
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if (ppc440spe_revB()) { |
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); |
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); |
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} else { |
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); |
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); |
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} |
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ |
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break; |
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} |
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|
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/*
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* Check for VC0 active and assert RDY. |
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*/ |
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attempts = 10; |
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switch (port) { |
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case 0: |
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while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { |
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if (!(attempts--)) { |
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printf("PCIE0: VC0 not active\n"); |
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return -1; |
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} |
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mdelay(1000); |
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} |
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SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); |
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break; |
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case 1: |
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while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { |
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if (!(attempts--)) { |
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printf("PCIE1: VC0 not active\n"); |
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return -1; |
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} |
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mdelay(1000); |
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} |
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|
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SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); |
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break; |
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case 2: |
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while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { |
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if (!(attempts--)) { |
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printf("PCIE2: VC0 not active\n"); |
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return -1; |
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} |
||||
mdelay(1000); |
||||
} |
||||
|
||||
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); |
||||
break; |
||||
} |
||||
mdelay(100); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void ppc440spe_setup_pcie(struct pci_controller *hose, int port) |
||||
{ |
||||
volatile void *mbase = NULL; |
||||
|
||||
pci_set_ops(hose, |
||||
pcie_read_config_byte, |
||||
pcie_read_config_word, |
||||
pcie_read_config_dword, |
||||
pcie_write_config_byte, |
||||
pcie_write_config_word, |
||||
pcie_write_config_dword); |
||||
|
||||
switch(port) { |
||||
case 0: |
||||
mbase = (u32 *)CFG_PCIE0_XCFGBASE; |
||||
hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; |
||||
break; |
||||
case 1: |
||||
mbase = (u32 *)CFG_PCIE1_XCFGBASE; |
||||
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; |
||||
break; |
||||
case 2: |
||||
mbase = (u32 *)CFG_PCIE2_XCFGBASE; |
||||
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; |
||||
break; |
||||
} |
||||
|
||||
/*
|
||||
* Set bus numbers on our root port |
||||
*/ |
||||
if (ppc440spe_revB()) { |
||||
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); |
||||
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); |
||||
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); |
||||
} else { |
||||
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); |
||||
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); |
||||
} |
||||
|
||||
/*
|
||||
* Set up outbound translation to hose->mem_space from PLB |
||||
* addresses at an offset of 0xd_0000_0000. We set the low |
||||
* bits of the mask to 11 to turn off splitting into 8 |
||||
* subregions and to enable the outbound translation. |
||||
*/ |
||||
out_le32(mbase + PECFG_POM0LAH, 0x00000000); |
||||
out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE + |
||||
port * CFG_PCIE_MEMSIZE)); |
||||
|
||||
switch (port) { |
||||
case 0: |
||||
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); |
||||
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + |
||||
port * CFG_PCIE_MEMSIZE); |
||||
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
||||
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), |
||||
~(CFG_PCIE_MEMSIZE - 1) | 3); |
||||
break; |
||||
case 1: |
||||
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); |
||||
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + |
||||
port * CFG_PCIE_MEMSIZE)); |
||||
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
||||
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), |
||||
~(CFG_PCIE_MEMSIZE - 1) | 3); |
||||
break; |
||||
case 2: |
||||
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); |
||||
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + |
||||
port * CFG_PCIE_MEMSIZE)); |
||||
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
||||
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), |
||||
~(CFG_PCIE_MEMSIZE - 1) | 3); |
||||
break; |
||||
} |
||||
|
||||
/* Set up 16GB inbound memory window at 0 */ |
||||
out_le32(mbase + PCI_BASE_ADDRESS_0, 0); |
||||
out_le32(mbase + PCI_BASE_ADDRESS_1, 0); |
||||
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); |
||||
out_le32(mbase + PECFG_BAR0LMPA, 0); |
||||
out_le32(mbase + PECFG_PIM0LAL, 0); |
||||
out_le32(mbase + PECFG_PIM0LAH, 0); |
||||
out_le32(mbase + PECFG_PIMEN, 0x1); |
||||
|
||||
/* Enable I/O, Mem, and Busmaster cycles */ |
||||
out_le16((u16 *)(mbase + PCI_COMMAND), |
||||
in_le16((u16 *)(mbase + PCI_COMMAND)) | |
||||
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
||||
} |
||||
#endif /* CONFIG_PCI */ |
||||
#endif /* CONFIG_440SPE */ |
||||
@ -0,0 +1,162 @@ |
||||
/*
|
||||
* Copyright (c) 2005 Cisco Systems. All rights reserved. |
||||
* Roland Dreier <rolandd@cisco.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
*/ |
||||
|
||||
#include <ppc4xx.h> |
||||
#ifndef __440SPE_PCIE_H |
||||
#define __440SPE_PCIE_H |
||||
|
||||
#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) |
||||
|
||||
#define DCRN_SDR0_CFGADDR 0x00e |
||||
#define DCRN_SDR0_CFGDATA 0x00f |
||||
|
||||
#define DCRN_PCIE0_BASE 0x100 |
||||
#define DCRN_PCIE1_BASE 0x120 |
||||
#define DCRN_PCIE2_BASE 0x140 |
||||
#define PCIE0 DCRN_PCIE0_BASE |
||||
#define PCIE1 DCRN_PCIE1_BASE |
||||
#define PCIE2 DCRN_PCIE2_BASE |
||||
|
||||
#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) |
||||
#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) |
||||
#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) |
||||
#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) |
||||
#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) |
||||
#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) |
||||
#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) |
||||
#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) |
||||
#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) |
||||
#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) |
||||
#define DCRN_PEGPL_REGBAH(base) (base + 0x12) |
||||
#define DCRN_PEGPL_REGBAL(base) (base + 0x13) |
||||
#define DCRN_PEGPL_REGMSK(base) (base + 0x14) |
||||
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) |
||||
|
||||
/*
|
||||
* System DCRs (SDRs) |
||||
*/ |
||||
#define PESDR0_PLLLCT1 0x03a0 |
||||
#define PESDR0_PLLLCT2 0x03a1 |
||||
#define PESDR0_PLLLCT3 0x03a2 |
||||
|
||||
#define PESDR0_UTLSET1 0x0300 |
||||
#define PESDR0_UTLSET2 0x0301 |
||||
#define PESDR0_DLPSET 0x0302 |
||||
#define PESDR0_LOOP 0x0303 |
||||
#define PESDR0_RCSSET 0x0304 |
||||
#define PESDR0_RCSSTS 0x0305 |
||||
#define PESDR0_HSSL0SET1 0x0306 |
||||
#define PESDR0_HSSL0SET2 0x0307 |
||||
#define PESDR0_HSSL0STS 0x0308 |
||||
#define PESDR0_HSSL1SET1 0x0309 |
||||
#define PESDR0_HSSL1SET2 0x030a |
||||
#define PESDR0_HSSL1STS 0x030b |
||||
#define PESDR0_HSSL2SET1 0x030c |
||||
#define PESDR0_HSSL2SET2 0x030d |
||||
#define PESDR0_HSSL2STS 0x030e |
||||
#define PESDR0_HSSL3SET1 0x030f |
||||
#define PESDR0_HSSL3SET2 0x0310 |
||||
#define PESDR0_HSSL3STS 0x0311 |
||||
#define PESDR0_HSSL4SET1 0x0312 |
||||
#define PESDR0_HSSL4SET2 0x0313 |
||||
#define PESDR0_HSSL4STS 0x0314 |
||||
#define PESDR0_HSSL5SET1 0x0315 |
||||
#define PESDR0_HSSL5SET2 0x0316 |
||||
#define PESDR0_HSSL5STS 0x0317 |
||||
#define PESDR0_HSSL6SET1 0x0318 |
||||
#define PESDR0_HSSL6SET2 0x0319 |
||||
#define PESDR0_HSSL6STS 0x031a |
||||
#define PESDR0_HSSL7SET1 0x031b |
||||
#define PESDR0_HSSL7SET2 0x031c |
||||
#define PESDR0_HSSL7STS 0x031d |
||||
#define PESDR0_HSSCTLSET 0x031e |
||||
#define PESDR0_LANE_ABCD 0x031f |
||||
#define PESDR0_LANE_EFGH 0x0320 |
||||
|
||||
#define PESDR1_UTLSET1 0x0340 |
||||
#define PESDR1_UTLSET2 0x0341 |
||||
#define PESDR1_DLPSET 0x0342 |
||||
#define PESDR1_LOOP 0x0343 |
||||
#define PESDR1_RCSSET 0x0344 |
||||
#define PESDR1_RCSSTS 0x0345 |
||||
#define PESDR1_HSSL0SET1 0x0346 |
||||
#define PESDR1_HSSL0SET2 0x0347 |
||||
#define PESDR1_HSSL0STS 0x0348 |
||||
#define PESDR1_HSSL1SET1 0x0349 |
||||
#define PESDR1_HSSL1SET2 0x034a |
||||
#define PESDR1_HSSL1STS 0x034b |
||||
#define PESDR1_HSSL2SET1 0x034c |
||||
#define PESDR1_HSSL2SET2 0x034d |
||||
#define PESDR1_HSSL2STS 0x034e |
||||
#define PESDR1_HSSL3SET1 0x034f |
||||
#define PESDR1_HSSL3SET2 0x0350 |
||||
#define PESDR1_HSSL3STS 0x0351 |
||||
#define PESDR1_HSSCTLSET 0x0352 |
||||
#define PESDR1_LANE_ABCD 0x0353 |
||||
|
||||
#define PESDR2_UTLSET1 0x0370 |
||||
#define PESDR2_UTLSET2 0x0371 |
||||
#define PESDR2_DLPSET 0x0372 |
||||
#define PESDR2_LOOP 0x0373 |
||||
#define PESDR2_RCSSET 0x0374 |
||||
#define PESDR2_RCSSTS 0x0375 |
||||
#define PESDR2_HSSL0SET1 0x0376 |
||||
#define PESDR2_HSSL0SET2 0x0377 |
||||
#define PESDR2_HSSL0STS 0x0378 |
||||
#define PESDR2_HSSL1SET1 0x0379 |
||||
#define PESDR2_HSSL1SET2 0x037a |
||||
#define PESDR2_HSSL1STS 0x037b |
||||
#define PESDR2_HSSL2SET1 0x037c |
||||
#define PESDR2_HSSL2SET2 0x037d |
||||
#define PESDR2_HSSL2STS 0x037e |
||||
#define PESDR2_HSSL3SET1 0x037f |
||||
#define PESDR2_HSSL3SET2 0x0380 |
||||
#define PESDR2_HSSL3STS 0x0381 |
||||
#define PESDR2_HSSCTLSET 0x0382 |
||||
#define PESDR2_LANE_ABCD 0x0383 |
||||
|
||||
/*
|
||||
* UTL register offsets |
||||
*/ |
||||
#define PEUTL_PBBSZ 0x20 |
||||
#define PEUTL_OPDBSZ 0x68 |
||||
#define PEUTL_IPHBSZ 0x70 |
||||
#define PEUTL_IPDBSZ 0x78 |
||||
#define PEUTL_OUTTR 0x90 |
||||
#define PEUTL_INTR 0x98 |
||||
#define PEUTL_PCTL 0xa0 |
||||
#define PEUTL_RCIRQEN 0xb8 |
||||
|
||||
/*
|
||||
* Config space register offsets |
||||
*/ |
||||
#define PECFG_BAR0LMPA 0x210 |
||||
#define PECFG_BAR0HMPA 0x214 |
||||
#define PECFG_PIMEN 0x33c |
||||
#define PECFG_PIM0LAL 0x340 |
||||
#define PECFG_PIM0LAH 0x344 |
||||
#define PECFG_POM0LAL 0x380 |
||||
#define PECFG_POM0LAH 0x384 |
||||
|
||||
#define SDR_READ(offset) ({\ |
||||
mtdcr(DCRN_SDR0_CFGADDR, offset); \
|
||||
mfdcr(DCRN_SDR0_CFGDATA);}) |
||||
|
||||
#define SDR_WRITE(offset, data) ({\ |
||||
mtdcr(DCRN_SDR0_CFGADDR, offset); \
|
||||
mtdcr(DCRN_SDR0_CFGDATA,data);}) |
||||
|
||||
int ppc440spe_init_pcie(void); |
||||
int ppc440spe_init_pcie_rootport(int port); |
||||
void yucca_setup_pcie_fpga_rootpoint(int port); |
||||
void ppc440spe_setup_pcie(struct pci_controller *hose, int port); |
||||
int yucca_pcie_card_present(int port); |
||||
int pcie_hose_scan(struct pci_controller *hose, int bus); |
||||
#endif /* __440SPE_PCIE_H */ |
||||
Loading…
Reference in new issue