Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces. This patch adds support for it. The corresponding DTSI file, from Linux next-20180720, is also introduced. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>lime2-spi
Icenowy Zheng
6 years ago
committed by
Jagan Teki
parent
da2616543a
commit
6f796a9bb4
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// SPDX-License-Identifier: (GPL-2.0+ or MIT) |
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/* |
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
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*/ |
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|
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/sun50i-h6-ccu.h> |
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h> |
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#include <dt-bindings/reset/sun50i-h6-ccu.h> |
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h> |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0>; |
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enable-method = "psci"; |
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}; |
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <1>; |
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enable-method = "psci"; |
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}; |
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cpu2: cpu@2 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <2>; |
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enable-method = "psci"; |
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}; |
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cpu3: cpu@3 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <3>; |
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enable-method = "psci"; |
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}; |
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}; |
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iosc: internal-osc-clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <16000000>; |
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clock-accuracy = <300000000>; |
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clock-output-names = "iosc"; |
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}; |
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osc24M: osc24M_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <24000000>; |
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clock-output-names = "osc24M"; |
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}; |
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osc32k: osc32k_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <32768>; |
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clock-output-names = "osc32k"; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
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<GIC_PPI 14 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
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<GIC_PPI 11 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
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<GIC_PPI 10 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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ccu: clock@3001000 { |
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compatible = "allwinner,sun50i-h6-ccu"; |
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reg = <0x03001000 0x1000>; |
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clocks = <&osc24M>, <&osc32k>, <&iosc>; |
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clock-names = "hosc", "losc", "iosc"; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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gic: interrupt-controller@3021000 { |
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compatible = "arm,gic-400"; |
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reg = <0x03021000 0x1000>, |
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<0x03022000 0x2000>, |
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<0x03024000 0x2000>, |
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<0x03026000 0x2000>; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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}; |
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pio: pinctrl@300b000 { |
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compatible = "allwinner,sun50i-h6-pinctrl"; |
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reg = <0x0300b000 0x400>; |
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; |
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clock-names = "apb", "hosc", "losc"; |
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gpio-controller; |
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#gpio-cells = <3>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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mmc0_pins: mmc0-pins { |
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pins = "PF0", "PF1", "PF2", "PF3", |
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"PF4", "PF5"; |
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function = "mmc0"; |
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drive-strength = <30>; |
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bias-pull-up; |
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}; |
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mmc2_pins: mmc2-pins { |
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pins = "PC1", "PC4", "PC5", "PC6", |
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"PC7", "PC8", "PC9", "PC10", |
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"PC11", "PC12", "PC13", "PC14"; |
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function = "mmc2"; |
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drive-strength = <30>; |
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bias-pull-up; |
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}; |
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uart0_ph_pins: uart0-ph { |
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pins = "PH0", "PH1"; |
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function = "uart0"; |
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}; |
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}; |
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mmc0: mmc@4020000 { |
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compatible = "allwinner,sun50i-h6-mmc", |
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"allwinner,sun50i-a64-mmc"; |
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reg = <0x04020000 0x1000>; |
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; |
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clock-names = "ahb", "mmc"; |
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resets = <&ccu RST_BUS_MMC0>; |
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reset-names = "ahb"; |
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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mmc1: mmc@4021000 { |
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compatible = "allwinner,sun50i-h6-mmc", |
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"allwinner,sun50i-a64-mmc"; |
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reg = <0x04021000 0x1000>; |
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; |
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clock-names = "ahb", "mmc"; |
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resets = <&ccu RST_BUS_MMC1>; |
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reset-names = "ahb"; |
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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mmc2: mmc@4022000 { |
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compatible = "allwinner,sun50i-h6-emmc", |
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"allwinner,sun50i-a64-emmc"; |
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reg = <0x04022000 0x1000>; |
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; |
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clock-names = "ahb", "mmc"; |
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resets = <&ccu RST_BUS_MMC2>; |
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reset-names = "ahb"; |
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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uart0: serial@5000000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x05000000 0x400>; |
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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clocks = <&ccu CLK_BUS_UART0>; |
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resets = <&ccu RST_BUS_UART0>; |
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status = "disabled"; |
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}; |
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uart1: serial@5000400 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x05000400 0x400>; |
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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clocks = <&ccu CLK_BUS_UART1>; |
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resets = <&ccu RST_BUS_UART1>; |
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status = "disabled"; |
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}; |
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uart2: serial@5000800 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x05000800 0x400>; |
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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clocks = <&ccu CLK_BUS_UART2>; |
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resets = <&ccu RST_BUS_UART2>; |
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status = "disabled"; |
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}; |
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uart3: serial@5000c00 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x05000c00 0x400>; |
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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clocks = <&ccu CLK_BUS_UART3>; |
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resets = <&ccu RST_BUS_UART3>; |
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status = "disabled"; |
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}; |
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r_ccu: clock@7010000 { |
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compatible = "allwinner,sun50i-h6-r-ccu"; |
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reg = <0x07010000 0x400>; |
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clocks = <&osc24M>, <&osc32k>, <&iosc>, |
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<&ccu CLK_PLL_PERIPH0>; |
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clock-names = "hosc", "losc", "iosc", "pll-periph"; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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r_intc: interrupt-controller@7021000 { |
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compatible = "allwinner,sun50i-h6-r-intc", |
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"allwinner,sun6i-a31-r-intc"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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reg = <0x07021000 0x400>; |
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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r_pio: pinctrl@7022000 { |
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compatible = "allwinner,sun50i-h6-r-pinctrl"; |
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reg = <0x07022000 0x400>; |
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; |
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clock-names = "apb", "hosc", "losc"; |
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gpio-controller; |
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#gpio-cells = <3>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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r_i2c_pins: r-i2c { |
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pins = "PL0", "PL1"; |
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function = "s_i2c"; |
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}; |
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}; |
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r_i2c: i2c@7081400 { |
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compatible = "allwinner,sun6i-a31-i2c"; |
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reg = <0x07081400 0x400>; |
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&r_ccu CLK_R_APB2_I2C>; |
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resets = <&r_ccu RST_R_APB2_I2C>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&r_i2c_pins>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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}; |
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@ -0,0 +1,125 @@ |
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
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*/ |
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#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ |
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#define _DT_BINDINGS_CLK_SUN50I_H6_H_ |
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#define CLK_PLL_PERIPH0 3 |
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#define CLK_CPUX 21 |
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#define CLK_APB1 26 |
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#define CLK_DE 29 |
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#define CLK_BUS_DE 30 |
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#define CLK_DEINTERLACE 31 |
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#define CLK_BUS_DEINTERLACE 32 |
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#define CLK_GPU 33 |
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#define CLK_BUS_GPU 34 |
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#define CLK_CE 35 |
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#define CLK_BUS_CE 36 |
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#define CLK_VE 37 |
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#define CLK_BUS_VE 38 |
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#define CLK_EMCE 39 |
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#define CLK_BUS_EMCE 40 |
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#define CLK_VP9 41 |
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#define CLK_BUS_VP9 42 |
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#define CLK_BUS_DMA 43 |
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#define CLK_BUS_MSGBOX 44 |
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#define CLK_BUS_SPINLOCK 45 |
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#define CLK_BUS_HSTIMER 46 |
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#define CLK_AVS 47 |
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#define CLK_BUS_DBG 48 |
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#define CLK_BUS_PSI 49 |
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#define CLK_BUS_PWM 50 |
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#define CLK_BUS_IOMMU 51 |
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#define CLK_MBUS_DMA 53 |
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#define CLK_MBUS_VE 54 |
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#define CLK_MBUS_CE 55 |
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#define CLK_MBUS_TS 56 |
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#define CLK_MBUS_NAND 57 |
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#define CLK_MBUS_CSI 58 |
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#define CLK_MBUS_DEINTERLACE 59 |
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#define CLK_NAND0 61 |
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#define CLK_NAND1 62 |
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#define CLK_BUS_NAND 63 |
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#define CLK_MMC0 64 |
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#define CLK_MMC1 65 |
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#define CLK_MMC2 66 |
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#define CLK_BUS_MMC0 67 |
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#define CLK_BUS_MMC1 68 |
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#define CLK_BUS_MMC2 69 |
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#define CLK_BUS_UART0 70 |
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#define CLK_BUS_UART1 71 |
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#define CLK_BUS_UART2 72 |
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#define CLK_BUS_UART3 73 |
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#define CLK_BUS_I2C0 74 |
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#define CLK_BUS_I2C1 75 |
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#define CLK_BUS_I2C2 76 |
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#define CLK_BUS_I2C3 77 |
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#define CLK_BUS_SCR0 78 |
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#define CLK_BUS_SCR1 79 |
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#define CLK_SPI0 80 |
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#define CLK_SPI1 81 |
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#define CLK_BUS_SPI0 82 |
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#define CLK_BUS_SPI1 83 |
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#define CLK_BUS_EMAC 84 |
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#define CLK_TS 85 |
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#define CLK_BUS_TS 86 |
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#define CLK_IR_TX 87 |
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#define CLK_BUS_IR_TX 88 |
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#define CLK_BUS_THS 89 |
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#define CLK_I2S3 90 |
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#define CLK_I2S0 91 |
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#define CLK_I2S1 92 |
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#define CLK_I2S2 93 |
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#define CLK_BUS_I2S0 94 |
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#define CLK_BUS_I2S1 95 |
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#define CLK_BUS_I2S2 96 |
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#define CLK_BUS_I2S3 97 |
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#define CLK_SPDIF 98 |
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#define CLK_BUS_SPDIF 99 |
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#define CLK_DMIC 100 |
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#define CLK_BUS_DMIC 101 |
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#define CLK_AUDIO_HUB 102 |
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#define CLK_BUS_AUDIO_HUB 103 |
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#define CLK_USB_OHCI0 104 |
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#define CLK_USB_PHY0 105 |
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#define CLK_USB_PHY1 106 |
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#define CLK_USB_OHCI3 107 |
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#define CLK_USB_PHY3 108 |
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#define CLK_USB_HSIC_12M 109 |
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#define CLK_USB_HSIC 110 |
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#define CLK_BUS_OHCI0 111 |
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#define CLK_BUS_OHCI3 112 |
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#define CLK_BUS_EHCI0 113 |
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#define CLK_BUS_XHCI 114 |
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#define CLK_BUS_EHCI3 115 |
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#define CLK_BUS_OTG 116 |
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#define CLK_PCIE_REF_100M 117 |
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#define CLK_PCIE_REF 118 |
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#define CLK_PCIE_REF_OUT 119 |
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#define CLK_PCIE_MAXI 120 |
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#define CLK_PCIE_AUX 121 |
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#define CLK_BUS_PCIE 122 |
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#define CLK_HDMI 123 |
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#define CLK_HDMI_SLOW 124 |
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#define CLK_HDMI_CEC 125 |
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#define CLK_BUS_HDMI 126 |
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#define CLK_BUS_TCON_TOP 127 |
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#define CLK_TCON_LCD0 128 |
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#define CLK_BUS_TCON_LCD0 129 |
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#define CLK_TCON_TV0 130 |
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#define CLK_BUS_TCON_TV0 131 |
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#define CLK_CSI_CCI 132 |
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#define CLK_CSI_TOP 133 |
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#define CLK_CSI_MCLK 134 |
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#define CLK_BUS_CSI 135 |
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#define CLK_HDCP 136 |
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#define CLK_BUS_HDCP 137 |
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#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ |
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@ -0,0 +1,24 @@ |
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/* SPDX-License-Identifier: GPL-2.0 */ |
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/*
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* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> |
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*/ |
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#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ |
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#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ |
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#define CLK_AR100 0 |
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#define CLK_R_APB1 2 |
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#define CLK_R_APB1_TIMER 4 |
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#define CLK_R_APB1_TWD 5 |
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#define CLK_R_APB1_PWM 6 |
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#define CLK_R_APB2_UART 7 |
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#define CLK_R_APB2_I2C 8 |
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#define CLK_R_APB1_IR 9 |
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#define CLK_R_APB1_W1 10 |
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#define CLK_IR 11 |
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#define CLK_W1 12 |
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#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ |
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@ -0,0 +1,73 @@ |
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
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*/ |
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#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ |
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#define _DT_BINDINGS_RESET_SUN50I_H6_H_ |
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#define RST_MBUS 0 |
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#define RST_BUS_DE 1 |
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#define RST_BUS_DEINTERLACE 2 |
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#define RST_BUS_GPU 3 |
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#define RST_BUS_CE 4 |
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#define RST_BUS_VE 5 |
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#define RST_BUS_EMCE 6 |
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#define RST_BUS_VP9 7 |
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#define RST_BUS_DMA 8 |
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#define RST_BUS_MSGBOX 9 |
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#define RST_BUS_SPINLOCK 10 |
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#define RST_BUS_HSTIMER 11 |
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#define RST_BUS_DBG 12 |
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#define RST_BUS_PSI 13 |
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#define RST_BUS_PWM 14 |
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#define RST_BUS_IOMMU 15 |
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#define RST_BUS_DRAM 16 |
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#define RST_BUS_NAND 17 |
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#define RST_BUS_MMC0 18 |
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#define RST_BUS_MMC1 19 |
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#define RST_BUS_MMC2 20 |
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#define RST_BUS_UART0 21 |
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#define RST_BUS_UART1 22 |
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#define RST_BUS_UART2 23 |
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#define RST_BUS_UART3 24 |
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#define RST_BUS_I2C0 25 |
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#define RST_BUS_I2C1 26 |
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#define RST_BUS_I2C2 27 |
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#define RST_BUS_I2C3 28 |
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#define RST_BUS_SCR0 29 |
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#define RST_BUS_SCR1 30 |
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#define RST_BUS_SPI0 31 |
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#define RST_BUS_SPI1 32 |
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#define RST_BUS_EMAC 33 |
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#define RST_BUS_TS 34 |
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#define RST_BUS_IR_TX 35 |
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#define RST_BUS_THS 36 |
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#define RST_BUS_I2S0 37 |
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#define RST_BUS_I2S1 38 |
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#define RST_BUS_I2S2 39 |
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#define RST_BUS_I2S3 40 |
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#define RST_BUS_SPDIF 41 |
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#define RST_BUS_DMIC 42 |
||||
#define RST_BUS_AUDIO_HUB 43 |
||||
#define RST_USB_PHY0 44 |
||||
#define RST_USB_PHY1 45 |
||||
#define RST_USB_PHY3 46 |
||||
#define RST_USB_HSIC 47 |
||||
#define RST_BUS_OHCI0 48 |
||||
#define RST_BUS_OHCI3 49 |
||||
#define RST_BUS_EHCI0 50 |
||||
#define RST_BUS_XHCI 51 |
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#define RST_BUS_EHCI3 52 |
||||
#define RST_BUS_OTG 53 |
||||
#define RST_BUS_PCIE 54 |
||||
#define RST_PCIE_POWERUP 55 |
||||
#define RST_BUS_HDMI 56 |
||||
#define RST_BUS_HDMI_SUB 57 |
||||
#define RST_BUS_TCON_TOP 58 |
||||
#define RST_BUS_TCON_LCD0 59 |
||||
#define RST_BUS_TCON_TV0 60 |
||||
#define RST_BUS_CSI 61 |
||||
#define RST_BUS_HDCP 62 |
||||
|
||||
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ |
||||
@ -0,0 +1,17 @@ |
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ |
||||
/*
|
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ |
||||
#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ |
||||
|
||||
#define RST_R_APB1_TIMER 0 |
||||
#define RST_R_APB1_TWD 1 |
||||
#define RST_R_APB1_PWM 2 |
||||
#define RST_R_APB2_UART 3 |
||||
#define RST_R_APB2_I2C 4 |
||||
#define RST_R_APB1_IR 5 |
||||
#define RST_R_APB1_W1 6 |
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ |
||||
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Reference in new issue