@ -39,60 +39,6 @@
# define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
# define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI0 | \
DAVINCI_SYSCFG_SUSPSRC_UART1 | \
DAVINCI_SYSCFG_SUSPSRC_I2C )
/*
* PLL configuration
*/
# define CONFIG_SYS_DA850_PLL0_PLLM 24
# define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
# define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
( 0x4 < < DV_DDR_PHY_RD_LATENCY_SHIFT ) )
# define CONFIG_SYS_DA850_DDR2_SDBCR ( \
( 1 < < DV_DDR_SDCR_MSDRAMEN_SHIFT ) | \
( 1 < < DV_DDR_SDCR_DDREN_SHIFT ) | \
( 1 < < DV_DDR_SDCR_SDRAMEN_SHIFT ) | \
( 1 < < DV_DDR_SDCR_BUS_WIDTH_SHIFT ) | \
( 0x3 < < DV_DDR_SDCR_CL_SHIFT ) | \
( 0x2 < < DV_DDR_SDCR_IBANK_SHIFT ) | \
( 0x2 < < DV_DDR_SDCR_PAGESIZE_SHIFT ) )
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
# define CONFIG_SYS_DA850_DDR2_SDBCR2 0
# define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
( 14 < < DV_DDR_SDTMR1_RFC_SHIFT ) | \
( 2 < < DV_DDR_SDTMR1_RP_SHIFT ) | \
( 2 < < DV_DDR_SDTMR1_RCD_SHIFT ) | \
( 1 < < DV_DDR_SDTMR1_WR_SHIFT ) | \
( 5 < < DV_DDR_SDTMR1_RAS_SHIFT ) | \
( 8 < < DV_DDR_SDTMR1_RC_SHIFT ) | \
( 1 < < DV_DDR_SDTMR1_RRD_SHIFT ) | \
( 0 < < DV_DDR_SDTMR1_WTR_SHIFT ) )
# define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
( 7 < < DV_DDR_SDTMR2_RASMAX_SHIFT ) | \
( 0 < < DV_DDR_SDTMR2_XP_SHIFT ) | \
( 0 < < DV_DDR_SDTMR2_ODT_SHIFT ) | \
( 17 < < DV_DDR_SDTMR2_XSNR_SHIFT ) | \
( 199 < < DV_DDR_SDTMR2_XSRD_SHIFT ) | \
( 0 < < DV_DDR_SDTMR2_RTP_SHIFT ) | \
( 0 < < DV_DDR_SDTMR2_CKE_SHIFT ) )
# define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
# define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Serial Driver info
*/