On i.MX27, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de>master
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version |
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* 2 of the License, or (at your option) any later version. |
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*/ |
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); |
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DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); |
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DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); |
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DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); |
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DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); |
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DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); |
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DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); |
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DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); |
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DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); |
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DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); |
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DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); |
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DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); |
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DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); |
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DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); |
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DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); |
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DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); |
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return 0; |
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} |
@ -1,16 +0,0 @@ |
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#define AIPI1_PSR0 0x10000000 |
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#define AIPI1_PSR1 0x10000004 |
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#define AIPI2_PSR0 0x10020000 |
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#define AIPI2_PSR1 0x10020004 |
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#define CSCR 0x10027000 |
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#define MPCTL0 0x10027004 |
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#define SPCTL0 0x1002700c |
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#define PCDR0 0x10027018 |
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#define PCDR1 0x1002701c |
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#define PCCR0 0x10027020 |
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#define PCCR1 0x10027024 |
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#define ESDCTL0_ROF 0x00 |
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#define ESDCFG0_ROF 0x04 |
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#define ESDCTL1_ROF 0x08 |
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#define ESDCFG1_ROF 0x0C |
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#define ESDMISC_ROF 0x10 |
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