This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>lime2-spi
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Xilinx, Inc. (Michal Simek) |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <timer.h> |
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#include <asm/io.h> |
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#define CNT_CNTRL_RESET BIT(4) |
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struct cadence_ttc_regs { |
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u32 clk_cntrl1; /* 0x0 - Clock Control 1 */ |
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u32 clk_cntrl2; /* 0x4 - Clock Control 2 */ |
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u32 clk_cntrl3; /* 0x8 - Clock Control 3 */ |
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u32 counter_cntrl1; /* 0xC - Counter Control 1 */ |
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u32 counter_cntrl2; /* 0x10 - Counter Control 2 */ |
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u32 counter_cntrl3; /* 0x14 - Counter Control 3 */ |
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u32 counter_val1; /* 0x18 - Counter Control 1 */ |
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u32 counter_val2; /* 0x1C - Counter Control 2 */ |
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u32 counter_val3; /* 0x20 - Counter Control 3 */ |
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u32 reserved[15]; |
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u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */ |
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u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */ |
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u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */ |
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}; |
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struct cadence_ttc_priv { |
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struct cadence_ttc_regs *regs; |
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}; |
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static int cadence_ttc_get_count(struct udevice *dev, u64 *count) |
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{ |
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struct cadence_ttc_priv *priv = dev_get_priv(dev); |
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*count = readl(&priv->regs->counter_val1); |
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return 0; |
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} |
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static int cadence_ttc_probe(struct udevice *dev) |
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{ |
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struct cadence_ttc_priv *priv = dev_get_priv(dev); |
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/* Disable interrupts for sure */ |
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writel(0, &priv->regs->interrupt_enable1); |
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writel(0, &priv->regs->interrupt_enable2); |
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writel(0, &priv->regs->interrupt_enable3); |
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/* Make sure that clocks are configured properly without prescaller */ |
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writel(0, &priv->regs->clk_cntrl1); |
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writel(0, &priv->regs->clk_cntrl2); |
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writel(0, &priv->regs->clk_cntrl3); |
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/* Reset and enable this counter */ |
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writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1); |
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return 0; |
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} |
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static int cadence_ttc_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct cadence_ttc_priv *priv = dev_get_priv(dev); |
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priv->regs = map_physmem(devfdt_get_addr(dev), |
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sizeof(struct cadence_ttc_regs), MAP_NOCACHE); |
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return 0; |
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} |
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static const struct timer_ops cadence_ttc_ops = { |
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.get_count = cadence_ttc_get_count, |
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}; |
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static const struct udevice_id cadence_ttc_ids[] = { |
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{ .compatible = "cdns,ttc" }, |
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{} |
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}; |
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U_BOOT_DRIVER(cadence_ttc) = { |
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.name = "cadence_ttc", |
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.id = UCLASS_TIMER, |
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.of_match = cadence_ttc_ids, |
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.ofdata_to_platdata = cadence_ttc_ofdata_to_platdata, |
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.priv_auto_alloc_size = sizeof(struct cadence_ttc_priv), |
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.probe = cadence_ttc_probe, |
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.ops = &cadence_ttc_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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