These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>master
parent
8d1e3cb140
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743d48151d
@ -1,12 +0,0 @@ |
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if TARGET_P1_P2_RDB |
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config SYS_BOARD |
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default "p1_p2_rdb" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_CONFIG_NAME |
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default "P1_P2_RDB" |
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endif |
@ -1,37 +0,0 @@ |
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P1_P2_RDB BOARD |
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#M: - |
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S: Maintained |
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F: board/freescale/p1_p2_rdb/ |
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F: include/configs/P1_P2_RDB.h |
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F: configs/P1011RDB_defconfig |
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F: configs/P1011RDB_36BIT_defconfig |
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F: configs/P1011RDB_36BIT_SDCARD_defconfig |
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F: configs/P1011RDB_36BIT_SPIFLASH_defconfig |
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F: configs/P1011RDB_NAND_defconfig |
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F: configs/P1011RDB_SDCARD_defconfig |
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F: configs/P1011RDB_SPIFLASH_defconfig |
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F: configs/P1020RDB_defconfig |
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F: configs/P1020RDB_36BIT_defconfig |
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F: configs/P1020RDB_36BIT_SDCARD_defconfig |
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F: configs/P1020RDB_36BIT_SPIFLASH_defconfig |
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F: configs/P1020RDB_NAND_defconfig |
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F: configs/P1020RDB_SDCARD_defconfig |
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F: configs/P1020RDB_SPIFLASH_defconfig |
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F: configs/P2010RDB_defconfig |
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F: configs/P2010RDB_36BIT_defconfig |
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F: configs/P2010RDB_36BIT_SDCARD_defconfig |
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F: configs/P2010RDB_36BIT_SPIFLASH_defconfig |
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F: configs/P2010RDB_NAND_defconfig |
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F: configs/P2010RDB_SDCARD_defconfig |
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F: configs/P2010RDB_SPIFLASH_defconfig |
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F: configs/P2020RDB_36BIT_defconfig |
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F: configs/P2020RDB_36BIT_SDCARD_defconfig |
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F: configs/P2020RDB_36BIT_SPIFLASH_defconfig |
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F: configs/P2020RDB_NAND_defconfig |
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F: configs/P2020RDB_SDCARD_defconfig |
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F: configs/P2020RDB_SPIFLASH_defconfig |
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P2020RDB BOARD |
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M: Poonam Aggrwal <poonam.aggrwal@freescale.com> |
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S: Maintained |
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F: configs/P2020RDB_defconfig |
@ -1,30 +0,0 @@ |
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#
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# Copyright 2009 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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MINIMAL=
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ifdef CONFIG_SPL_BUILD |
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ifdef CONFIG_SPL_INIT_MINIMAL |
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MINIMAL=y
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endif |
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endif |
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ifdef MINIMAL |
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obj-y += spl_minimal.o tlb.o law.o
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else |
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ifdef CONFIG_SPL_BUILD |
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obj-y += spl.o
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else |
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obj-y += p1_p2_rdb.o
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obj-$(CONFIG_PCI) += pci.o
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endif |
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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endif |
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Overview |
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-------- |
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P2020RDB is a Low End Dual core platform supporting the P2020 processor |
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of QorIQ series. P2020 is an e500 based dual core SOC. |
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|
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Building U-boot |
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----------- |
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To build the u-boot for P2020RDB: |
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make P2020RDB_config |
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make |
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|
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NOR Flash Banks |
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----------- |
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RDB board for P2020 has two flash banks. They are both present on boot. |
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Booting by default is always from the boot bank at 0xef00_0000. |
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Memory Map |
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---------- |
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0xef00_0000 - 0xef7f_ffff Alternate bank 8MB |
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0xe800_0000 - 0xefff_ffff Boot bank 8MB |
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0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB |
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0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB |
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Switch settings to boot from the NOR flash banks |
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------------------------------------------------ |
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SW4[8]=0 default NOR Flash bank |
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SW4[8]=1 Alternate NOR Flash bank |
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Flashing Images |
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--------------- |
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To place a new u-boot image in the alternate flash bank and then boot |
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with that new image temporarily, use this: |
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tftp 1000000 u-boot.bin |
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erase ef740000 ef7fffff |
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cp.b 1000000 ef740000 c0000 |
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Now to boot from the alternate bank change the SW4[8] from 0 to 1. |
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To program the image in the boot flash bank: |
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tftp 1000000 u-boot.bin |
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protect off all |
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erase eff40000 ffffffff |
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cp.b 1000000 eff40000 c0000 |
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Using the Device Tree Source File |
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--------------------------------- |
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To create the DTB (Device Tree Binary) image file, |
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use a command similar to this: |
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dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb |
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Likely, that .dts file will come from here; |
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linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts |
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Booting Linux |
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------------- |
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Place a linux uImage in the TFTP disk area. |
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tftp 1000000 uImage.p2020rdb |
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tftp 2000000 rootfs.ext2.gz.uboot |
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tftp c00000 p2020rdb.dtb |
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bootm 1000000 2000000 c00000 |
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Implementing AMP(Asymmetric MultiProcessing) |
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--------------------------------------------- |
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1. Build kernel image for core0: |
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a. $ make 85xx/p1_p2_rdb_defconfig |
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b. $ make menuconfig |
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- un-select "Processor support"-> |
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"Symetric multi-processing support" |
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c. $ make uImage |
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d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 |
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2. Build kernel image for core1: |
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a. $ make 85xx/p1_p2_rdb_defconfig |
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b. $ make menuconfig |
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- Un-select "Processor support"-> |
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"Symetric multi-processing support" |
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- Select "Advanced setup" -> |
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"Prompt for advanced kernel configuration options" |
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- Select |
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"Set physical address where the kernel is loaded" |
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and set it to 0x20000000, assuming core1 will |
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start from 512MB. |
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- Select "Set custom page offset address" |
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- Select "Set custom kernel base address" |
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- Select "Set maximum low memory" |
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- "Exit" and save the selection. |
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c. $ make uImage |
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d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 |
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3. Create dtb for core0: |
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$ dtc -I dts -O dtb -f -b 0 |
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arch/powerpc/boot/dts/p2020rdb_camp_core0.dts > |
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/tftpboot/p2020rdb_camp_core0.dtb |
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4. Create dtb for core1: |
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$ dtc -I dts -O dtb -f -b 1 |
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arch/powerpc/boot/dts/p2020rdb_camp_core1.dts > |
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/tftpboot/p2020rdb_camp_core1.dtb |
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5. Bring up two cores separately: |
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a. Power on the board, under u-boot prompt: |
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=> setenv <serverip> |
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=> setenv <ipaddr> |
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=> setenv bootargs root=/dev/ram rw console=ttyS0,115200 |
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b. Bring up core1's kernel first: |
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=> setenv bootm_low 0x20000000 |
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=> setenv bootm_size 0x10000000 |
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=> tftp 21000000 uImage.core1 |
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=> tftp 22000000 ramdiskfile |
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=> tftp 20c00000 p2020rdb_camp_core1.dtb |
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=> interrupts off |
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=> bootm start 21000000 22000000 20c00000 |
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=> bootm loados |
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=> bootm ramdisk |
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=> bootm fdt |
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=> fdt boardsetup |
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=> fdt chosen $initrd_start $initrd_end |
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=> bootm prep |
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=> cpu 1 release $bootm_low - $fdtaddr - |
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c. Bring up core0's kernel(on the same u-boot console): |
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=> setenv bootm_low 0 |
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=> setenv bootm_size 0x20000000 |
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=> tftp 1000000 uImage.core0 |
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=> tftp 2000000 ramdiskfile |
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=> tftp c00000 p2020rdb_camp_core0.dtb |
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=> bootm 1000000 2000000 c00000 |
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Please note only core0 will run u-boot, core1 starts kernel directly |
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after "cpu release" command is issued. |
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/*
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* Copyright 2009, 2011 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/mmu.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/processor.h> |
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#include <fsl_ddr_sdram.h> |
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#include <asm/io.h> |
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#include <asm/fsl_law.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 |
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 |
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 |
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 |
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 |
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 |
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 |
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#define CONFIG_SYS_DDR_RCW_1 0x00000000 |
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#define CONFIG_SYS_DDR_RCW_2 0x00000000 |
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#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/ |
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#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 |
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#define CONFIG_SYS_DDR_TIMING_4 0x00000000 |
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#define CONFIG_SYS_DDR_TIMING_5 0x00000000 |
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#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000 |
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#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802 |
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#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322 |
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#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca |
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#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000 |
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#define CONFIG_SYS_DDR_MODE_1_400 0x00480432 |
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#define CONFIG_SYS_DDR_MODE_2_400 0x00000000 |
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#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100 |
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#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000 |
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#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802 |
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#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432 |
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#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce |
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#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000 |
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#define CONFIG_SYS_DDR_MODE_1_533 0x00040642 |
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#define CONFIG_SYS_DDR_MODE_2_533 0x00000000 |
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#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100 |
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#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000 |
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#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 |
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#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 |
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#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 |
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#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 |
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#define CONFIG_SYS_DDR_MODE_1_667 0x00040852 |
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#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 |
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#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 |
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#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 |
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#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 |
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 |
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 |
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 |
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#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 |
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 |
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 |
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fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { |
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400, |
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400, |
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400, |
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400, |
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400, |
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400, |
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400, |
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.ddr_data_init = CONFIG_MEM_INIT_VALUE, |
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400, |
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
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}; |
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fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { |
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533, |
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533, |
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533, |
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533, |
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533, |
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533, |
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533, |
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.ddr_data_init = CONFIG_MEM_INIT_VALUE, |
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533, |
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
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}; |
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fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { |
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, |
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, |
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, |
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, |
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, |
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, |
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, |
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.ddr_data_init = CONFIG_MEM_INIT_VALUE, |
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, |
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
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}; |
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { |
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, |
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, |
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, |
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, |
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, |
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, |
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, |
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.ddr_data_init = CONFIG_MEM_INIT_VALUE, |
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, |
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
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}; |
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/*
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* Fixed sdram init -- doesn't use serial presence detect. |
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*/ |
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phys_size_t fixed_sdram (void) |
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{ |
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fsl_ddr_cfg_regs_t ddr_cfg_regs; |
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size_t ddr_size; |
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struct cpu_type *cpu; |
||||
ulong ddr_freq, ddr_freq_mhz; |
||||
|
||||
cpu = gd->arch.cpu; |
||||
|
||||
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) |
||||
return ddr_size; |
||||
#endif |
||||
ddr_freq = get_ddr_freq(0); |
||||
ddr_freq_mhz = ddr_freq / 1000000; |
||||
|
||||
printf("Configuring DDR for %ld T/s data rate\n", ddr_freq); |
||||
|
||||
if(ddr_freq_mhz <= 400) |
||||
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); |
||||
else if(ddr_freq_mhz <= 533) |
||||
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); |
||||
else if(ddr_freq_mhz <= 667) |
||||
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); |
||||
else if(ddr_freq_mhz <= 800) |
||||
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); |
||||
else |
||||
panic("Unsupported DDR data rate %ld T/s\n", ddr_freq); |
||||
|
||||
/* P1020 and it's derivatives support max 32bit DDR width */ |
||||
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { |
||||
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; |
||||
ddr_cfg_regs.cs[0].bnds = 0x0000001F; |
||||
} |
||||
|
||||
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); |
||||
|
||||
set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); |
||||
return ddr_size; |
||||
} |
@ -1,17 +0,0 @@ |
||||
/*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), |
||||
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
@ -1,303 +0,0 @@ |
||||
/*
|
||||
* Copyright 2009-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/io.h> |
||||
#include <miiphy.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <fsl_mdio.h> |
||||
#include <tsec.h> |
||||
#include <vsc7385.h> |
||||
#include <netdev.h> |
||||
#include <rtc.h> |
||||
#include <i2c.h> |
||||
#include <hwconfig.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define VSC7385_RST_SET 0x00080000 |
||||
#define SLIC_RST_SET 0x00040000 |
||||
#define SGMII_PHY_RST_SET 0x00020000 |
||||
#define PCIE_RST_SET 0x00010000 |
||||
#define RGMII_PHY_RST_SET 0x02000000 |
||||
|
||||
#define USB_RST_CLR 0x04000000 |
||||
#define USB2_PORT_OUT_EN 0x01000000 |
||||
|
||||
#define GPIO_DIR 0x060f0000 |
||||
|
||||
#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \ |
||||
SGMII_PHY_RST_SET | PCIE_RST_SET | \
|
||||
RGMII_PHY_RST_SET |
||||
|
||||
#define SYSCLK_MASK 0x00200000 |
||||
#define BOARDREV_MASK 0x10100000 |
||||
#define BOARDREV_C 0x00100000 |
||||
#define BOARDREV_D 0x00000000 |
||||
|
||||
#define SYSCLK_66 66666666 |
||||
#define SYSCLK_100 100000000 |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
||||
u32 val_gpdat, sysclk_gpio; |
||||
|
||||
val_gpdat = in_be32(&pgpio->gpdat); |
||||
sysclk_gpio = val_gpdat & SYSCLK_MASK; |
||||
|
||||
if(sysclk_gpio == 0) |
||||
return SYSCLK_66; |
||||
else |
||||
return SYSCLK_100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_MMC |
||||
int board_early_init_f (void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
|
||||
setbits_be32(&gur->pmuxcr, |
||||
(MPC85xx_PMUXCR_SDHC_CD | |
||||
MPC85xx_PMUXCR_SDHC_WP)); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
u32 val_gpdat, board_rev_gpio; |
||||
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
||||
char board_rev = 0; |
||||
struct cpu_type *cpu; |
||||
|
||||
val_gpdat = in_be32(&pgpio->gpdat); |
||||
board_rev_gpio = val_gpdat & BOARDREV_MASK; |
||||
if (board_rev_gpio == BOARDREV_C) |
||||
board_rev = 'C'; |
||||
else if (board_rev_gpio == BOARDREV_D) |
||||
board_rev = 'D'; |
||||
else |
||||
panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); |
||||
|
||||
cpu = gd->arch.cpu; |
||||
printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); |
||||
|
||||
setbits_be32(&pgpio->gpdir, GPIO_DIR); |
||||
|
||||
/*
|
||||
* Bringing the following peripherals out of reset via GPIOs |
||||
* 0 = reset and 1 = out of reset |
||||
* GPIO12 - Reset to Ethernet Switch |
||||
* GPIO13 - Reset to SLIC/SLAC devices |
||||
* GPIO14 - Reset to SGMII_PHY_N |
||||
* GPIO15 - Reset to PCIe slots |
||||
* GPIO6 - Reset to RGMII PHY |
||||
* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset |
||||
*/ |
||||
clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR; |
||||
|
||||
setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN); |
||||
setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN); |
||||
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
unsigned int orig_bus = i2c_get_bus_num(); |
||||
u8 i2c_data; |
||||
|
||||
i2c_set_bus_num(1); |
||||
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, |
||||
1, &i2c_data, sizeof(i2c_data)) == 0) { |
||||
if (i2c_data & 0x2) |
||||
puts("NOR Flash Bank : Secondary\n"); |
||||
else |
||||
puts("NOR Flash Bank : Primary\n"); |
||||
|
||||
if (i2c_data & 0x1) { |
||||
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); |
||||
puts("SD/MMC : 8-bit Mode\n"); |
||||
puts("eSPI : Disabled\n"); |
||||
} else { |
||||
puts("SD/MMC : 4-bit Mode\n"); |
||||
puts("eSPI : Enabled\n"); |
||||
} |
||||
} else { |
||||
puts("Failed reading I2C Chip 0x18 on bus 1\n"); |
||||
} |
||||
i2c_set_bus_num(orig_bus); |
||||
|
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
if (flash_esel == -1) { |
||||
/* very unlikely unless something is messed up */ |
||||
puts("Error: Could not find TLB for FLASH BASE\n"); |
||||
flash_esel = 2; /* give our best effort to continue */ |
||||
} else { |
||||
/* invalidate existing TLB entry for flash */ |
||||
disable_tlb(flash_esel); |
||||
} |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_16M, 1); |
||||
rtc_reset(); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
#ifdef CONFIG_TSEC_ENET |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
struct fsl_pq_mdio_info mdio_info; |
||||
struct tsec_info_struct tsec_info[4]; |
||||
int num = 0; |
||||
char *tmp; |
||||
unsigned int vscfw_addr; |
||||
|
||||
#ifdef CONFIG_TSEC1 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 1); |
||||
num++; |
||||
#endif |
||||
#ifdef CONFIG_TSEC2 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 2); |
||||
num++; |
||||
#endif |
||||
#ifdef CONFIG_TSEC3 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 3); |
||||
if (is_serdes_configured(SGMII_TSEC3)) { |
||||
puts("eTSEC3 is in sgmii mode.\n"); |
||||
tsec_info[num].flags |= TSEC_SGMII; |
||||
} |
||||
num++; |
||||
#endif |
||||
if (!num) { |
||||
printf("No TSECs initialized\n"); |
||||
return 0; |
||||
} |
||||
#ifdef CONFIG_VSC7385_ENET |
||||
/* If a VSC7385 microcode image is present, then upload it. */ |
||||
if ((tmp = getenv ("vscfw_addr")) != NULL) { |
||||
vscfw_addr = simple_strtoul (tmp, NULL, 16); |
||||
printf("uploading VSC7385 microcode from %x\n", vscfw_addr); |
||||
if (vsc7385_upload_firmware((void *) vscfw_addr, |
||||
CONFIG_VSC7385_IMAGE_SIZE)) |
||||
puts("Failure uploading VSC7385 microcode.\n"); |
||||
} else |
||||
puts("No address specified for VSC7385 microcode.\n"); |
||||
#endif |
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; |
||||
mdio_info.name = DEFAULT_MII_NAME; |
||||
fsl_pq_mdio_init(bis, &mdio_info); |
||||
|
||||
tsec_eth_init(bis, tsec_info, num); |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
extern void ft_pci_board_setup(void *blob); |
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
const char *soc_usb_compat = "fsl-usb2-dr"; |
||||
int err, usb1_off, usb2_off; |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
ft_pci_board_setup(blob); |
||||
#endif /* #if defined(CONFIG_PCI) */ |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB) |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
||||
/* Delete eLBC node as it is muxed with USB2 controller */ |
||||
if (hwconfig("usb2")) { |
||||
const char *soc_elbc_compat = "fsl,p1020-elbc"; |
||||
int off = fdt_node_offset_by_compatible(blob, -1, |
||||
soc_elbc_compat); |
||||
if (off < 0) { |
||||
printf("WARNING: could not find compatible node %s\n", |
||||
soc_elbc_compat); |
||||
return off; |
||||
} |
||||
err = fdt_del_node(blob, off); |
||||
if (err < 0) { |
||||
printf("WARNING: could not remove %s\n", |
||||
soc_elbc_compat); |
||||
return err; |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
/* Delete USB2 node as it is muxed with eLBC */ |
||||
usb1_off = fdt_node_offset_by_compatible(blob, -1, |
||||
soc_usb_compat); |
||||
if (usb1_off < 0) { |
||||
printf("WARNING: could not find compatible node %s\n", |
||||
soc_usb_compat); |
||||
return usb1_off; |
||||
} |
||||
usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, |
||||
soc_usb_compat); |
||||
if (usb2_off < 0) { |
||||
printf("WARNING: could not find compatible node %s\n", |
||||
soc_usb_compat); |
||||
return usb2_off; |
||||
} |
||||
err = fdt_del_node(blob, usb2_off); |
||||
if (err < 0) { |
||||
printf("WARNING: could not remove %s\n", soc_usb_compat); |
||||
return err; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#endif |
@ -1,27 +0,0 @@ |
||||
/*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <pci.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/io.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
|
||||
void ft_pci_board_setup(void *blob) |
||||
{ |
||||
FT_FSL_PCI_SETUP; |
||||
} |
@ -1,141 +0,0 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ns16550.h> |
||||
#include <malloc.h> |
||||
#include <mmc.h> |
||||
#include <nand.h> |
||||
#include <i2c.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <spi_flash.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define SYSCLK_MASK 0x00200000 |
||||
#define BOARDREV_MASK 0x10100000 |
||||
|
||||
#define SYSCLK_66 66666666 |
||||
#define SYSCLK_100 100000000 |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
||||
u32 val_gpdat, sysclk_gpio; |
||||
|
||||
val_gpdat = in_be32(&pgpio->gpdat); |
||||
sysclk_gpio = val_gpdat & SYSCLK_MASK; |
||||
|
||||
if (sysclk_gpio == 0) |
||||
return SYSCLK_66; |
||||
else |
||||
return SYSCLK_100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
return CONFIG_SYS_L2_SIZE; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio, bus_clk; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
console_init_f(); |
||||
|
||||
/* Set pmuxcr to allow both i2c1 and i2c2 */ |
||||
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); |
||||
setbits_be32(&gur->pmuxcr, |
||||
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); |
||||
|
||||
/* Read back the register to synchronize the write. */ |
||||
in_be32(&gur->pmuxcr); |
||||
|
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); |
||||
#endif |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
||||
plat_ratio >>= 1; |
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
||||
gd->bus_clk = bus_clk; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
bus_clk / 16 / CONFIG_BAUDRATE); |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
puts("\nSD boot...\n"); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
puts("\nSPI Flash boot...\n"); |
||||
#endif |
||||
|
||||
/* copy code to RAM and jump to it - this should not return */ |
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read. |
||||
*/ |
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
/* Pointer is writable since we allocated a register for it */ |
||||
gd = (gd_t *)CONFIG_SPL_GD_ADDR; |
||||
bd_t *bd; |
||||
|
||||
memset(gd, 0, sizeof(gd_t)); |
||||
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); |
||||
memset(bd, 0, sizeof(bd_t)); |
||||
gd->bd = bd; |
||||
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; |
||||
bd->bi_memsize = CONFIG_SYS_L2_SIZE; |
||||
|
||||
probecpu(); |
||||
get_clocks(); |
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
||||
CONFIG_SPL_RELOC_MALLOC_SIZE); |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_initialize(bd); |
||||
#endif |
||||
/* relocate environment function pointers etc. */ |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
||||
gd->env_valid = 1; |
||||
|
||||
gd->ram_size = initdram(0); |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
puts("Tertiary program loader running in sram..."); |
||||
#else |
||||
puts("Second program loader running in sram...\n"); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_boot(); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
spi_boot(); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
nand_boot(); |
||||
#endif |
||||
} |
@ -1,84 +0,0 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ns16550.h> |
||||
#include <asm/io.h> |
||||
#include <nand.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <asm/global_data.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
#define SYSCLK_MASK 0x00200000 |
||||
#define BOARDREV_MASK 0x10100000 |
||||
|
||||
#define SYSCLK_66 66666666 |
||||
#define SYSCLK_100 100000000 |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
||||
u32 val_gpdat, sysclk_gpio; |
||||
|
||||
val_gpdat = in_be32(&pgpio->gpdat); |
||||
sysclk_gpio = val_gpdat & SYSCLK_MASK; |
||||
|
||||
if (sysclk_gpio == 0) |
||||
return SYSCLK_66; |
||||
else |
||||
return SYSCLK_100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) |
||||
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); |
||||
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); |
||||
#endif |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
||||
plat_ratio >>= 1; |
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE); |
||||
|
||||
puts("\nNAND boot... "); |
||||
|
||||
/* copy code to RAM and jump to it - this should not return */ |
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read. |
||||
*/ |
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
puts("\nSecond program loader running in sram..."); |
||||
nand_boot(); |
||||
} |
||||
|
||||
void putc(char c) |
||||
{ |
||||
if (c == '\n') |
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); |
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); |
||||
} |
||||
|
||||
void puts(const char *str) |
||||
{ |
||||
while (*str) |
||||
putc(*str++); |
||||
} |
@ -1,91 +0,0 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
/* W**G* - Flash/promjet, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256K, 1), |
||||
|
||||
#endif /* #if defined(CONFIG_PCI) */ |
||||
#endif |
||||
/* *I*G - NAND */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
/* *I*G - VSC7385 Switch */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR |
||||
/* *I*G - L2SRAM */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, |
||||
0, 11, BOOKE_PAGESZ_256K, 1), |
||||
#if CONFIG_SYS_L2_SIZE >= (256 << 10) |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, |
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 12, BOOKE_PAGESZ_256K, 1), |
||||
#endif |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || \ |
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 7, BOOKE_PAGESZ_1G, 1) |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,6 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_TPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,NAND" |
||||
+ST:CONFIG_PPC=y |
||||
+ST:CONFIG_MPC85xx=y |
||||
+ST:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1011RDB" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,6 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_TPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,NAND" |
||||
+ST:CONFIG_PPC=y |
||||
+ST:CONFIG_MPC85xx=y |
||||
+ST:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,6 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_TPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,NAND" |
||||
+ST:CONFIG_PPC=y |
||||
+ST:CONFIG_MPC85xx=y |
||||
+ST:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2010RDB" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,6 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_TPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" |
||||
+ST:CONFIG_PPC=y |
||||
+ST:CONFIG_MPC85xx=y |
||||
+ST:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,5 +0,0 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_P1_P2_RDB=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_P1_P2_RDB=y |
@ -1,808 +0,0 @@ |
||||
/*
|
||||
* Copyright 2009-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* P1 P2 RDB board configuration file |
||||
* This file is intended to address a set of Low End and Ultra Low End |
||||
* Freescale SOCs of QorIQ series(RDB platforms). |
||||
* Currently only P2020RDB |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#ifdef CONFIG_36BIT |
||||
#define CONFIG_PHYS_64BIT |
||||
#endif |
||||
|
||||
#ifdef CONFIG_P1011RDB |
||||
#define CONFIG_P1011 |
||||
#define CONFIG_SYS_L2_SIZE (256 << 10) |
||||
#endif |
||||
#ifdef CONFIG_P1020RDB |
||||
#define CONFIG_P1020 |
||||
#define CONFIG_SYS_L2_SIZE (256 << 10) |
||||
#endif |
||||
#ifdef CONFIG_P2010RDB |
||||
#define CONFIG_P2010 |
||||
#define CONFIG_SYS_L2_SIZE (512 << 10) |
||||
#endif |
||||
#ifdef CONFIG_P2020RDB |
||||
#define CONFIG_P2020 |
||||
#define CONFIG_SYS_L2_SIZE (512 << 10) |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SDCARD |
||||
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
||||
#define CONFIG_SPL_ENV_SUPPORT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_MMC_SUPPORT |
||||
#define CONFIG_SPL_MMC_MINIMAL |
||||
#define CONFIG_SPL_FLUSH_IMAGE |
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_I2C_SUPPORT |
||||
#define CONFIG_SYS_TEXT_BASE 0x11001000 |
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
||||
#define CONFIG_SPL_PAD_TO 0x20000 |
||||
#define CONFIG_SPL_MAX_SIZE (128 * 1024) |
||||
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
||||
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
||||
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) |
||||
#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10) |
||||
#define CONFIG_SYS_MPC85XX_NO_RESETVEC |
||||
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
||||
#define CONFIG_SPL_MMC_BOOT |
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SPL_COMMON_INIT_DDR |
||||
#endif |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPIFLASH |
||||
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
||||
#define CONFIG_SPL_ENV_SUPPORT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_SPI_SUPPORT |
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT |
||||
#define CONFIG_SPL_SPI_FLASH_MINIMAL |
||||
#define CONFIG_SPL_FLUSH_IMAGE |
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_I2C_SUPPORT |
||||
#define CONFIG_SYS_TEXT_BASE 0x11001000 |
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
||||
#define CONFIG_SPL_PAD_TO 0x20000 |
||||
#define CONFIG_SPL_MAX_SIZE (128 * 1024) |
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) |
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) |
||||
#define CONFIG_SYS_MPC85XX_NO_RESETVEC |
||||
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
||||
#define CONFIG_SPL_SPI_BOOT |
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SPL_COMMON_INIT_DDR |
||||
#endif |
||||
#endif |
||||
|
||||
#ifdef CONFIG_NAND |
||||
#ifdef CONFIG_TPL_BUILD |
||||
#define CONFIG_SPL_NAND_BOOT |
||||
#define CONFIG_SPL_FLUSH_IMAGE |
||||
#define CONFIG_SPL_ENV_SUPPORT |
||||
#define CONFIG_SPL_NAND_INIT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_I2C_SUPPORT |
||||
#define CONFIG_SPL_NAND_SUPPORT |
||||
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
||||
#define CONFIG_SPL_COMMON_INIT_DDR |
||||
#define CONFIG_SPL_MAX_SIZE (128 << 10) |
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
||||
#define CONFIG_SYS_MPC85XX_NO_RESETVEC |
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
||||
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) |
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) |
||||
#elif defined(CONFIG_SPL_BUILD) |
||||
#define CONFIG_SPL_INIT_MINIMAL |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_NAND_SUPPORT |
||||
#define CONFIG_SPL_FLUSH_IMAGE |
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
||||
#define CONFIG_SPL_TEXT_BASE 0xff800000 |
||||
#define CONFIG_SPL_MAX_SIZE 4096 |
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) |
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 |
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 |
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) |
||||
#endif /* not CONFIG_TPL_BUILD */ |
||||
|
||||
#define CONFIG_SPL_PAD_TO 0x20000 |
||||
#define CONFIG_TPL_PAD_TO 0x20000 |
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
||||
#define CONFIG_SYS_TEXT_BASE 0x11001000 |
||||
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0xeff40000 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE |
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
||||
#endif |
||||
#endif |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ |
||||
|
||||
#define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
||||
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
||||
#endif /* #if defined(CONFIG_PCI) */ |
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ |
||||
#endif |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long get_board_sys_clk(unsigned long dummy); |
||||
#endif |
||||
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ |
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ |
||||
|
||||
#if defined(CONFIG_P2020) || defined(CONFIG_P1020) |
||||
#define CONFIG_MP |
||||
#endif |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||
|
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_ADDR_MAP 1 |
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x1fffffff |
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||
|
||||
/*
|
||||
* Config the L2 Cache as L2 SRAM |
||||
*/ |
||||
#if defined(CONFIG_SPL_BUILD) |
||||
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
||||
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 |
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) |
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) |
||||
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) |
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) |
||||
#if defined(CONFIG_P2020RDB) |
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) |
||||
#else |
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) |
||||
#endif |
||||
#elif defined(CONFIG_NAND) |
||||
#ifdef CONFIG_TPL_BUILD |
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
||||
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 |
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) |
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) |
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) |
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) |
||||
#else |
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
||||
#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) |
||||
#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
||||
#endif /* CONFIG_TPL_BUILD */ |
||||
#endif |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
||||
#endif |
||||
|
||||
/* DDR Setup */ |
||||
#define CONFIG_SYS_FSL_DDR2 |
||||
#undef CONFIG_FSL_DDR_INTERACTIVE |
||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
|
||||
#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB) |
||||
/*
|
||||
* P1020 and it's derivatives support max 32bit DDR width |
||||
* So Reduce available DDR size |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_SIZE 512 |
||||
#else |
||||
#define CONFIG_SYS_SDRAM_SIZE 1024 |
||||
#endif |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1 |
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1 |
||||
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
||||
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
||||
#define CONFIG_SYS_DDR_SBE 0x00FF0000 |
||||
|
||||
/*
|
||||
* Memory map |
||||
* |
||||
* 0x0000_0000 0x3fff_ffff DDR 1G cacheablen |
||||
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
||||
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable |
||||
* |
||||
* Localbus cacheable (TBD) |
||||
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
||||
* |
||||
* Localbus non-cacheable |
||||
* 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable |
||||
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
||||
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable |
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
||||
*/ |
||||
|
||||
/*
|
||||
* Local Bus Definitions |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ |
||||
|
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull |
||||
#else |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
||||
BR_PS_16 | BR_V) |
||||
#define CONFIG_FLASH_OR_PRELIM 0xff000ff7 |
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_HWCONFIG |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR |
||||
/* The assembler doesn't like typecast */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
||||
#else |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS |
||||
#endif |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
||||
- GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
||||
#else |
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_NAND_FSL_ELBC 1 |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) |
||||
|
||||
/* NAND flash config */ |
||||
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */ |
||||
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ |
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR) |
||||
|
||||
#ifdef CONFIG_NAND |
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
||||
#else |
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_VSC7385_BASE 0xffb00000 |
||||
|
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull |
||||
#else |
||||
#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ |
||||
| BR_PS_8 | BR_V) |
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ |
||||
OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
|
||||
OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2 |
||||
* shorted - index 1 |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
||||
#define CONFIG_NS16550_MIN_FUNCTIONS |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/*
|
||||
* Pass open firmware flat tree |
||||
*/ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT 1 |
||||
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
||||
|
||||
/*
|
||||
* I2C2 EEPROM |
||||
*/ |
||||
#define CONFIG_ID_EEPROM |
||||
#ifdef CONFIG_ID_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#endif |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1 |
||||
|
||||
#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 |
||||
|
||||
#define CONFIG_RTC_DS1337 |
||||
#define CONFIG_SYS_RTC_DS1337_NOOSC |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
|
||||
/* eSPI - Enhanced SPI */ |
||||
#define CONFIG_FSL_ESPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
||||
#define CONFIG_SYS_PCIE2_NAME "Slot 1" |
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 1, Slot 1, tgtid 1, Base address a000 */ |
||||
#define CONFIG_SYS_PCIE1_NAME "Slot 2" |
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||
#ifdef CONFIG_PHYS_64BIT |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull |
||||
#else |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 |
||||
#endif |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
#undef CONFIG_RTL8139 |
||||
|
||||
#ifdef CONFIG_RTL8139 |
||||
/* This macro is used by RTL8139 but not defined in PPC architecture */ |
||||
#define KSEG1ADDR(x) (x) |
||||
#define _IO_BASE 0x00000000 |
||||
#endif |
||||
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC1" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC2" |
||||
#define CONFIG_TSEC3 1 |
||||
#define CONFIG_TSEC3_NAME "eTSEC3" |
||||
|
||||
#define TSEC1_PHY_ADDR 2 |
||||
#define TSEC2_PHY_ADDR 0 |
||||
#define TSEC3_PHY_ADDR 1 |
||||
|
||||
#define CONFIG_VSC7385_ENET |
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
|
||||
/* Vitesse 7385 */ |
||||
|
||||
#ifdef CONFIG_VSC7385_ENET |
||||
/* The size of the VSC7385 firmware image */ |
||||
#define CONFIG_VSC7385_IMAGE_SIZE 8192 |
||||
#endif |
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1" |
||||
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifdef CONFIG_SPIFLASH |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
||||
#define CONFIG_ENV_SPI_MODE 0 |
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
||||
#elif defined(CONFIG_SDCARD) |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_FSL_FIXED_MMC_LOCATION |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_ENV_OFFSET (512 * 0x800) |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
||||
#elif defined(CONFIG_NAND) |
||||
#ifdef CONFIG_TPL_BUILD |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
||||
#else |
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
||||
#endif |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_OFFSET (1024 * 1024) |
||||
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
||||
#elif defined(CONFIG_SYS_RAMBOOT) |
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||
#endif |
||||
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SETEXPR |
||||
#define CONFIG_CMD_REGINFO |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_MMC 1 |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
||||
#ifdef CONFIG_P2020 |
||||
#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_HAS_FSL_DR_USB |
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB) |
||||
#define CONFIG_USB_EHCI |
||||
|
||||
#ifdef CONFIG_USB_EHCI |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_USB_EHCI_FSL |
||||
#define CONFIG_USB_STORAGE |
||||
#endif |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 64 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_HAS_ETH2 |
||||
#endif |
||||
|
||||
#define CONFIG_HOSTNAME P2020RDB |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
||||
|
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 1000000 |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=p2020rdb.dtb\0" \
|
||||
"bdev=sda1\0" \
|
||||
"jffs2nor=mtdblock3\0" \
|
||||
"norbootaddr=ef080000\0" \
|
||||
"norfdtaddr=ef040000\0" \
|
||||
"jffs2nand=mtdblock9\0" \
|
||||
"nandbootaddr=100000\0" \
|
||||
"nandfdtaddr=80000\0" \
|
||||
"nandimgsize=400000\0" \
|
||||
"nandfdtsize=80000\0" \
|
||||
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
|
||||
"vscfw_addr=ef000000\0" \
|
||||
"othbootargs=ramdisk_size=600000\0" \
|
||||
"usbfatboot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"fatload usb 0:2 $loadaddr $bootfile;" \
|
||||
"fatload usb 0:2 $fdtaddr $fdtfile;" \
|
||||
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
"usbext2boot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
"norboot=setenv bootargs root=/dev/$jffs2nor rw " \
|
||||
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
|
||||
"bootm $norbootaddr - $norfdtaddr\0" \
|
||||
"nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"nand read 2000000 $nandbootaddr $nandimgsize;" \
|
||||
"nand read 3000000 $nandfdtaddr $nandfdtsize;" \
|
||||
"bootm 2000000 - 3000000;\0" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_HDBOOT \ |
||||
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
|
||||
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue