This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>master
Haiying Wang
16 years ago
committed by
Kumar Gala
parent
22b6dbc169
commit
765547dc5e
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#
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# Copyright 2004-2009 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += bcsr.o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,49 @@ |
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/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include "bcsr.h" |
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void enable_8569mds_flash_write() |
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{ |
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP); |
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} |
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void disable_8569mds_flash_write() |
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{ |
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); |
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} |
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void enable_8569mds_qe_mdio() |
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{ |
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), |
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BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); |
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), |
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BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); |
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} |
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void disable_8569mds_brd_eeprom_write_protect() |
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{ |
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); |
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} |
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@ -0,0 +1,82 @@ |
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/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __BCSR_H_ |
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#define __BCSR_H_ |
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#include <common.h> |
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/* BCSR Bit definitions*/ |
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/****************************************/ |
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/* BCSR defines */ |
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/****************************************/ |
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#define BCSR6_UPC1_EN 0x80 |
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#define BCSR6_UPC1_POS_EN 0x40 |
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#define BCSR6_UPC1_ADDR_EN 0x20 |
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#define BCSR6_UPC1_DEV2 0x10 |
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#define BCSR6_SD_ENABLE 0x04 |
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#define BCSR6_TDM2G_EN 0x02 |
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#define BCSR6_UCC7_RMII_EN 0x01 |
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#define BCSR7_UCC1_GETH_EN 0x80 |
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#define BCSR7_UCC1_RGMII_EN 0x40 |
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#define BCSR7_UCC1_RTBI_EN 0x20 |
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#define BCSR7_GETHRST_MRVL 0x04 |
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#define BCSR7_BRD_WRT_PROTECT 0x02 |
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#define BCSR8_UCC2_GETH_EN 0x80 |
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#define BCSR8_UCC2_RGMII_EN 0x40 |
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#define BCSR8_UCC2_RTBI_EN 0x20 |
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#define BCSR8_UEM_MARVEL_RESET 0x02 |
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#define BCSR9_UCC3_GETH_EN 0x80 |
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#define BCSR9_UCC3_RGMII_EN 0x40 |
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#define BCSR9_UCC3_RTBI_EN 0x20 |
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#define BCSR9_UCC3_RMII_EN 0x10 |
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#define BCSR9_UCC3_UEM_MICREL 0x01 |
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#define BCSR10_UCC4_GETH_EN 0x80 |
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#define BCSR10_UCC4_RGMII_EN 0x40 |
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#define BCSR10_UCC4_RTBI_EN 0x20 |
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#define BCSR11_LED0 0x40 |
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#define BCSR11_LED1 0x20 |
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#define BCSR11_LED2 0x10 |
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#define BCSR12_UCC6_RMII_EN 0x20 |
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#define BCSR12_UCC8_RMII_EN 0x20 |
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#define BCSR15_SMII6_DIS 0x08 |
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#define BCSR15_SMII8_DIS 0x04 |
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#define BCSR16_UPC1_DEV2 0x02 |
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#define BCSR17_FLASH_nWP 0x01 |
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/*BCSR Utils functions*/ |
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void enable_8569mds_flash_write(void); |
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void disable_8569mds_flash_write(void); |
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void enable_8569mds_qe_mdio(void); |
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void disable_8569mds_brd_eeprom_write_protect(void); |
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#endif /* __BCSR_H_ */ |
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@ -0,0 +1,30 @@ |
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#
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# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# mpc8569mds board
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#
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TEXT_BASE = 0xfff80000
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PLATFORM_CPPFLAGS += -DCONFIG_E500=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8569=1
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@ -0,0 +1,84 @@ |
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/*
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* Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/fsl_ddr_dimm_params.h> |
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static void |
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get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) |
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{ |
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i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); |
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} |
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unsigned int fsl_ddr_get_mem_data_rate(void) |
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{ |
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return get_ddr_freq(0); |
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} |
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, |
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unsigned int ctrl_num) |
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{ |
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unsigned int i; |
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unsigned int i2c_address = 0; |
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
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if (ctrl_num == 0 && i == 0) |
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i2c_address = SPD_EEPROM_ADDRESS1; |
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if (ctrl_num == 0 && i == 1) |
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i2c_address = SPD_EEPROM_ADDRESS2; |
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get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
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} |
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} |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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/*
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* Factors to consider for clock adjust: |
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* - number of chips on bus |
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* - position of slot |
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* - DDR1 vs. DDR2? |
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* - ??? |
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* |
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* This needs to be determined on a board-by-board basis. |
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* 0110 3/4 cycle late |
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* 0111 7/8 cycle late |
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*/ |
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popts->clk_adjust = 6; |
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/*
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* Factors to consider for CPO: |
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* - frequency |
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* - ddr1 vs. ddr2 |
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*/ |
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popts->cpo_override = 0xff; |
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/*
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* Factors to consider for write data delay: |
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* - number of DIMMs |
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* |
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* 1 = 1/4 clock delay |
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* 2 = 1/2 clock delay |
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* 3 = 3/4 clock delay |
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* 4 = 1 clock delay |
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* 5 = 5/4 clock delay |
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* 6 = 3/2 clock delay |
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*/ |
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popts->write_data_delay = 2; |
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 0; |
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} |
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@ -0,0 +1,59 @@ |
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/*
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* Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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/*
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* LAW(Local Access Window) configuration: |
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* |
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*0) 0x0000_0000 0x7fff_ffff DDR 2G |
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*1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB |
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*-) 0xe000_0000 0xe00f_ffff CCSR 1M |
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*2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M |
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*3) 0xc000_0000 0xdfff_ffff SRIO 512MB |
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*4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB |
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*4.b) 0xf800_0000 0xf800_7fff BCSR 32KB |
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*4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB |
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*4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB |
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*4.e) 0xfe00_0000 0xffff_ffff Flash 32MB |
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* |
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*Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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* |
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*/ |
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struct law_entry law_table[] = { |
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#ifndef CONFIG_SPD_EEPROM |
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), |
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#endif |
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), |
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), |
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SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), |
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}; |
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int num_law_entries = ARRAY_SIZE(law_table); |
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@ -0,0 +1,329 @@ |
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/*
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* Copyright 2009 Freescale Semiconductor. |
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* |
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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|
* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
|
||||||
|
#include <common.h> |
||||||
|
#include <pci.h> |
||||||
|
#include <asm/processor.h> |
||||||
|
#include <asm/mmu.h> |
||||||
|
#include <asm/immap_85xx.h> |
||||||
|
#include <asm/immap_fsl_pci.h> |
||||||
|
#include <asm/fsl_ddr_sdram.h> |
||||||
|
#include <asm/io.h> |
||||||
|
#include <spd_sdram.h> |
||||||
|
#include <i2c.h> |
||||||
|
#include <ioports.h> |
||||||
|
#include <libfdt.h> |
||||||
|
#include <fdt_support.h> |
||||||
|
|
||||||
|
#include "bcsr.h" |
||||||
|
|
||||||
|
phys_size_t fixed_sdram(void); |
||||||
|
|
||||||
|
const qe_iop_conf_t qe_iop_conf_tab[] = { |
||||||
|
/* QE_MUX_MDC */ |
||||||
|
{2, 31, 1, 0, 1}, /* QE_MUX_MDC */ |
||||||
|
|
||||||
|
/* QE_MUX_MDIO */ |
||||||
|
{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ |
||||||
|
|
||||||
|
/* UCC_1_RGMII */ |
||||||
|
{2, 11, 2, 0, 1}, /* CLK12 */ |
||||||
|
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ |
||||||
|
{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ |
||||||
|
{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ |
||||||
|
{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ |
||||||
|
{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ |
||||||
|
{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ |
||||||
|
{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ |
||||||
|
{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ |
||||||
|
{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ |
||||||
|
{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ |
||||||
|
{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ |
||||||
|
{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ |
||||||
|
|
||||||
|
/* UCC_2_RGMII */ |
||||||
|
{2, 16, 2, 0, 3}, /* CLK17 */ |
||||||
|
{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ |
||||||
|
{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ |
||||||
|
{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ |
||||||
|
{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ |
||||||
|
{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ |
||||||
|
{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ |
||||||
|
{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ |
||||||
|
{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ |
||||||
|
{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ |
||||||
|
{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ |
||||||
|
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ |
||||||
|
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ |
||||||
|
|
||||||
|
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ |
||||||
|
}; |
||||||
|
|
||||||
|
void local_bus_init(void); |
||||||
|
|
||||||
|
int board_early_init_f (void) |
||||||
|
{ |
||||||
|
/*
|
||||||
|
* Initialize local bus. |
||||||
|
*/ |
||||||
|
local_bus_init (); |
||||||
|
|
||||||
|
enable_8569mds_flash_write(); |
||||||
|
|
||||||
|
#ifdef CONFIG_QE |
||||||
|
enable_8569mds_qe_mdio(); |
||||||
|
#endif |
||||||
|
|
||||||
|
#if CONFIG_SYS_I2C2_OFFSET |
||||||
|
/* Enable I2C2 signals instead of SD signals */ |
||||||
|
volatile struct ccsr_gur *gur; |
||||||
|
gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); |
||||||
|
gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; |
||||||
|
gur->plppar1 |= PLPPAR1_I2C2_VAL; |
||||||
|
gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; |
||||||
|
gur->plpdir1 |= PLPDIR1_I2C2_VAL; |
||||||
|
|
||||||
|
disable_8569mds_brd_eeprom_write_protect(); |
||||||
|
#endif |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
int checkboard (void) |
||||||
|
{ |
||||||
|
printf ("Board: 8569 MDS\n"); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
phys_size_t |
||||||
|
initdram(int board_type) |
||||||
|
{ |
||||||
|
long dram_size = 0; |
||||||
|
|
||||||
|
puts("Initializing\n"); |
||||||
|
|
||||||
|
#if defined(CONFIG_DDR_DLL) |
||||||
|
/*
|
||||||
|
* Work around to stabilize DDR DLL MSYNC_IN. |
||||||
|
* Errata DDR9 seems to have been fixed. |
||||||
|
* This is now the workaround for Errata DDR11: |
||||||
|
* Override DLL = 1, Course Adj = 1, Tap Select = 0 |
||||||
|
*/ |
||||||
|
volatile ccsr_gur_t *gur = |
||||||
|
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||||
|
|
||||||
|
out_be32(&gur->ddrdllcr, 0x81000000); |
||||||
|
udelay(200); |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef CONFIG_SPD_EEPROM |
||||||
|
dram_size = fsl_ddr_sdram(); |
||||||
|
#else |
||||||
|
dram_size = fixed_sdram(); |
||||||
|
#endif |
||||||
|
|
||||||
|
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
||||||
|
dram_size *= 0x100000; |
||||||
|
|
||||||
|
puts(" DDR: "); |
||||||
|
return dram_size; |
||||||
|
} |
||||||
|
|
||||||
|
#if !defined(CONFIG_SPD_EEPROM) |
||||||
|
phys_size_t fixed_sdram(void) |
||||||
|
{ |
||||||
|
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; |
||||||
|
uint d_init; |
||||||
|
|
||||||
|
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); |
||||||
|
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); |
||||||
|
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); |
||||||
|
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); |
||||||
|
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); |
||||||
|
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); |
||||||
|
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); |
||||||
|
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); |
||||||
|
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); |
||||||
|
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); |
||||||
|
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); |
||||||
|
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); |
||||||
|
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); |
||||||
|
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); |
||||||
|
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); |
||||||
|
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); |
||||||
|
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); |
||||||
|
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); |
||||||
|
#if defined (CONFIG_DDR_ECC) |
||||||
|
out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); |
||||||
|
out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); |
||||||
|
out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); |
||||||
|
#endif |
||||||
|
udelay(500); |
||||||
|
|
||||||
|
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); |
||||||
|
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||||
|
d_init = 1; |
||||||
|
debug("DDR - 1st controller: memory initializing\n"); |
||||||
|
/*
|
||||||
|
* Poll until memory is initialized. |
||||||
|
* 512 Meg at 400 might hit this 200 times or so. |
||||||
|
*/ |
||||||
|
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { |
||||||
|
udelay(1000); |
||||||
|
} |
||||||
|
debug("DDR: memory initialized\n\n"); |
||||||
|
udelay(500); |
||||||
|
#endif |
||||||
|
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
||||||
|
} |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize Local Bus |
||||||
|
*/ |
||||||
|
void |
||||||
|
local_bus_init(void) |
||||||
|
{ |
||||||
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||||
|
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
||||||
|
|
||||||
|
uint clkdiv; |
||||||
|
uint lbc_hz; |
||||||
|
sys_info_t sysinfo; |
||||||
|
|
||||||
|
get_sys_info(&sysinfo); |
||||||
|
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; |
||||||
|
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
||||||
|
|
||||||
|
out_be32(&gur->lbiuiplldcr1, 0x00078080); |
||||||
|
if (clkdiv == 16) |
||||||
|
out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); |
||||||
|
else if (clkdiv == 8) |
||||||
|
out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); |
||||||
|
else if (clkdiv == 4) |
||||||
|
out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); |
||||||
|
|
||||||
|
out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); |
||||||
|
} |
||||||
|
|
||||||
|
#ifdef CONFIG_PCIE1 |
||||||
|
static struct pci_controller pcie1_hose; |
||||||
|
#endif /* CONFIG_PCIE1 */ |
||||||
|
|
||||||
|
extern int fsl_pci_setup_inbound_windows(struct pci_region *r); |
||||||
|
extern void fsl_pci_init(struct pci_controller *hose); |
||||||
|
|
||||||
|
int first_free_busno = 0; |
||||||
|
|
||||||
|
#ifdef CONFIG_PCI |
||||||
|
void |
||||||
|
pci_init_board(void) |
||||||
|
{ |
||||||
|
volatile ccsr_gur_t *gur; |
||||||
|
uint io_sel; |
||||||
|
uint host_agent; |
||||||
|
|
||||||
|
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||||
|
io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
||||||
|
host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
||||||
|
|
||||||
|
#ifdef CONFIG_PCIE1 |
||||||
|
{ |
||||||
|
volatile ccsr_fsl_pci_t *pci; |
||||||
|
struct pci_controller *hose; |
||||||
|
int pcie_ep; |
||||||
|
struct pci_region *r; |
||||||
|
int pcie_configured; |
||||||
|
|
||||||
|
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; |
||||||
|
hose = &pcie1_hose; |
||||||
|
pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); |
||||||
|
r = hose->regions; |
||||||
|
pcie_configured = io_sel >= 1; |
||||||
|
|
||||||
|
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ |
||||||
|
printf ("\n PCIE connected to slot as %s (base address %x)", |
||||||
|
pcie_ep ? "End Point" : "Root Complex", |
||||||
|
(uint)pci); |
||||||
|
|
||||||
|
if (pci->pme_msg_det) { |
||||||
|
pci->pme_msg_det = 0xffffffff; |
||||||
|
debug (" with errors. Clearing. Now 0x%08x", |
||||||
|
pci->pme_msg_det); |
||||||
|
} |
||||||
|
printf ("\n"); |
||||||
|
|
||||||
|
/* inbound */ |
||||||
|
r += fsl_pci_setup_inbound_windows(r); |
||||||
|
|
||||||
|
/* outbound memory */ |
||||||
|
pci_set_region(r++, |
||||||
|
CONFIG_SYS_PCIE1_MEM_BUS, |
||||||
|
CONFIG_SYS_PCIE1_MEM_PHYS, |
||||||
|
CONFIG_SYS_PCIE1_MEM_SIZE, |
||||||
|
PCI_REGION_MEM); |
||||||
|
|
||||||
|
/* outbound io */ |
||||||
|
pci_set_region(r++, |
||||||
|
CONFIG_SYS_PCIE1_IO_BUS, |
||||||
|
CONFIG_SYS_PCIE1_IO_PHYS, |
||||||
|
CONFIG_SYS_PCIE1_IO_SIZE, |
||||||
|
PCI_REGION_IO); |
||||||
|
|
||||||
|
hose->region_count = r - hose->regions; |
||||||
|
|
||||||
|
hose->first_busno=first_free_busno; |
||||||
|
pci_setup_indirect(hose, (int) &pci->cfg_addr, |
||||||
|
(int) &pci->cfg_data); |
||||||
|
|
||||||
|
fsl_pci_init(hose); |
||||||
|
printf ("PCIE on bus %02x - %02x\n", |
||||||
|
hose->first_busno,hose->last_busno); |
||||||
|
|
||||||
|
first_free_busno=hose->last_busno+1; |
||||||
|
|
||||||
|
} else { |
||||||
|
printf (" PCIE: disabled\n"); |
||||||
|
} |
||||||
|
} |
||||||
|
#else |
||||||
|
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
||||||
|
#endif |
||||||
|
} |
||||||
|
#endif /* CONFIG_PCI */ |
||||||
|
|
||||||
|
#if defined(CONFIG_OF_BOARD_SETUP) |
||||||
|
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, |
||||||
|
struct pci_controller *hose); |
||||||
|
|
||||||
|
void ft_board_setup(void *blob, bd_t *bd) |
||||||
|
{ |
||||||
|
ft_cpu_setup(blob, bd); |
||||||
|
|
||||||
|
#ifdef CONFIG_PCIE1 |
||||||
|
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); |
||||||
|
#endif |
||||||
|
} |
||||||
|
#endif |
||||||
@ -0,0 +1,103 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2009 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* (C) Copyright 2000 |
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <asm/mmu.h> |
||||||
|
|
||||||
|
struct fsl_e_tlb_entry tlb_table[] = { |
||||||
|
/* TLB 0 - for temp stack in cache */ |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
|
||||||
|
/* TLB 1 Initializations */ |
||||||
|
/*
|
||||||
|
* TLBe 0: 16M Non-cacheable, guarded |
||||||
|
* 0xff000000 16M FLASH (upper half) |
||||||
|
* Out of reset this entry is only 4K. |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, |
||||||
|
CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 0, BOOKE_PAGESZ_16M, 1), |
||||||
|
|
||||||
|
/*
|
||||||
|
* TLBe 1: 16M Non-cacheable, guarded |
||||||
|
* 0xfe000000 16M FLASH (lower half) |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 1, BOOKE_PAGESZ_16M, 1), |
||||||
|
|
||||||
|
/*
|
||||||
|
* TLBe 2: 256M Non-cacheable, guarded |
||||||
|
* 0xa00000000 256M PCIe MEM (lower half) |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 2, BOOKE_PAGESZ_256M, 1), |
||||||
|
|
||||||
|
/*
|
||||||
|
* TLBe 3: 256M Non-cacheable, guarded |
||||||
|
* 0xb00000000 256M PCIe MEM (higher half) |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000), |
||||||
|
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 3, BOOKE_PAGESZ_256M, 1), |
||||||
|
|
||||||
|
/*
|
||||||
|
* TLBe 4: 64M Non-cacheable, guarded |
||||||
|
* 0xe000_0000 1M CCSRBAR |
||||||
|
* 0xe280_0000 8M PCIe IO |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 4, BOOKE_PAGESZ_64M, 1), |
||||||
|
|
||||||
|
/*
|
||||||
|
* TLBe 5: 256K Non-cacheable, guarded |
||||||
|
* 0xf8000000 32K BCSR |
||||||
|
* 0xf8008000 32K PIB (CS4) |
||||||
|
* 0xf8010000 32K PIB (CS5) |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 5, BOOKE_PAGESZ_256K, 1), |
||||||
|
}; |
||||||
|
|
||||||
|
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||||
@ -0,0 +1,143 @@ |
|||||||
|
/* |
||||||
|
* Copyright 2004-2009 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
OUTPUT_ARCH(powerpc) |
||||||
|
/* Do we need any of these for elf? |
||||||
|
__DYNAMIC = 0; */ |
||||||
|
PHDRS |
||||||
|
{ |
||||||
|
text PT_LOAD; |
||||||
|
bss PT_LOAD; |
||||||
|
} |
||||||
|
|
||||||
|
SECTIONS |
||||||
|
{ |
||||||
|
/* Read-only sections, merged into text segment: */ |
||||||
|
. = + SIZEOF_HEADERS; |
||||||
|
.interp : { *(.interp) } |
||||||
|
.hash : { *(.hash) } |
||||||
|
.dynsym : { *(.dynsym) } |
||||||
|
.dynstr : { *(.dynstr) } |
||||||
|
.rel.text : { *(.rel.text) } |
||||||
|
.rela.text : { *(.rela.text) } |
||||||
|
.rel.data : { *(.rel.data) } |
||||||
|
.rela.data : { *(.rela.data) } |
||||||
|
.rel.rodata : { *(.rel.rodata) } |
||||||
|
.rela.rodata : { *(.rela.rodata) } |
||||||
|
.rel.got : { *(.rel.got) } |
||||||
|
.rela.got : { *(.rela.got) } |
||||||
|
.rel.ctors : { *(.rel.ctors) } |
||||||
|
.rela.ctors : { *(.rela.ctors) } |
||||||
|
.rel.dtors : { *(.rel.dtors) } |
||||||
|
.rela.dtors : { *(.rela.dtors) } |
||||||
|
.rel.bss : { *(.rel.bss) } |
||||||
|
.rela.bss : { *(.rela.bss) } |
||||||
|
.rel.plt : { *(.rel.plt) } |
||||||
|
.rela.plt : { *(.rela.plt) } |
||||||
|
.init : { *(.init) } |
||||||
|
.plt : { *(.plt) } |
||||||
|
.text : |
||||||
|
{ |
||||||
|
*(.text) |
||||||
|
*(.fixup) |
||||||
|
*(.got1) |
||||||
|
} :text |
||||||
|
_etext = .; |
||||||
|
PROVIDE (etext = .); |
||||||
|
.rodata : |
||||||
|
{ |
||||||
|
*(.eh_frame) |
||||||
|
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||||
|
} :text |
||||||
|
.fini : { *(.fini) } =0 |
||||||
|
.ctors : { *(.ctors) } |
||||||
|
.dtors : { *(.dtors) } |
||||||
|
|
||||||
|
/* Read-write section, merged into data segment: */ |
||||||
|
. = (. + 0x00FF) & 0xFFFFFF00; |
||||||
|
_erotext = .; |
||||||
|
PROVIDE (erotext = .); |
||||||
|
.reloc : |
||||||
|
{ |
||||||
|
*(.got) |
||||||
|
_GOT2_TABLE_ = .; |
||||||
|
*(.got2) |
||||||
|
_FIXUP_TABLE_ = .; |
||||||
|
*(.fixup) |
||||||
|
} |
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||||
|
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||||
|
|
||||||
|
.data : |
||||||
|
{ |
||||||
|
*(.data) |
||||||
|
*(.data1) |
||||||
|
*(.sdata) |
||||||
|
*(.sdata2) |
||||||
|
*(.dynamic) |
||||||
|
CONSTRUCTORS |
||||||
|
} |
||||||
|
_edata = .; |
||||||
|
PROVIDE (edata = .); |
||||||
|
|
||||||
|
. = .; |
||||||
|
__u_boot_cmd_start = .; |
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) } |
||||||
|
__u_boot_cmd_end = .; |
||||||
|
|
||||||
|
. = .; |
||||||
|
__start___ex_table = .; |
||||||
|
__ex_table : { *(__ex_table) } |
||||||
|
__stop___ex_table = .; |
||||||
|
|
||||||
|
. = ALIGN(256); |
||||||
|
__init_begin = .; |
||||||
|
.text.init : { *(.text.init) } |
||||||
|
.data.init : { *(.data.init) } |
||||||
|
. = ALIGN(256); |
||||||
|
__init_end = .; |
||||||
|
|
||||||
|
.bootpg ADDR(.text) + 0x7f000 : |
||||||
|
{ |
||||||
|
cpu/mpc85xx/start.o (.bootpg) |
||||||
|
} :text = 0xffff |
||||||
|
|
||||||
|
.resetvec ADDR(.text) + 0x7fffc : |
||||||
|
{ |
||||||
|
*(.resetvec) |
||||||
|
} :text = 0xffff |
||||||
|
|
||||||
|
. = ADDR(.text) + 0x80000; |
||||||
|
|
||||||
|
__bss_start = .; |
||||||
|
.bss (NOLOAD) : |
||||||
|
{ |
||||||
|
*(.sbss) *(.scommon) |
||||||
|
*(.dynbss) |
||||||
|
*(.bss) |
||||||
|
*(COMMON) |
||||||
|
} :bss |
||||||
|
|
||||||
|
. = ALIGN(4); |
||||||
|
_end = . ; |
||||||
|
PROVIDE (end = .); |
||||||
|
} |
||||||
@ -0,0 +1,454 @@ |
|||||||
|
/*
|
||||||
|
* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
/*
|
||||||
|
* mpc8569mds board configuration file |
||||||
|
*/ |
||||||
|
#ifndef __CONFIG_H |
||||||
|
#define __CONFIG_H |
||||||
|
|
||||||
|
/* High Level Configuration Options */ |
||||||
|
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||||
|
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||||
|
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ |
||||||
|
#define CONFIG_MPC8569 1 /* MPC8569 specific */ |
||||||
|
#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ |
||||||
|
|
||||||
|
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ |
||||||
|
|
||||||
|
#define CONFIG_PCI 1 /* Disable PCI/PCIE */ |
||||||
|
#define CONFIG_PCIE1 1 /* PCIE controller */ |
||||||
|
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ |
||||||
|
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
||||||
|
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
||||||
|
#define CONFIG_QE /* Enable QE */ |
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* When initializing flash, if we cannot find the manufacturer ID, |
||||||
|
* assume this is the AMD flash associated with the MDS board. |
||||||
|
* This allows booting from a promjet. |
||||||
|
*/ |
||||||
|
#define CONFIG_ASSUME_AMD_FLASH |
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__ |
||||||
|
extern unsigned long get_clock_freq(void); |
||||||
|
#endif |
||||||
|
/* Replace a call to get_clock_freq (after it is implemented)*/ |
||||||
|
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||||
|
#define CONFIG_DDR_CLK_FREQ 66000000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* These can be toggled for performance analysis, otherwise use default. |
||||||
|
*/ |
||||||
|
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||||
|
#define CONFIG_BTB /* toggle branch predition */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Only possible on E500 Version 2 or newer cores. |
||||||
|
*/ |
||||||
|
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
||||||
|
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* Base addresses -- Note these are effective addresses where the |
||||||
|
* actual resources get mapped (not physical addresses) |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||||
|
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
||||||
|
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR |
||||||
|
/* physical addr of CCSRBAR */ |
||||||
|
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR |
||||||
|
/* PQII uses CONFIG_SYS_IMMR */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
||||||
|
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) |
||||||
|
|
||||||
|
/* DDR Setup */ |
||||||
|
#define CONFIG_FSL_DDR3 |
||||||
|
#undef CONFIG_FSL_DDR_INTERACTIVE |
||||||
|
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
||||||
|
#define CONFIG_DDR_SPD |
||||||
|
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||||
|
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
||||||
|
|
||||||
|
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||||
|
/* DDR is system memory*/ |
||||||
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||||
|
|
||||||
|
#define CONFIG_NUM_DDR_CONTROLLERS 1 |
||||||
|
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||||
|
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
||||||
|
|
||||||
|
/* I2C addresses of SPD EEPROMs */ |
||||||
|
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
||||||
|
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ |
||||||
|
|
||||||
|
/* These are used when DDR doesn't use SPD. */ |
||||||
|
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ |
||||||
|
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
||||||
|
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
||||||
|
#define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
||||||
|
#define CONFIG_SYS_DDR_TIMING_0 0x00330004 |
||||||
|
#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 |
||||||
|
#define CONFIG_SYS_DDR_TIMING_2 0x002888D0 |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 |
||||||
|
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 |
||||||
|
#define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
||||||
|
#define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
||||||
|
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 |
||||||
|
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 |
||||||
|
#define CONFIG_SYS_DDR_CDR_1 0x80040000 |
||||||
|
#define CONFIG_SYS_DDR_CDR_2 0x00000000 |
||||||
|
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
||||||
|
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
||||||
|
#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ |
||||||
|
#define CONFIG_SYS_DDR_CONTROL2 0x24400000 |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
||||||
|
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
||||||
|
#define CONFIG_SYS_DDR_SBE 0x00010000 |
||||||
|
|
||||||
|
#undef CONFIG_CLOCKS_IN_MHZ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Local Bus Definitions |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
||||||
|
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
||||||
|
|
||||||
|
#define CONFIG_SYS_BCSR_BASE 0xf8000000 |
||||||
|
#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE |
||||||
|
|
||||||
|
/*Chip select 0 - Flash*/ |
||||||
|
#define CONFIG_SYS_BR0_PRELIM 0xfe000801 |
||||||
|
#define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 |
||||||
|
|
||||||
|
/*Chip slelect 1 - BCSR*/ |
||||||
|
#define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
||||||
|
#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 |
||||||
|
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ |
||||||
|
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||||
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||||
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||||
|
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER |
||||||
|
#define CONFIG_SYS_FLASH_CFI |
||||||
|
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM on the LocalBus |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||||
|
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
||||||
|
#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ |
||||||
|
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
||||||
|
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
||||||
|
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||||
|
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||||
|
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||||
|
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||||
|
|
||||||
|
/* Serial Port */ |
||||||
|
#define CONFIG_CONS_INDEX 1 |
||||||
|
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||||
|
#define CONFIG_SYS_NS16550 |
||||||
|
#define CONFIG_SYS_NS16550_SERIAL |
||||||
|
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||||
|
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||||
|
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||||
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
||||||
|
|
||||||
|
/* Use the HUSH parser*/ |
||||||
|
#define CONFIG_SYS_HUSH_PARSER |
||||||
|
#ifdef CONFIG_SYS_HUSH_PARSER |
||||||
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||||
|
#endif |
||||||
|
|
||||||
|
/* pass open firmware flat tree */ |
||||||
|
#define CONFIG_OF_LIBFDT 1 |
||||||
|
#define CONFIG_OF_BOARD_SETUP 1 |
||||||
|
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_64BIT_VSPRINTF 1 |
||||||
|
#define CONFIG_SYS_64BIT_STRTOUL 1 |
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C |
||||||
|
*/ |
||||||
|
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||||
|
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||||
|
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||||
|
#define CONFIG_I2C_MULTI_BUS |
||||||
|
#define CONFIG_I2C_CMD_TREE |
||||||
|
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||||
|
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||||
|
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
||||||
|
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
||||||
|
#define CONFIG_SYS_I2C2_OFFSET 0x3100 |
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C2 EEPROM |
||||||
|
*/ |
||||||
|
#define CONFIG_ID_EEPROM |
||||||
|
#ifdef CONFIG_ID_EEPROM |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||||
|
#endif |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||||
|
#define CONFIG_SYS_EEPROM_BUS_NUM 1 |
||||||
|
|
||||||
|
#define PLPPAR1_I2C_BIT_MASK 0x0000000F |
||||||
|
#define PLPPAR1_I2C2_VAL 0x00000000 |
||||||
|
#define PLPDIR1_I2C_BIT_MASK 0x0000000F |
||||||
|
#define PLPDIR1_I2C2_VAL 0x0000000F |
||||||
|
|
||||||
|
/*
|
||||||
|
* General PCI |
||||||
|
* Memory Addresses are mapped 1-1. I/O is mapped from 0 |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||||
|
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
||||||
|
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||||
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 |
||||||
|
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 |
||||||
|
#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 |
||||||
|
#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 |
||||||
|
|
||||||
|
#ifdef CONFIG_QE |
||||||
|
/*
|
||||||
|
* QE UEC ethernet configuration |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) |
||||||
|
#define CONFIG_UEC_ETH |
||||||
|
#define CONFIG_ETHPRIME "FSL UEC0" |
||||||
|
#define CONFIG_PHY_MODE_NEED_CHANGE |
||||||
|
|
||||||
|
#define CONFIG_UEC_ETH1 /* GETH1 */ |
||||||
|
#define CONFIG_HAS_ETH0 |
||||||
|
|
||||||
|
#ifdef CONFIG_UEC_ETH1 |
||||||
|
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
||||||
|
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE |
||||||
|
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
||||||
|
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH |
||||||
|
#define CONFIG_SYS_UEC1_PHY_ADDR 7 |
||||||
|
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_UEC_ETH2 /* GETH2 */ |
||||||
|
#define CONFIG_HAS_ETH1 |
||||||
|
|
||||||
|
#ifdef CONFIG_UEC_ETH2 |
||||||
|
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
||||||
|
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE |
||||||
|
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
||||||
|
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH |
||||||
|
#define CONFIG_SYS_UEC2_PHY_ADDR 1 |
||||||
|
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID |
||||||
|
#endif |
||||||
|
|
||||||
|
#endif /* CONFIG_QE */ |
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) |
||||||
|
|
||||||
|
#define CONFIG_NET_MULTI |
||||||
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||||
|
|
||||||
|
#undef CONFIG_EEPRO100 |
||||||
|
#undef CONFIG_TULIP |
||||||
|
|
||||||
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||||
|
|
||||||
|
#endif /* CONFIG_PCI */ |
||||||
|
|
||||||
|
#ifndef CONFIG_NET_MULTI |
||||||
|
#define CONFIG_NET_MULTI 1 |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment |
||||||
|
*/ |
||||||
|
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||||
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
|
||||||
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||||
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||||
|
|
||||||
|
/* QE microcode/firmware address */ |
||||||
|
#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options |
||||||
|
*/ |
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE |
||||||
|
#define CONFIG_BOOTP_BOOTPATH |
||||||
|
#define CONFIG_BOOTP_GATEWAY |
||||||
|
#define CONFIG_BOOTP_HOSTNAME |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration. |
||||||
|
*/ |
||||||
|
#include <config_cmd_default.h> |
||||||
|
|
||||||
|
#define CONFIG_CMD_PING |
||||||
|
#define CONFIG_CMD_I2C |
||||||
|
#define CONFIG_CMD_MII |
||||||
|
#define CONFIG_CMD_ELF |
||||||
|
#define CONFIG_CMD_IRQ |
||||||
|
#define CONFIG_CMD_SETEXPR |
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) |
||||||
|
#define CONFIG_CMD_PCI |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||||
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||||
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ |
||||||
|
#else |
||||||
|
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||||
|
#endif |
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||||
|
/* Print Buffer Size */ |
||||||
|
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||||
|
/* Boot Argument Buffer Size */ |
||||||
|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data |
||||||
|
* have to be in the first 8 MB of memory, since this is |
||||||
|
* the maximum mapped by the Linux kernel during initialization. |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
||||||
|
/* Initial Memory map for Linux*/ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions |
||||||
|
* |
||||||
|
* Boot Flags |
||||||
|
*/ |
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||||
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment Configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_HOSTNAME mpc8569mds |
||||||
|
#define CONFIG_ROOTPATH /nfsroot |
||||||
|
#define CONFIG_BOOTFILE your.uImage |
||||||
|
|
||||||
|
#define CONFIG_SERVERIP 192.168.1.1 |
||||||
|
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||||
|
#define CONFIG_NETMASK 255.255.255.0 |
||||||
|
|
||||||
|
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||||
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||||
|
"netdev=eth0\0" \
|
||||||
|
"consoledev=ttyS0\0" \
|
||||||
|
"ramdiskaddr=600000\0" \
|
||||||
|
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||||
|
"fdtaddr=400000\0" \
|
||||||
|
"fdtfile=your.fdt.dtb\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=$serverip:$rootpath " \
|
||||||
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs\0" \
|
||||||
|
"ramargs=setenv bootargs root=/dev/ram rw " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs\0" \
|
||||||
|
|
||||||
|
#define CONFIG_NFSBOOTCOMMAND \ |
||||||
|
"run nfsargs;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
|
"bootm $loadaddr - $fdtaddr" |
||||||
|
|
||||||
|
#define CONFIG_RAMBOOTCOMMAND \ |
||||||
|
"run ramargs;" \
|
||||||
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"bootm $loadaddr $ramdiskaddr" |
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue