* new board (eb_cpux9k2) * support for EB+CPUx9K2 board by BuS Elektronik GmbH & Co. KG * select via make eb_cpux9k2_config * this also demonstrates, how to use boards with AT91RM9200 cpu in at91 arch tree Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>master
Jens Scharsig
15 years ago
committed by
Tom Rix
parent
6799a80f76
commit
77e7273c40
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := cpux9k2.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1 @@ |
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TEXT_BASE = 0x23f00000
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@ -0,0 +1,387 @@ |
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/*
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* (C) Copyright 2008-2009 |
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* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de> |
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* Jens Scharsig <esw@bus-elektronik.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <exports.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <nand.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/at91_pio.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_mc.h> |
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#ifdef CONFIG_STATUS_LED |
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#include <status_led.h> |
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#endif |
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#ifdef CONFIG_VIDEO |
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#include <bus_vcxk.h> |
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extern unsigned long display_width; |
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extern unsigned long display_height; |
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#endif |
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#ifdef CONFIG_CMD_NAND |
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void cpux9k2_nand_hw_init(void); |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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/* Enable Ctrlc */ |
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console_init_f(); |
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/* Correct IRDA resistor problem / Set PA23_TXD in Output */ |
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writel(AT91_PMX_AA_TXD2, &pio->pioa.oer); |
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gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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#ifdef CONFIG_STATUS_LED |
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); |
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#endif |
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#ifdef CONFIG_CMD_NAND |
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cpux9k2_nand_hw_init(); |
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#endif |
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return 0; |
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} |
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#ifdef CONFIG_MISC_INIT_R |
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int misc_init_r(void) |
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{ |
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uchar mac[8]; |
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uchar tm; |
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uchar midx; |
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uchar macn6, macn7; |
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#ifdef CONFIG_NET_MULTI |
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if (getenv("ethaddr") == NULL) { |
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00, |
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, |
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(uchar *) &mac, sizeof(mac)) != 0) { |
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puts("Error reading MAC from EEPROM\n"); |
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} else { |
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tm = 0; |
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macn6 = 0; |
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macn7 = 0xFF; |
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for (midx = 0; midx < 6; midx++) { |
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if ((mac[midx] != 0) && (mac[midx] != 0xFF)) |
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tm++; |
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macn6 += mac[midx]; |
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macn7 ^= mac[midx]; |
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} |
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if ((macn6 != mac[6]) || (macn7 != mac[7])) |
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tm = 0; |
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if (tm) |
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eth_setenv_enetaddr("ethaddr", mac); |
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else |
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puts("Error: invalid MAC at EEPROM\n"); |
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} |
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} |
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#endif |
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gd->jt[XF_do_reset] = (void *) do_reset; |
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#ifdef CONFIG_STATUS_LED |
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status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); |
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#endif |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_RESET_PHY_R |
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void reset_phy(void) |
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{ |
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udelay(10000); |
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eth_init(gd->bd); |
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} |
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#endif |
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/*
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* DRAM initialisations |
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*/ |
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int dram_init(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM; |
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gd->bd->bi_dram[0].size = |
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get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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return 0; |
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} |
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/*
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* Ethernet initialisations |
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*/ |
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#ifdef CONFIG_DRIVER_AT91EMAC |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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rc = at91emac_register(bis, (u32) AT91_EMAC_BASE); |
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return rc; |
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} |
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#endif |
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/*
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* Disk On Chip (NAND) Millenium initialization. |
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* The NAND lives in the CS2* space |
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*/ |
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#if defined(CONFIG_CMD_NAND) |
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#define MASK_ALE (1 << 22) /* our ALE is AD22 */ |
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#define MASK_CLE (1 << 21) /* our CLE is AD21 */ |
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void cpux9k2_nand_hw_init(void) |
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{ |
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unsigned long csr; |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE; |
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/* Setup Smart Media, fitst enable the address range of CS3 */ |
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writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa); |
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/* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */ |
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csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) | |
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AT91_SMC_CSR_NWS(3) | |
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AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 | |
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AT91_SMC_CSR_WSEN; |
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writel(csr, &mc->smc.csr[3]); |
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writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr); |
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writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, |
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&pio->pioc.pdr); |
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/* Configure PC2 as input (signal Nand READY ) */ |
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writel(AT91_PMX_CA_BFAVD, &pio->pioc.per); |
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writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */ |
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writel(AT91_PMX_CA_BFCK, &pio->pioc.codr); |
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/* PIOC clock enabling */ |
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writel(1 << AT91_ID_PIOC, &pmc->pcer); |
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} |
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static void board_nand_hwcontrol(struct mtd_info *mtd, |
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int cmd, unsigned int ctrl) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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struct nand_chip *this = mtd->priv; |
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
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if (ctrl & NAND_CTRL_CHANGE) { |
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IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); |
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if (ctrl & NAND_CLE) |
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IO_ADDR_W |= MASK_CLE; |
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if (ctrl & NAND_ALE) |
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IO_ADDR_W |= MASK_ALE; |
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if ((ctrl & NAND_NCE)) |
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writel(1, &pio->pioc.codr); |
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else |
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writel(1, &pio->pioc.sodr); |
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this->IO_ADDR_W = (void *) IO_ADDR_W; |
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} |
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if (cmd != NAND_CMD_NONE) |
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writeb(cmd, this->IO_ADDR_W); |
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} |
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static int board_nand_dev_ready(struct mtd_info *mtd) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0); |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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cpux9k2_nand_hw_init(); |
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nand->ecc.mode = NAND_ECC_SOFT; |
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nand->cmd_ctrl = board_nand_hwcontrol; |
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nand->dev_ready = board_nand_dev_ready; |
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nand->chip_delay = 20; |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_VIDEO) |
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/*
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* drv_video_init |
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* FUNCTION: initialize VCxK device |
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*/ |
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int drv_video_init(void) |
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{ |
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#ifdef CONFIG_SPLASH_SCREEN |
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unsigned long splash; |
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#endif |
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char *s; |
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unsigned long csr; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE; |
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printf("Init Video as "); |
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s = getenv("displaywidth"); |
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if (s != NULL) |
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display_width = simple_strtoul(s, NULL, 10); |
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else |
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display_width = 256; |
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s = getenv("displayheight"); |
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if (s != NULL) |
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display_height = simple_strtoul(s, NULL, 10); |
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else |
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display_height = 256; |
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printf("%ld x %ld pixel matrix\n", display_width, display_height); |
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/* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */ |
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csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) | |
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AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) | |
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AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 | |
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AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN; |
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writel(csr, &mc->smc.csr[2]); |
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writel(1 << AT91_ID_PIOB, &pmc->pcer); |
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vcxk_init(display_width, display_height); |
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#ifdef CONFIG_SPLASH_SCREEN |
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s = getenv("splashimage"); |
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if (s != NULL) { |
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splash = simple_strtoul(s, NULL, 16); |
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printf("use splashimage: %lx\n", splash); |
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video_display_bitmap(splash, 0, 0); |
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} |
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#endif |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_SOFT_I2C |
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void i2c_init_board(void) |
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{ |
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u32 pin; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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writel(1 << AT91_ID_PIOA, &pmc->pcer); |
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pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; |
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writel(pin, &pio->pioa.idr); |
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writel(pin, &pio->pioa.pudr); |
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writel(pin, &pio->pioa.per); |
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writel(pin, &pio->pioa.oer); |
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writel(pin, &pio->pioa.sodr); |
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} |
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#endif |
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/*--------------------------------------------------------------------------*/ |
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#ifdef CONFIG_STATUS_LED |
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void __led_toggle(led_id_t mask) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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if (readl(&pio->piod.odsr) & mask) |
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writel(mask, &pio->piod.codr); |
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else |
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writel(mask, &pio->piod.codr); |
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} |
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void __led_init(led_id_t mask, int state) |
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{ |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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writel(1 << AT91_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */ |
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/* Disable peripherals on LEDs */ |
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writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per); |
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/* Enable pins as outputs */ |
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writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer); |
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/* Turn all LEDs OFF */ |
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writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr); |
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__led_set(mask, state); |
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} |
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void __led_set(led_id_t mask, int state) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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if (state == STATUS_LED_ON) |
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writel(mask, &pio->piod.codr); |
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else |
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writel(mask, &pio->piod.sodr); |
||||||
|
} |
||||||
|
|
||||||
|
#endif |
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------*/ |
||||||
|
|
||||||
|
int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||||
|
{ |
||||||
|
int rcode = 0; |
||||||
|
ulong side; |
||||||
|
ulong bright; |
||||||
|
|
||||||
|
switch (argc) { |
||||||
|
case 3: |
||||||
|
side = simple_strtoul(argv[1], NULL, 10); |
||||||
|
bright = simple_strtoul(argv[2], NULL, 10); |
||||||
|
if ((side >= 0) && (side <= 3) && |
||||||
|
(bright >= 0) && (bright <= 1000)) { |
||||||
|
vcxk_setbrightness(side, bright); |
||||||
|
rcode = 0; |
||||||
|
} else { |
||||||
|
printf("parameters out of range\n"); |
||||||
|
printf("Usage:\n%s\n", cmdtp->usage); |
||||||
|
rcode = 1; |
||||||
|
} |
||||||
|
break; |
||||||
|
default: |
||||||
|
printf("Usage:\n%s\n", cmdtp->usage); |
||||||
|
rcode = 1; |
||||||
|
break; |
||||||
|
} |
||||||
|
return rcode; |
||||||
|
} |
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------*/ |
||||||
|
|
||||||
|
U_BOOT_CMD( |
||||||
|
bright, 3, 0, do_brightness, |
||||||
|
"bright - sets the display brightness\n", |
||||||
|
" <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n" |
||||||
|
); |
||||||
|
|
||||||
|
/* EOF cpu9k2.c */ |
||||||
@ -0,0 +1,415 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2008-2009 |
||||||
|
* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de> |
||||||
|
* Jens Scharsig <esw@bus-elektronik.de> |
||||||
|
* |
||||||
|
* Configuation settings for the EB+CPUx9K2 board. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef _CONFIG_EB_CPUx9K2_H_ |
||||||
|
#define _CONFIG_EB_CPUx9K2_H_ |
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------*/ |
||||||
|
|
||||||
|
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
||||||
|
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ |
||||||
|
#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */ |
||||||
|
#define USE_920T_MMU 1 |
||||||
|
|
||||||
|
#define CONFIG_VERSION_VARIABLE 1 |
||||||
|
#define CONFIG_IDENT_STRING " on EB+CPUx9K2" |
||||||
|
|
||||||
|
#include <asm/arch/hardware.h> /* needed for port definitions */ |
||||||
|
|
||||||
|
#define CONFIG_MISC_INIT_R |
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ |
||||||
|
#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 |
||||||
|
#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ |
||||||
|
|
||||||
|
|
||||||
|
#define CONFIG_BOOT_RETRY_TIME 30 |
||||||
|
#define CONFIG_CMDLINE_EDITING |
||||||
|
|
||||||
|
#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ |
||||||
|
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||||
|
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
||||||
|
#define CONFIG_SYS_PBSIZE \ |
||||||
|
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||||
|
|
||||||
|
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* ARM asynchronous clock |
||||||
|
*/ |
||||||
|
|
||||||
|
#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */ |
||||||
|
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) |
||||||
|
#define CONFIG_SYS_HZ 1000 |
||||||
|
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) |
||||||
|
|
||||||
|
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||||
|
|
||||||
|
#define CONFIG_CMDLINE_TAG 1 |
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||||
|
#define CONFIG_INITRD_TAG 1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 |
||||||
|
/* flash */ |
||||||
|
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 |
||||||
|
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ |
||||||
|
|
||||||
|
/* clocks */ |
||||||
|
#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */ |
||||||
|
#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */ |
||||||
|
#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Size of malloc() pool |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024) |
||||||
|
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||||
|
|
||||||
|
/*
|
||||||
|
* sdram |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1 |
||||||
|
#define PHYS_SDRAM 0x20000000 |
||||||
|
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
||||||
|
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ |
||||||
|
PHYS_SDRAM_SIZE - 0x00400000 - \
|
||||||
|
CONFIG_SYS_MALLOC_LEN) |
||||||
|
|
||||||
|
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ |
||||||
|
#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 |
||||||
|
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 |
||||||
|
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ |
||||||
|
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */ |
||||||
|
#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ |
||||||
|
#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ |
||||||
|
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ |
||||||
|
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ |
||||||
|
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ |
||||||
|
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ |
||||||
|
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ |
||||||
|
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <config_cmd_default.h> |
||||||
|
|
||||||
|
#define CONFIG_CMD_BMP |
||||||
|
#define CONFIG_CMD_DATE |
||||||
|
#define CONFIG_CMD_DHCP |
||||||
|
#define CONFIG_CMD_I2C |
||||||
|
#define CONFIG_CMD_JFFS2 |
||||||
|
#define CONFIG_CMD_MII |
||||||
|
#define CONFIG_CMD_NAND |
||||||
|
#define CONFIG_CMD_PING |
||||||
|
#define CONFIG_I2C_CMD_NO_FLAT |
||||||
|
#define CONFIG_I2C_CMD_TREE |
||||||
|
|
||||||
|
#define CONFIG_SYS_LONGHELP |
||||||
|
|
||||||
|
/*
|
||||||
|
* Filesystems |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_JFFS2_NAND 1 |
||||||
|
|
||||||
|
#ifndef CONFIG_JFFS2_CMDLINE |
||||||
|
#define CONFIG_JFFS2_DEV "nand0" |
||||||
|
#define CONFIG_JFFS2_PART_OFFSET 0 |
||||||
|
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF |
||||||
|
#else |
||||||
|
#define MTDIDS_DEFAULT "nor0=0,nand0=1" |
||||||
|
#define MTDPARTS_DEFAULT "mtdparts=" \ |
||||||
|
"0:" \
|
||||||
|
"384k(U-Boot)," \
|
||||||
|
"128k(Env)," \
|
||||||
|
"128k(Splash)," \
|
||||||
|
"4M(Kernel)," \
|
||||||
|
"-(FS)" \
|
||||||
|
";" \
|
||||||
|
"1:" \
|
||||||
|
"-(jffs2)" |
||||||
|
#endif /* CONFIG_JFFS2_CMDLINE */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Hardware drivers |
||||||
|
*/ |
||||||
|
|
||||||
|
/*
|
||||||
|
* UART/CONSOLE |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
#define CONFIG_AT91RM9200_USART |
||||||
|
#define CONFIG_DBGU /* define DBGU as console */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* network |
||||||
|
*/ |
||||||
|
#define CONFIG_NET_MULTI 1 |
||||||
|
|
||||||
|
#define CONFIG_NET_RETRY_COUNT 10 |
||||||
|
#define CONFIG_RESET_PHY_R 1 |
||||||
|
|
||||||
|
#define CONFIG_DRIVER_AT91EMAC 1 |
||||||
|
#define CONFIG_DRIVER_AT91EMAC_QUIET 1 |
||||||
|
#define CONFIG_SYS_RX_ETH_BUFFER 8 |
||||||
|
#define CONFIG_MII 1 |
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options |
||||||
|
*/ |
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE |
||||||
|
#define CONFIG_BOOTP_BOOTPATH |
||||||
|
#define CONFIG_BOOTP_GATEWAY |
||||||
|
#define CONFIG_BOOTP_HOSTNAME |
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C-Bus |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_I2C_SPEED 50000 |
||||||
|
#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ |
||||||
|
|
||||||
|
#ifndef CONFIG_HARD_I2C |
||||||
|
#define CONFIG_SOFT_I2C |
||||||
|
|
||||||
|
/* Software I2C driver configuration */ |
||||||
|
|
||||||
|
#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */ |
||||||
|
#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_I2C_INIT_BOARD |
||||||
|
|
||||||
|
#define I2C_INIT i2c_init_board(); |
||||||
|
#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); |
||||||
|
#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); |
||||||
|
#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) |
||||||
|
#define I2C_SDA(bit) \ |
||||||
|
if (bit) \
|
||||||
|
writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
|
||||||
|
else \
|
||||||
|
writel(AT91_PMX_AA_TWD, &pio->pioa.codr); |
||||||
|
#define I2C_SCL(bit) \ |
||||||
|
if (bit) \
|
||||||
|
writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
|
||||||
|
else \
|
||||||
|
writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); |
||||||
|
|
||||||
|
#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) |
||||||
|
|
||||||
|
#endif /* CONFIG_HARD_I2C */ |
||||||
|
|
||||||
|
/* I2C-RTC */ |
||||||
|
|
||||||
|
#ifdef CONFIG_CMD_DATE |
||||||
|
#define CONFIG_RTC_DS1338 |
||||||
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||||
|
#endif |
||||||
|
|
||||||
|
/* EEPROM */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||||
|
|
||||||
|
/* FLASH organization */ |
||||||
|
|
||||||
|
/* NOR-FLASH */ |
||||||
|
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||||
|
|
||||||
|
#define PHYS_FLASH_1 0x10000000 |
||||||
|
#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */ |
||||||
|
#define CONFIG_SYS_FLASH_CFI 1 |
||||||
|
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_PROTECTION 1 |
||||||
|
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 512 |
||||||
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 6000 |
||||||
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 |
||||||
|
|
||||||
|
/* NAND */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||||
|
#define CONFIG_SYS_NAND_BASE 0x40000000 |
||||||
|
#define CONFIG_SYS_NAND_DBW_8 1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_64BIT_VSPRINTF 1 |
||||||
|
|
||||||
|
/* Status LED's */ |
||||||
|
|
||||||
|
#define CONFIG_STATUS_LED 1 |
||||||
|
#define CONFIG_BOARD_SPECIFIC_LED 1 |
||||||
|
|
||||||
|
#define STATUS_LED_BOOT 1 |
||||||
|
#define STATUS_LED_ACTIVE 0 |
||||||
|
|
||||||
|
#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */ |
||||||
|
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||||
|
#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */ |
||||||
|
#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */ |
||||||
|
#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */ |
||||||
|
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4) |
||||||
|
|
||||||
|
#define CONFIG_VIDEO 1 |
||||||
|
|
||||||
|
/* Options */ |
||||||
|
|
||||||
|
#ifdef CONFIG_VIDEO |
||||||
|
|
||||||
|
#define CONFIG_VIDEO_VCXK 1 |
||||||
|
|
||||||
|
#define CONFIG_SPLASH_SCREEN 1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4 |
||||||
|
#define CONFIG_SYS_VCXK_BASE 0x30000000 |
||||||
|
|
||||||
|
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3) |
||||||
|
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob |
||||||
|
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr |
||||||
|
|
||||||
|
#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5) |
||||||
|
#define CONFIG_SYS_VCXK_ENABLE_PORT piob |
||||||
|
#define CONFIG_SYS_VCXK_ENABLE_DDR oer |
||||||
|
|
||||||
|
#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2) |
||||||
|
#define CONFIG_SYS_VCXK_REQUEST_PORT piob |
||||||
|
#define CONFIG_SYS_VCXK_REQUEST_DDR oer |
||||||
|
|
||||||
|
#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4) |
||||||
|
#define CONFIG_SYS_VCXK_INVERT_PORT piob |
||||||
|
#define CONFIG_SYS_VCXK_INVERT_DDR oer |
||||||
|
|
||||||
|
#define CONFIG_SYS_VCXK_RESET_PIN (1<<6) |
||||||
|
#define CONFIG_SYS_VCXK_RESET_PORT piob |
||||||
|
#define CONFIG_SYS_VCXK_RESET_DDR oer |
||||||
|
|
||||||
|
#endif /* CONFIG_VIDEO */ |
||||||
|
|
||||||
|
/* Environment */ |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 5 |
||||||
|
|
||||||
|
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||||
|
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) |
||||||
|
#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "run nfsboot" |
||||||
|
|
||||||
|
#define CONFIG_NFSBOOTCOMMAND \ |
||||||
|
"dhcp $(copy_addr) uImage_cpux9k2;" \
|
||||||
|
"run bootargsdefaults;" \
|
||||||
|
"set bootargs $(bootargs) boot=nfs " \
|
||||||
|
";echo $(bootargs)" \
|
||||||
|
";bootm" |
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||||
|
"displaywidth=256\0" \
|
||||||
|
"displayheight=512\0" \
|
||||||
|
"displaybsteps=1023\0" \
|
||||||
|
"ubootaddr=10000000\0" \
|
||||||
|
"splashimage=10080000\0" \
|
||||||
|
"kerneladdr=100A0000\0" \
|
||||||
|
"kernelsize=00400000\0" \
|
||||||
|
"rootfsaddr=104A0000\0" \
|
||||||
|
"copy_addr=21200000\0" \
|
||||||
|
"rootfssize=00B60000\0" \
|
||||||
|
"bootargsdefaults=set bootargs " \
|
||||||
|
"console=ttyS0,115200 " \
|
||||||
|
"video=vcxk_fb:xres:${displaywidth}," \
|
||||||
|
"yres:${displayheight}," \
|
||||||
|
"bres:${displaybsteps} " \
|
||||||
|
"mem=62M " \
|
||||||
|
"panic=10 " \
|
||||||
|
"uboot=\\\"${ver}\\\" " \
|
||||||
|
"\0" \
|
||||||
|
"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
|
||||||
|
"dhcp $(copy_addr) uImage_cpux9k2;" \
|
||||||
|
"erase $(kerneladdr) +$(kernelsize);" \
|
||||||
|
"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
|
||||||
|
"protect on $(kerneladdr) +$(kernelsize)" \
|
||||||
|
"\0" \
|
||||||
|
"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
|
||||||
|
"dhcp $(copy_addr) rfs;" \
|
||||||
|
"erase $(rootfsaddr) +$(rootfssize);" \
|
||||||
|
"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
|
||||||
|
"\0" \
|
||||||
|
"update_uboot=protect off 10000000 1005FFFF;" \
|
||||||
|
"dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
|
||||||
|
"erase 10000000 1005FFFF;" \
|
||||||
|
"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
|
||||||
|
"protect on 10000000 1005FFFF;reset\0" \
|
||||||
|
"update_splash=protect off $(splashimage) +20000;" \
|
||||||
|
"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
|
||||||
|
"erase $(splashimage) +20000;" \
|
||||||
|
"cp.b $(fileaddr) 10080000 $(filesize);" \
|
||||||
|
"protect on $(splashimage) +20000;reset\0" \
|
||||||
|
"emergency=run bootargsdefaults;" \
|
||||||
|
"set bootargs $(bootargs) root=initramfs boot=emergency " \
|
||||||
|
";bootm $(kerneladdr)\0" \
|
||||||
|
"netemergency=run bootargsdefaults;" \
|
||||||
|
"dhcp $(copy_addr) uImage_cpux9k2;" \
|
||||||
|
"set bootargs $(bootargs) root=initramfs boot=emergency " \
|
||||||
|
";bootm $(copy_addr)\0" \
|
||||||
|
"norboot=run bootargsdefaults;" \
|
||||||
|
"set bootargs $(bootargs) root=initramfs boot=local " \
|
||||||
|
";bootm $(kerneladdr)\0" \
|
||||||
|
"nandboot=run bootargsdefaults;" \
|
||||||
|
"set bootargs $(bootargs) root=initramfs boot=nand " \
|
||||||
|
";bootm $(kerneladdr)\0" \
|
||||||
|
"uu=run update_uboot\0" \
|
||||||
|
"ur=run update_root;run nk\0" \
|
||||||
|
"nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
|
||||||
|
"boot=local " \
|
||||||
|
";echo $(bootargs)" \
|
||||||
|
";dhcp uImage_cpux9k2;bootm\0" \
|
||||||
|
"nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
|
||||||
|
"boot=nand " \
|
||||||
|
";echo $(bootargs)" \
|
||||||
|
";dhcp uImage_cpux9k2;bootm\0" \
|
||||||
|
" " |
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------*/ |
||||||
|
|
||||||
|
#endif |
||||||
|
|
||||||
|
/* EOF */ |
||||||
Loading…
Reference in new issue