Merge branch 'master' of git://www.denx.de/git/u-boot-imx

arch/arm/Kconfig

@@ -578,6 +578,13 @@ config TARGET_MX6SXSABRESD
 	select DM
 	select DM_THERMAL
 
+config TARGET_MX6UL_14X14_EVK
+	bool "Support mx6ul_14x14_evk"
+	select CPU_V7
+	select DM
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_GW_VENTANA
 	bool "Support gw_ventana"
 	select CPU_V7
@@ -625,14 +632,6 @@ config RMOBILE
 	bool "Renesas ARM SoCs"
 	select CPU_V7
 
-config TARGET_CM_FX6
-	bool "Support cm_fx6"
-	select CPU_V7
-	select SUPPORT_SPL
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
@@ -920,6 +919,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx6ul_14x14_evk/Kconfig"
 source "board/freescale/vf610twr/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/genesi/mx51_efikamx/Kconfig"

arch/arm/cpu/armv7/mx6/Kconfig

@@ -25,17 +25,26 @@ config MX6SL
 config MX6SX
 	bool
 
+config MX6UL
+	select SYS_L2CACHE_OFF
+	bool
+
 choice
 	prompt "MX6 board select"
 	optional
 
+config TARGET_CM_FX6
+	bool "Support CM-FX6"
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_SECOMX6
 	bool "Support secomx6 boards"
-	select CPU_V7
 
 config TARGET_TQMA6
 	bool "TQ Systems TQMa6 board"
-	select CPU_V7
 
 endchoice
 

arch/arm/cpu/armv7/mx6/clock.c

@@ -81,43 +81,37 @@ void enable_usboh3_clk(unsigned char enable)
 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
 void enable_enet_clk(unsigned char enable)
 {
-	u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+	u32 mask, *addr;
+
+	if (is_cpu_type(MXC_CPU_MX6UL)) {
+		mask = MXC_CCM_CCGR3_ENET_MASK;
+		addr = &imx_ccm->CCGR3;
+	} else {
+		mask = MXC_CCM_CCGR1_ENET_MASK;
+		addr = &imx_ccm->CCGR1;
+	}
 
 	if (enable)
-		setbits_le32(&imx_ccm->CCGR1, mask);
+		setbits_le32(addr, mask);
 	else
-		clrbits_le32(&imx_ccm->CCGR1, mask);
+		clrbits_le32(addr, mask);
 }
 #endif
 
 #ifdef CONFIG_MXC_UART
 void enable_uart_clk(unsigned char enable)
 {
-	u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
-
-	if (enable)
-		setbits_le32(&imx_ccm->CCGR5, mask);
-	else
-		clrbits_le32(&imx_ccm->CCGR5, mask);
-}
-#endif
-
-#ifdef CONFIG_SPI
-/* spi_num can be from 0 - 4 */
-int enable_cspi_clock(unsigned char enable, unsigned spi_num)
-{
 	u32 mask;
 
-	if (spi_num > 4)
+	if (is_cpu_type(MXC_CPU_MX6UL))
-		return -EINVAL;
+		mask = MXC_CCM_CCGR5_UART_MASK;
+	else
+		mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 
-	mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
 	if (enable)
-		setbits_le32(&imx_ccm->CCGR1, mask);
+		setbits_le32(&imx_ccm->CCGR5, mask);
 	else
-		clrbits_le32(&imx_ccm->CCGR1, mask);
+		clrbits_le32(&imx_ccm->CCGR5, mask);
-
-	return 0;
 }
 #endif
 
@@ -145,6 +139,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
 	u32 reg;
 	u32 mask;
+	u32 *addr;
 
 	if (i2c_num > 3)
 		return -EINVAL;
@@ -159,14 +154,19 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 			reg &= ~mask;
 		__raw_writel(reg, &imx_ccm->CCGR2);
 	} else {
-		mask = MXC_CCM_CCGR_CG_MASK
+		if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
-			<< (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+			mask = MXC_CCM_CCGR6_I2C4_MASK;
-		reg = __raw_readl(&imx_ccm->CCGR1);
+			addr = &imx_ccm->CCGR6;
+		} else {
+			mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+			addr = &imx_ccm->CCGR1;
+		}
+		reg = __raw_readl(addr);
 		if (enable)
 			reg |= mask;
 		else
 			reg &= ~mask;
-		__raw_writel(reg, &imx_ccm->CCGR1);
+		__raw_writel(reg, addr);
 	}
 	return 0;
 }
@@ -227,9 +227,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
 	switch (pll) {
 	case PLL_BUS:
-		if (pfd_num == 3) {
+		if (!is_cpu_type(MXC_CPU_MX6UL)) {
-			/* No PFD3 on PPL2 */
+			if (pfd_num == 3) {
-			return 0;
+				/* No PFD3 on PPL2 */
+				return 0;
+			}
 		}
 		div = __raw_readl(&imx_ccm->analog_pfd_528);
 		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
@@ -261,10 +263,12 @@ static u32 get_mcu_main_clk(void)
 
 u32 get_periph_clk(void)
 {
-	u32 reg, freq = 0;
+	u32 reg, div = 0, freq = 0;
 
 	reg = __raw_readl(&imx_ccm->cbcdr);
 	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+		       MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 		reg = __raw_readl(&imx_ccm->cbcmr);
 		reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 		reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
@@ -304,7 +308,7 @@ u32 get_periph_clk(void)
 		}
 	}
 
-	return freq;
+	return freq / (div + 1);
 }
 
 static u32 get_ipg_clk(void)
@@ -323,10 +327,12 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
-		return MXC_HCLK; /* OSC 24Mhz */
+		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-#endif
+			return MXC_HCLK; /* OSC 24Mhz */
+	}
+
 	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
 	return get_ipg_clk() / (perclk_podf + 1);
@@ -337,10 +343,13 @@ static u32 get_uart_clk(void)
 	u32 reg, uart_podf;
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+
-	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-		freq = MXC_HCLK;
+	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
-#endif
+		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+			freq = MXC_HCLK;
+	}
+
 	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
@@ -352,8 +361,14 @@ static u32 get_cspi_clk(void)
 	u32 reg, cspi_podf;
 
 	reg = __raw_readl(&imx_ccm->cscdr2);
-	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
+	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
-	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+	if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
+	    is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+			return MXC_HCLK / (cspi_podf + 1);
+	}
 
 	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
@@ -405,47 +420,60 @@ static u32 get_emi_slow_clk(void)
 	return root_freq / (emi_slow_podf + 1);
 }
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 static u32 get_mmdc_ch0_clk(void)
 {
 	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-	u32 freq, podf;
 
-	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+	u32 freq, podf, per2_clk2_podf;
-			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
-
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+	    is_cpu_type(MXC_CPU_MX6SL)) {
-		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
-	case 0:
+			MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
-		freq = decode_pll(PLL_BUS, MXC_HCLK);
+		if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
-		break;
+			per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
-	case 1:
+				MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
-		freq = mxc_get_pll_pfd(PLL_BUS, 2);
+			if (is_cpu_type(MXC_CPU_MX6SL)) {
-		break;
+				if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
-	case 2:
+					freq = MXC_HCLK;
-		freq = mxc_get_pll_pfd(PLL_BUS, 0);
+				else
-		break;
+					freq = decode_pll(PLL_USBOTG, MXC_HCLK);
-	case 3:
+			} else {
-		/* static / 2 divider */
+				if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
-		freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+					freq = decode_pll(PLL_BUS, MXC_HCLK);
+				else
+					freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+			}
+		} else {
+			per2_clk2_podf = 0;
+			switch ((cbcmr &
+				MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+				MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+			case 0:
+				freq = decode_pll(PLL_BUS, MXC_HCLK);
+				break;
+			case 1:
+				freq = mxc_get_pll_pfd(PLL_BUS, 2);
+				break;
+			case 2:
+				freq = mxc_get_pll_pfd(PLL_BUS, 0);
+				break;
+			case 3:
+				/* static / 2 divider */
+				freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+				break;
+			}
+		}
+		return freq / (podf + 1) / (per2_clk2_podf + 1);
+	} else {
+		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+			MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+		return get_periph_clk() / (podf + 1);
 	}
-
-	return freq / (podf + 1);
-
-}
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
-	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-	return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
-#endif
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_FSL_QSPI
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {
@@ -606,6 +634,7 @@ u32 imx_get_fecclk(void)
 	return mxc_get_clock(MXC_IPG_CLK);
 }
 
+#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 static int enable_enet_pll(uint32_t en)
 {
 	struct mxc_ccm_reg *const imx_ccm
@@ -630,8 +659,9 @@ static int enable_enet_pll(uint32_t en)
 	writel(reg, &imx_ccm->analog_pll_enet);
 	return 0;
 }
+#endif
 
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
 static void ungate_sata_clock(void)
 {
 	struct mxc_ccm_reg *const imx_ccm =
@@ -640,18 +670,7 @@ static void ungate_sata_clock(void)
 	/* Enable SATA clock. */
 	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 }
-#endif
 
-static void ungate_pcie_clock(void)
-{
-	struct mxc_ccm_reg *const imx_ccm =
-		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* Enable PCIe clock. */
-	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
-
-#ifndef CONFIG_MX6SX
 int enable_sata_clock(void)
 {
 	ungate_sata_clock();
@@ -667,6 +686,16 @@ void disable_sata_clock(void)
 }
 #endif
 
+#ifdef CONFIG_PCIE_IMX
+static void ungate_pcie_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Enable PCIe clock. */
+	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
 int enable_pcie_clock(void)
 {
 	struct anatop_regs *anatop_regs =
@@ -706,7 +735,7 @@ int enable_pcie_clock(void)
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
 	/* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
 	ungate_sata_clock();
 #endif
 	ungate_pcie_clock();
@@ -714,6 +743,7 @@ int enable_pcie_clock(void)
 	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
+#endif
 
 #ifdef CONFIG_SECURE_BOOT
 void hab_caam_clock_enable(unsigned char enable)
@@ -856,6 +886,11 @@ void enable_ipu_clock(void)
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
+
+	if (is_mx6dqp()) {
+		setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+		setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+	}
 }
 #endif
 /***************************************************/

arch/arm/cpu/armv7/mx6/ddr.c

@@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
+#ifdef CONFIG_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+		      const struct mx6ul_iomux_ddr_regs *ddr,
+		      const struct mx6ul_iomux_grp_regs *grp)
+{
+	struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+	struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+	mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+	mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+	/* DDR IO TYPE */
+	writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+	writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+	/* CLOCK */
+	writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+	/* ADDRESS */
+	writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+	writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+	writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+	/* Control */
+	writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+	writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+	writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+	writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+	writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+	/* Data Strobes */
+	writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+	writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+	writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+	/* Data */
+	writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+	writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+	writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+	writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+	writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
@@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-#ifdef CONFIG_MX6SX
+#define MMDC1(entry, value) do {					  \
-#define MMDC1(entry, value)	do {} while (0)
+	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))	  \
-#else
+		mmdc1->entry = value;					  \
-#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
+	} while (0)
-#endif
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		  const struct mx6_mmdc_calibration *calib,
 		  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
 	volatile struct mmdc_p_regs *mmdc0;
-#ifndef CONFIG_MX6SX
 	volatile struct mmdc_p_regs *mmdc1;
-#endif
 	u32 val;
 	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-#ifndef CONFIG_MX6SX
+	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
-	mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-#endif
 
 	/* Limit mem_speed for MX6D/MX6Q */
 	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {

arch/arm/cpu/armv7/mx6/hab.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -111,6 +111,153 @@
  * +------------+ + CSF_PAD_SIZE
  */
 
+#define MAX_RECORD_BYTES     (8*1024) /* 4 kbytes */
+
+struct record {
+	uint8_t  tag;						/* Tag */
+	uint8_t  len[2];					/* Length */
+	uint8_t  par;						/* Version */
+	uint8_t  contents[MAX_RECORD_BYTES];/* Record Data */
+	bool	 any_rec_flag;
+};
+
+char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
+				   "RSN = HAB_ENG_FAIL (0x30)\n",
+				   "RSN = HAB_INV_ADDRESS (0x22)\n",
+				   "RSN = HAB_INV_ASSERTION (0x0C)\n",
+				   "RSN = HAB_INV_CALL (0x28)\n",
+				   "RSN = HAB_INV_CERTIFICATE (0x21)\n",
+				   "RSN = HAB_INV_COMMAND (0x06)\n",
+				   "RSN = HAB_INV_CSF (0x11)\n",
+				   "RSN = HAB_INV_DCD (0x27)\n",
+				   "RSN = HAB_INV_INDEX (0x0F)\n",
+				   "RSN = HAB_INV_IVT (0x05)\n",
+				   "RSN = HAB_INV_KEY (0x1D)\n",
+				   "RSN = HAB_INV_RETURN (0x1E)\n",
+				   "RSN = HAB_INV_SIGNATURE (0x18)\n",
+				   "RSN = HAB_INV_SIZE (0x17)\n",
+				   "RSN = HAB_MEM_FAIL (0x2E)\n",
+				   "RSN = HAB_OVR_COUNT (0x2B)\n",
+				   "RSN = HAB_OVR_STORAGE (0x2D)\n",
+				   "RSN = HAB_UNS_ALGORITHM (0x12)\n",
+				   "RSN = HAB_UNS_COMMAND (0x03)\n",
+				   "RSN = HAB_UNS_ENGINE (0x0A)\n",
+				   "RSN = HAB_UNS_ITEM (0x24)\n",
+				   "RSN = HAB_UNS_KEY (0x1B)\n",
+				   "RSN = HAB_UNS_PROTOCOL (0x14)\n",
+				   "RSN = HAB_UNS_STATE (0x09)\n",
+				   "RSN = INVALID\n",
+				   NULL};
+
+char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
+				   "STS = HAB_FAILURE (0x33)\n",
+				   "STS = HAB_WARNING (0x69)\n",
+				   "STS = INVALID\n",
+				   NULL};
+
+char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
+				   "ENG = HAB_ENG_SCC (0x03)\n",
+				   "ENG = HAB_ENG_RTIC (0x05)\n",
+				   "ENG = HAB_ENG_SAHARA (0x06)\n",
+				   "ENG = HAB_ENG_CSU (0x0A)\n",
+				   "ENG = HAB_ENG_SRTC (0x0C)\n",
+				   "ENG = HAB_ENG_DCP (0x1B)\n",
+				   "ENG = HAB_ENG_CAAM (0x1D)\n",
+				   "ENG = HAB_ENG_SNVS (0x1E)\n",
+				   "ENG = HAB_ENG_OCOTP (0x21)\n",
+				   "ENG = HAB_ENG_DTCP (0x22)\n",
+				   "ENG = HAB_ENG_ROM (0x36)\n",
+				   "ENG = HAB_ENG_HDCP (0x24)\n",
+				   "ENG = HAB_ENG_RTL (0x77)\n",
+				   "ENG = HAB_ENG_SW (0xFF)\n",
+				   "ENG = INVALID\n",
+				   NULL};
+
+char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
+				   "CTX = HAB_CTX_FAB (0xFF)\n",
+				   "CTX = HAB_CTX_ENTRY (0xE1)\n",
+				   "CTX = HAB_CTX_TARGET (0x33)\n",
+				   "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
+				   "CTX = HAB_CTX_DCD (0xDD)\n",
+				   "CTX = HAB_CTX_CSF (0xCF)\n",
+				   "CTX = HAB_CTX_COMMAND (0xC0)\n",
+				   "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
+				   "CTX = HAB_CTX_ASSERT (0xA0)\n",
+				   "CTX = HAB_CTX_EXIT (0xEE)\n",
+				   "CTX = INVALID\n",
+				   NULL};
+
+uint8_t hab_statuses[5] = {
+	HAB_STS_ANY,
+	HAB_FAILURE,
+	HAB_WARNING,
+	HAB_SUCCESS,
+	-1
+};
+
+uint8_t hab_reasons[26] = {
+	HAB_RSN_ANY,
+	HAB_ENG_FAIL,
+	HAB_INV_ADDRESS,
+	HAB_INV_ASSERTION,
+	HAB_INV_CALL,
+	HAB_INV_CERTIFICATE,
+	HAB_INV_COMMAND,
+	HAB_INV_CSF,
+	HAB_INV_DCD,
+	HAB_INV_INDEX,
+	HAB_INV_IVT,
+	HAB_INV_KEY,
+	HAB_INV_RETURN,
+	HAB_INV_SIGNATURE,
+	HAB_INV_SIZE,
+	HAB_MEM_FAIL,
+	HAB_OVR_COUNT,
+	HAB_OVR_STORAGE,
+	HAB_UNS_ALGORITHM,
+	HAB_UNS_COMMAND,
+	HAB_UNS_ENGINE,
+	HAB_UNS_ITEM,
+	HAB_UNS_KEY,
+	HAB_UNS_PROTOCOL,
+	HAB_UNS_STATE,
+	-1
+};
+
+uint8_t hab_contexts[12] = {
+	HAB_CTX_ANY,
+	HAB_CTX_FAB,
+	HAB_CTX_ENTRY,
+	HAB_CTX_TARGET,
+	HAB_CTX_AUTHENTICATE,
+	HAB_CTX_DCD,
+	HAB_CTX_CSF,
+	HAB_CTX_COMMAND,
+	HAB_CTX_AUT_DAT,
+	HAB_CTX_ASSERT,
+	HAB_CTX_EXIT,
+	-1
+};
+
+uint8_t hab_engines[16] = {
+	HAB_ENG_ANY,
+	HAB_ENG_SCC,
+	HAB_ENG_RTIC,
+	HAB_ENG_SAHARA,
+	HAB_ENG_CSU,
+	HAB_ENG_SRTC,
+	HAB_ENG_DCP,
+	HAB_ENG_CAAM,
+	HAB_ENG_SNVS,
+	HAB_ENG_OCOTP,
+	HAB_ENG_DTCP,
+	HAB_ENG_ROM,
+	HAB_ENG_HDCP,
+	HAB_ENG_RTL,
+	HAB_ENG_SW,
+	-1
+};
+
 bool is_hab_enabled(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -122,6 +269,28 @@ bool is_hab_enabled(void)
 	return (reg & 0x2) == 0x2;
 }
 
+static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+{
+	uint8_t idx = 0;
+	uint8_t element = list[idx];
+	while (element != -1) {
+		if (element == tgt)
+			return idx;
+		element = list[++idx];
+	}
+	return -1;
+}
+
+void process_event_record(uint8_t *event_data, size_t bytes)
+{
+	struct record *rec = (struct record *)event_data;
+
+	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
+	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
+	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
+	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+}
+
 void display_event(uint8_t *event_data, size_t bytes)
 {
 	uint32_t i;
@@ -137,6 +306,8 @@ void display_event(uint8_t *event_data, size_t bytes)
 		else
 			printf(" 0x%02x", event_data[i]);
 	}
+
+	process_event_record(event_data, bytes);
 }
 
 int get_hab_status(void)
@@ -252,7 +423,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 * do cache flushes. don't think any
 					 * exist, so we ignore them.
 					 */
-					writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+					if (!is_mx6dqp())
+						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
 				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
 					   is_cpu_type(MXC_CPU_MX6SOLO)) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);

arch/arm/cpu/armv7/mx6/soc.c

@@ -62,12 +62,12 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
-	u32 major;
+	u32 major, cfg = 0;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
 		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-		u32 cfg = readl(&scu->config) & 3;
+		cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
 		if (type == MXC_CPU_MX6DL) {
 			if (!cfg)
@@ -81,6 +81,13 @@ u32 get_cpu_rev(void)
 
 	}
 	major = ((reg >> 8) & 0xff);
+	if ((major >= 1) &&
+	    ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
+		major--;
+		type = MXC_CPU_MX6QP;
+		if (cfg == 1)
+			type = MXC_CPU_MX6DP;
+	}
 	reg &= 0xff;		/* mx6 silicon revision */
 	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
@@ -309,11 +316,10 @@ static void imx_set_wdog_powerdown(bool enable)
 {
 	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
-
-#ifdef CONFIG_MX6SX
 	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
-	writew(enable, &wdog3->wmcr);
+
-#endif
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+		writew(enable, &wdog3->wmcr);
 
 	/* Write to the PDE (Power Down Enable) bit */
 	writew(enable, &wdog1->wmcr);
@@ -335,9 +341,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	writel(0, &mxc_ccm->ccdr);
+	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)
@@ -520,7 +529,7 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_cpu_type(MXC_CPU_MX6SX))
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

arch/arm/imx-common/cpu.c

@@ -122,6 +122,10 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX6QP:
+		return "6QP";	/* Quad-Plus version of the mx6 */
+	case MXC_CPU_MX6DP:
+		return "6DP";	/* Dual-Plus version of the mx6 */
 	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
 	case MXC_CPU_MX6D:
@@ -134,6 +138,8 @@ const char *get_imx_type(u32 imxtype)
 		return "6SL";	/* Solo-Lite version of the mx6 */
 	case MXC_CPU_MX6SX:
 		return "6SX";   /* SoloX version of the mx6 */
+	case MXC_CPU_MX6UL:
+		return "6UL";   /* Ultra-Lite version of the mx6 */
 	case MXC_CPU_MX51:
 		return "51";
 	case MXC_CPU_MX53:

arch/arm/imx-common/timer.c

@@ -45,7 +45,8 @@ static inline int gpt_has_clk_source_osc(void)
 #if defined(CONFIG_MX6)
 	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
 	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
+	     is_cpu_type(MXC_CPU_MX6UL))
 		return 1;
 
 	return 0;
@@ -103,10 +104,11 @@ int timer_init(void)
 	if (gpt_has_clk_source_osc()) {
 		i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
-		/* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
+		/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
 		if (is_cpu_type(MXC_CPU_MX6DL) ||
 		    is_cpu_type(MXC_CPU_MX6SOLO) ||
-		    is_cpu_type(MXC_CPU_MX6SX)) {
+		    is_cpu_type(MXC_CPU_MX6SX) ||
+		    is_cpu_type(MXC_CPU_MX6UL)) {
 			i |= GPTCR_24MEN;
 
 			/* Produce 3Mhz clock */

arch/arm/include/asm/arch-imx/cpu.h

@@ -10,8 +10,11 @@
 #define MXC_CPU_MX6DL		0x61
 #define MXC_CPU_MX6SX		0x62
 #define MXC_CPU_MX6Q		0x63
-#define MXC_CPU_MX6D		0x64
+#define MXC_CPU_MX6UL		0x64
 #define MXC_CPU_MX6SOLO		0x65 /* dummy ID */
+#define MXC_CPU_MX6D		0x67
+#define MXC_CPU_MX6DP		0x68
+#define MXC_CPU_MX6QP		0x69
 
 #define CS0_128					0
 #define CS0_64M_CS1_64M				1

arch/arm/include/asm/arch-mx6/clock.h

@@ -57,7 +57,6 @@ void hab_caam_clock_enable(unsigned char enable);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 void enable_uart_clk(unsigned char enable);
-int enable_cspi_clock(unsigned char enable, unsigned spi_num);
 int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
 int enable_sata_clock(void);
 void disable_sata_clock(void);

arch/arm/include/asm/arch-mx6/crm_regs.h

@@ -110,6 +110,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_RBC_EN				(1 << 27)
 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK			(0x3F << 21)
 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET		21
+/* CCR_WB does not exist on i.MX6SX/UL */
 #define MXC_CCM_CCR_WB_COUNT_MASK			0x7
 #define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
 #define MXC_CCM_CCR_COSC_EN				(1 << 12)
@@ -123,6 +124,8 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+/* Exists on i.MX6QP */
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG		(1 << 18)
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY				(1 << 5)
@@ -148,12 +151,11 @@ struct mxc_ccm_reg {
 /* Define the bits in register CBCDR */
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK		(0x7 << 27)
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET		27
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL			(1 << 26)
+#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL			(1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(1 << 25)
-#ifndef CONFIG_MX6SX
+/* MMDC_CH0 not exists on i.MX6SX */
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK		(0x7 << 19)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET		19
-#endif
 #define MXC_CCM_CBCDR_AXI_PODF_MASK			(0x7 << 16)
 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET			16
 #define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
@@ -176,7 +178,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL		(1 << 20)
+#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		18
 #ifndef CONFIG_MX6SX
@@ -195,26 +197,25 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
-#ifndef CONFIG_MX6SX
+/* Exists on i.MX6QP */
-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
+#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
-#endif
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET		29
-#ifdef CONFIG_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK			(0x7 << 26)
 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET		26
-#else
 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK			(0x3 << 27)
 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			27
-#endif
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	23
 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
+/* CSCMR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCMR1_GPMI_CLK_SEL			(1 << 19)
+#define MXC_CCM_CSCMR1_BCH_CLK_SEL			(1 << 18)
 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL			(1 << 19)
 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL			(1 << 18)
 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL			(1 << 17)
@@ -225,14 +226,13 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		10
-#ifdef CONFIG_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
-#endif
+/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
-#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK			(1 << 6)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
-#endif
+
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F
 
 /* Define the bits in register CSCMR2 */
@@ -244,21 +244,24 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
-#ifdef CONFIG_MX6SX
+/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
+
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
-#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		2
-#endif
 
 /* Define the bits in register CSCDR1 */
 #ifndef CONFIG_MX6SX
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		25
 #endif
+/* CSCDR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCDR1_GPMI_PODF_MASK			(0x7 << 22)
+#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET			22
+#define MXC_CCM_CSCDR1_BCH_PODF_MASK			(0x7 << 19)
+#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET			19
+
 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK			(0x7 << 22)
 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET		22
 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK			(0x7 << 19)
@@ -273,16 +276,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
 #endif
-#ifdef CONFIG_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
-#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
-#else
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
-#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
-#endif
-#endif
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
+#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
 
 /* Define the bits in register CS1CDR */
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
@@ -299,7 +296,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		0
 
 /* Define the bits in register CS2CDR */
-#ifdef CONFIG_MX6SX
+/* QSPI2 on i.MX6SX */
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << 21)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                       (((v) & 0x3f) << 21)
@@ -309,17 +306,34 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK              (0x7 << 15)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET            15
 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << 15)
-#else
+
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		21
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)			(((v) & 0x3f) << 21)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
+
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP		(0x7 << 15)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP		15
-#endif
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v)		(((v) & 0x7) << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ		(0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ		16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)		(((v) & 0x3) << 16)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		\
+	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :		\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		\
+	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			\
+	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :		\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
+
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
@@ -384,6 +398,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
+/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
+
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
@@ -544,10 +561,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_ECSPI4S_MASK			(3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET			8
 #define MXC_CCM_CCGR1_ECSPI5S_MASK			(3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
-#ifndef CONFIG_MX6SX
+/* CCGR1_ENET does not exist on i.MX6SX/UL */
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET		10
+#define MXC_CCM_CCGR1_ENET_OFFSET			10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_ENET_MASK				(3 << MXC_CCM_CCGR1_ENET_OFFSET)
-#endif
 #define MXC_CCM_CCGR1_EPIT1S_OFFSET			12
 #define MXC_CCM_CCGR1_EPIT1S_MASK			(3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
 #define MXC_CCM_CCGR1_EPIT2S_OFFSET			14
@@ -618,21 +634,21 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 #endif
 
-#ifdef CONFIG_MX6SX
+/* Exist on i.MX6SX */
 #define MXC_CCM_CCGR3_M4_OFFSET					2
 #define MXC_CCM_CCGR3_M4_MASK					(3 << MXC_CCM_CCGR3_M4_OFFSET)
 #define MXC_CCM_CCGR3_ENET_OFFSET				4
 #define MXC_CCM_CCGR3_ENET_MASK					(3 << MXC_CCM_CCGR3_ENET_OFFSET)
 #define MXC_CCM_CCGR3_QSPI_OFFSET				14
 #define MXC_CCM_CCGR3_QSPI_MASK					(3 << MXC_CCM_CCGR3_QSPI_OFFSET)
-#else
+
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
 #define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET			2
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET			4
 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
-#endif
+
 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET				6
 #define MXC_CCM_CCGR3_IPU2_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET			8
@@ -641,15 +657,22 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET				12
 #define MXC_CCM_CCGR3_LDB_DI0_MASK				(3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
-#ifdef CONFIG_MX6SX
+
+/* QSPI1 exists on i.MX6SX/UL */
 #define MXC_CCM_CCGR3_QSPI1_OFFSET				14
 #define MXC_CCM_CCGR3_QSPI1_MASK				(3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
-#else
+
 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET				14
 #define MXC_CCM_CCGR3_LDB_DI1_MASK				(3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET			16
 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK			(3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
-#endif
+
+/* A7_CLKDIV/WDOG1 on i.MX6UL */
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET			16
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET			18
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK			(3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
+
 #define MXC_CCM_CCGR3_MLB_OFFSET				18
 #define MXC_CCM_CCGR3_MLB_MASK					(3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET	20
@@ -662,8 +685,16 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+/* AXI on i.MX6UL */
+#define MXC_CCM_CCGR3_AXI_CLK_OFFSET				28
+#define MXC_CCM_CCGR3_AXI_CLK_MASK				(3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET				28
 #define MXC_CCM_CCGR3_OCRAM_MASK				(3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+
+/* GPIO4 on i.MX6UL */
+#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET				30
+#define MXC_CCM_CCGR3_GPIO4_CLK_MASK				(3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
+
 #ifndef CONFIG_MX6SX
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET			30
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
@@ -671,13 +702,11 @@ struct mxc_ccm_reg {
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET				0
 #define MXC_CCM_CCGR4_PCIE_MASK					(3 << MXC_CCM_CCGR4_PCIE_OFFSET)
-#ifdef CONFIG_MX6SX
+/* QSPI2 on i.MX6SX */
 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET				10
 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK				(3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
-#else
 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET		8
 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
-#endif
 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET			12
 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET	14
@@ -728,19 +757,28 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_SAI2_MASK				(3 << MXC_CCM_CCGR5_SAI2_OFFSET)
 #endif
 
+/* PRG_CLK0 exists on i.MX6QP */
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK		(3 << 24)
+
 #define MXC_CCM_CCGR6_USBOH3_OFFSET		0
 #define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC1_OFFSET		2
 #define MXC_CCM_CCGR6_USDHC1_MASK		(3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 #define MXC_CCM_CCGR6_USDHC2_OFFSET		4
 #define MXC_CCM_CCGR6_USDHC2_MASK		(3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+/* GPMI/BCH on i.MX6UL */
+#define MXC_CCM_CCGR6_BCH_OFFSET		6
+#define MXC_CCM_CCGR6_BCH_MASK			(3 << MXC_CCM_CCGR6_BCH_OFFSET)
+#define MXC_CCM_CCGR6_GPMI_OFFSET		8
+#define MXC_CCM_CCGR6_GPMI_MASK		(3 << MXC_CCM_CCGR6_GPMI_OFFSET)
+
 #define MXC_CCM_CCGR6_USDHC3_OFFSET		6
 #define MXC_CCM_CCGR6_USDHC3_MASK		(3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC4_OFFSET		8
 #define MXC_CCM_CCGR6_USDHC4_MASK		(3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET		10
 #define MXC_CCM_CCGR6_EMI_SLOW_MASK		(3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
-#ifdef CONFIG_MX6SX
+/* The following *CCGR6* exist only i.MX6SX */
 #define MXC_CCM_CCGR6_PWM8_OFFSET		16
 #define MXC_CCM_CCGR6_PWM8_MASK			(3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 #define MXC_CCM_CCGR6_VADC_OFFSET		20
@@ -755,10 +793,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_PWM6_MASK			(3 << MXC_CCM_CCGR6_PWM6_OFFSET)
 #define MXC_CCM_CCGR6_PWM7_OFFSET		30
 #define MXC_CCM_CCGR6_PWM7_MASK			(3 << MXC_CCM_CCGR6_PWM7_OFFSET)
-#else
+/* The two does not exist on i.MX6SX */
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
 #define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-#endif
 
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
 #define BP_ANADIG_PLL_SYS_RSVD0      20

arch/arm/include/asm/arch-mx6/hab.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  *
@@ -23,24 +23,68 @@ enum hab_status {
 
 /* Security Configuration definitions */
 enum hab_config {
-	HAB_CFG_RETURN = 0x33, /**< Field Return IC */
+	HAB_CFG_RETURN = 0x33,	/* < Field Return IC */
-	HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
+	HAB_CFG_OPEN = 0xf0,	/* < Non-secure IC */
-	HAB_CFG_CLOSED = 0xcc /**< Secure IC */
+	HAB_CFG_CLOSED = 0xcc	/* < Secure IC */
 };
 
 /* State definitions */
 enum hab_state {
-	HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
+	HAB_STATE_INITIAL = 0x33,	/* Initialising state (transitory) */
-	HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
+	HAB_STATE_CHECK = 0x55,		/* Check state (non-secure) */
-	HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
+	HAB_STATE_NONSECURE = 0x66,	/* Non-secure state */
-	HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
+	HAB_STATE_TRUSTED = 0x99,	/* Trusted state */
-	HAB_STATE_SECURE = 0xaa, /**< Secure state */
+	HAB_STATE_SECURE = 0xaa,	/* Secure state */
-	HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
+	HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
-	HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
+	HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
-	HAB_STATE_NONE = 0xf0, /**< No security state machine */
+	HAB_STATE_NONE = 0xf0,		/* No security state machine */
 	HAB_STATE_MAX
 };
 
+enum hab_reason {
+	HAB_RSN_ANY = 0x00,			/* Match any reason */
+	HAB_ENG_FAIL = 0x30,		/* Engine failure */
+	HAB_INV_ADDRESS = 0x22,		/* Invalid address: access denied */
+	HAB_INV_ASSERTION = 0x0c,   /* Invalid assertion */
+	HAB_INV_CALL = 0x28,		/* Function called out of sequence */
+	HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
+	HAB_INV_COMMAND = 0x06,     /* Invalid command: command malformed */
+	HAB_INV_CSF = 0x11,			/* Invalid csf */
+	HAB_INV_DCD = 0x27,			/* Invalid dcd */
+	HAB_INV_INDEX = 0x0f,		/* Invalid index: access denied */
+	HAB_INV_IVT = 0x05,			/* Invalid ivt */
+	HAB_INV_KEY = 0x1d,			/* Invalid key */
+	HAB_INV_RETURN = 0x1e,		/* Failed callback function */
+	HAB_INV_SIGNATURE = 0x18,   /* Invalid signature */
+	HAB_INV_SIZE = 0x17,		/* Invalid data size */
+	HAB_MEM_FAIL = 0x2e,		/* Memory failure */
+	HAB_OVR_COUNT = 0x2b,		/* Expired poll count */
+	HAB_OVR_STORAGE = 0x2d,		/* Exhausted storage region */
+	HAB_UNS_ALGORITHM = 0x12,   /* Unsupported algorithm */
+	HAB_UNS_COMMAND = 0x03,		/* Unsupported command */
+	HAB_UNS_ENGINE = 0x0a,		/* Unsupported engine */
+	HAB_UNS_ITEM = 0x24,		/* Unsupported configuration item */
+	HAB_UNS_KEY = 0x1b,	        /* Unsupported key type/parameters */
+	HAB_UNS_PROTOCOL = 0x14,	/* Unsupported protocol */
+	HAB_UNS_STATE = 0x09,		/* Unsuitable state */
+	HAB_RSN_MAX
+};
+
+enum hab_context {
+	HAB_CTX_ANY = 0x00,			/* Match any context */
+	HAB_CTX_FAB = 0xff,		    /* Event logged in hab_fab_test() */
+	HAB_CTX_ENTRY = 0xe1,		/* Event logged in hab_rvt.entry() */
+	HAB_CTX_TARGET = 0x33,	    /* Event logged in hab_rvt.check_target() */
+	HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
+	HAB_CTX_DCD = 0xdd,         /* Event logged in hab_rvt.run_dcd() */
+	HAB_CTX_CSF = 0xcf,         /* Event logged in hab_rvt.run_csf() */
+	HAB_CTX_COMMAND = 0xc0,     /* Event logged executing csf/dcd command */
+	HAB_CTX_AUT_DAT = 0xdb,		/* Authenticated data block */
+	HAB_CTX_ASSERT = 0xa0,		/* Event logged in hab_rvt.assert() */
+	HAB_CTX_EXIT = 0xee,		/* Event logged in hab_rvt.exit() */
+	HAB_CTX_MAX
+};
+
 /*Function prototype description*/
 typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
 		uint8_t* , size_t*);
@@ -53,6 +97,22 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
 		void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
+#define HAB_ENG_ANY		0x00   /* Select first compatible engine */
+#define HAB_ENG_SCC		0x03   /* Security controller */
+#define HAB_ENG_RTIC	0x05   /* Run-time integrity checker */
+#define HAB_ENG_SAHARA  0x06   /* Crypto accelerator */
+#define HAB_ENG_CSU		0x0a   /* Central Security Unit */
+#define HAB_ENG_SRTC	0x0c   /* Secure clock */
+#define HAB_ENG_DCP		0x1b   /* Data Co-Processor */
+#define HAB_ENG_CAAM	0x1d   /* CAAM */
+#define HAB_ENG_SNVS	0x1e   /* Secure Non-Volatile Storage */
+#define HAB_ENG_OCOTP	0x21   /* Fuse controller */
+#define HAB_ENG_DTCP	0x22   /* DTCP co-processor */
+#define HAB_ENG_ROM		0x36   /* Protected ROM area */
+#define HAB_ENG_HDCP	0x24   /* HDCP co-processor */
+#define HAB_ENG_RTL		0x77   /* RTL simulation engine */
+#define HAB_ENG_SW		0xff   /* Software engine */
+
 #ifdef CONFIG_MX6SX
 #define HAB_RVT_BASE			0x00000100
 #else
@@ -73,6 +133,7 @@ typedef void hapi_clock_init_t(void);
 
 #define HAB_CID_ROM 0 /**< ROM Caller ID */
 #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+
 /* ----------- end of HAB API updates ------------*/
 
 #endif

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -9,7 +9,11 @@
 
 #define ARCH_MXC
 
+#ifdef CONFIG_MX6UL
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#else
 #define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
 
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
@@ -19,7 +23,7 @@
 #define GPU_2D_ARB_END_ADDR             0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
-#elif CONFIG_MX6SX
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00107FFF
 #define GPU_ARB_BASE_ADDR               0x01800000
@@ -28,10 +32,6 @@
 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR			0x007F8000
 
-#define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
-#define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
-#define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
-
 #else
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00103FFF
@@ -52,13 +52,13 @@
 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define GPV2_BASE_ADDR                  0x00D00000
 #else
 #define GPV2_BASE_ADDR			0x00200000
 #endif
 
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define GPV3_BASE_ADDR			0x00E00000
 #define GPV4_BASE_ADDR			0x00F00000
 #define GPV5_BASE_ADDR			0x01000000
@@ -87,15 +87,21 @@
 #define AIPS1_ARB_END_ADDR              0x020FFFFF
 #define AIPS2_ARB_BASE_ADDR             0x02100000
 #define AIPS2_ARB_END_ADDR              0x021FFFFF
-#ifdef CONFIG_MX6SX
+/* AIPS3 only on i.MX6SX */
 #define AIPS3_ARB_BASE_ADDR             0x02200000
 #define AIPS3_ARB_END_ADDR              0x022FFFFF
+#ifdef CONFIG_MX6SX
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                0x60000000
 #define QSPI0_AMBA_END                 0x6FFFFFFF
 #define QSPI1_AMBA_BASE                0x70000000
 #define QSPI1_AMBA_END                 0x7FFFFFFF
+#elif defined(CONFIG_MX6UL)
+#define WEIM_ARB_BASE_ADDR              0x50000000
+#define WEIM_ARB_END_ADDR               0x57FFFFFF
+#define QSPI0_AMBA_BASE                 0x60000000
+#define QSPI0_AMBA_END                  0x6FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
@@ -111,7 +117,7 @@
 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
 #endif
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define MMDC0_ARB_BASE_ADDR             0x80000000
 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0xC0000000
@@ -238,13 +244,16 @@
 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
-#ifdef CONFIG_MX6SL
+/* i.MX6SL */
 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
-#elif CONFIG_MX6SX
+#ifdef CONFIG_MX6UL
-#define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
-#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
+/* i.MX6SX */
+#define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
 #endif
+/* i.MX6DQ/SDL */
+#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
 
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
@@ -257,22 +266,21 @@
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_MX6UL
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
-#else
-#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
-#endif
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-#ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
+#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
 #endif
+#define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
@@ -296,7 +304,6 @@
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
-#define WDOG3_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x88000)
 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
@@ -308,12 +315,17 @@
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
 #endif
+#define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?	\
+			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
 
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
 #define CHIP_REV_2_0                 0x20
-#ifndef CONFIG_MX6SX
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define IRAM_SIZE                    0x00040000
 #else
 #define IRAM_SIZE                    0x00020000
@@ -451,7 +463,7 @@ struct src {
 
 
 struct iomuxc {
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 	u8 reserved[0x4000];
 #endif
 	u32 gpr[14];
@@ -577,7 +589,7 @@ struct cspi_regs {
 #define MXC_CSPICON_POL		4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
@@ -661,7 +673,7 @@ struct fuse_bank1_regs {
 	u32	rsvd7[3];
 };
 
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 struct fuse_bank4_regs {
 	u32 sjc_resp_low;
 	u32 rsvd0[3];
@@ -674,7 +686,9 @@ struct fuse_bank4_regs {
 	u32 mac_addr2;
 	u32 rsvd4[7];
 	u32 gp1;
-	u32 rsvd5[7];
+	u32 rsvd5[3];
+	u32 gp2;
+	u32 rsvd6[3];
 };
 #else
 struct fuse_bank4_regs {

arch/arm/include/asm/arch-mx6/mx6-ddr.h

@@ -16,7 +16,11 @@
 #ifdef CONFIG_MX6SX
 #include "mx6sx-ddr.h"
 #else
+#ifdef CONFIG_MX6UL
+#include "mx6ul-ddr.h"
+#else
 #error "Please select cpu"
+#endif	/* CONFIG_MX6UL */
 #endif	/* CONFIG_MX6SX */
 #endif	/* CONFIG_MX6DL or CONFIG_MX6S */
 #endif	/* CONFIG_MX6Q */
@@ -62,6 +66,44 @@ struct mmdc_p_regs {
 	u32 mpmur0;
 };
 
+#define MX6UL_IOM_DDR_BASE	0x020e0200
+struct mx6ul_iomux_ddr_regs {
+	u32 res1[17];
+	u32 dram_dqm0;
+	u32 dram_dqm1;
+	u32 dram_ras;
+	u32 dram_cas;
+	u32 dram_cs0;
+	u32 dram_cs1;
+	u32 dram_sdwe_b;
+	u32 dram_odt0;
+	u32 dram_odt1;
+	u32 dram_sdba0;
+	u32 dram_sdba1;
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdcke1;
+	u32 dram_sdclk_0;
+	u32 dram_sdqs0;
+	u32 dram_sdqs1;
+	u32 dram_reset;
+};
+
+#define MX6UL_IOM_GRP_BASE	0x020e0400
+struct mx6ul_iomux_grp_regs {
+	u32 res1[36];
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 grp_b0ds;
+	u32 grp_ddrpk;
+	u32 grp_ctlds;
+	u32 grp_b1ds;
+	u32 grp_ddrhys;
+	u32 grp_ddrpke;
+	u32 grp_ddrmode;
+	u32 grp_ddr_type;
+};
+
 #define MX6SX_IOM_DDR_BASE	0x020e0200
 struct mx6sx_iomux_ddr_regs {
 	u32 res1[59];
@@ -290,6 +332,9 @@ void mx6sdl_dram_iocfg(unsigned width,
 void mx6sx_dram_iocfg(unsigned width,
 		      const struct mx6sx_iomux_ddr_regs *,
 		      const struct mx6sx_iomux_grp_regs *);
+void mx6ul_dram_iocfg(unsigned width,
+		      const struct mx6ul_iomux_ddr_regs *,
+		      const struct mx6ul_iomux_grp_regs *);
 
 /* configure mx6 mmdc registers */
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,

arch/arm/include/asm/arch-mx6/mx6-pins.h

@@ -37,6 +37,8 @@ enum {
 #include "mx6sl_pins.h"
 #elif defined(CONFIG_MX6SX)
 #include "mx6sx_pins.h"
+#elif defined(CONFIG_MX6UL)
+#include "mx6ul_pins.h"
 #else
 #error "Please select cpu"
 #endif	/* CONFIG_MX6Q */

arch/arm/include/asm/arch-mx6/mx6ul-ddr.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6UL_DDR_H__
+#define __ASM_ARCH_MX6UL_DDR_H__
+
+#ifndef CONFIG_MX6UL
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e0244
+#define MX6_IOM_DRAM_DQM1	0x020e0248
+
+#define MX6_IOM_DRAM_RAS	0x020e024c
+#define MX6_IOM_DRAM_CAS	0x020e0250
+#define MX6_IOM_DRAM_CS0	0x020e0254
+#define MX6_IOM_DRAM_CS1	0x020e0258
+#define MX6_IOM_DRAM_SDWE_B	0x020e025c
+#define MX6_IOM_DRAM_SDODT0	0x020e0260
+#define MX6_IOM_DRAM_SDODT1	0x020e0264
+#define MX6_IOM_DRAM_SDBA0	0x020e0268
+#define MX6_IOM_DRAM_SDBA1	0x020e026c
+#define MX6_IOM_DRAM_SDBA2	0x020e0270
+#define MX6_IOM_DRAM_SDCKE0	0x020e0274
+#define MX6_IOM_DRAM_SDCKE1	0x020e0278
+#define MX6_IOM_DRAM_SDCLK_0	0x020e027c
+#define MX6_IOM_DRAM_SDQS0	0x020e0280
+#define MX6_IOM_DRAM_SDQS1	0x020e0284
+#define MX6_IOM_DRAM_RESET	0x020e0288
+
+#define MX6_IOM_GRP_ADDDS	0x020e0490
+#define MX6_IOM_DDRMODE_CTL	0x020e0494
+#define MX6_IOM_GRP_B0DS	0x020e0498
+#define MX6_IOM_GRP_DDRPK	0x020e049c
+#define MX6_IOM_GRP_CTLDS	0x020e04a0
+#define MX6_IOM_GRP_B1DS	0x020e04a4
+#define MX6_IOM_GRP_DDRHYS	0x020e04a8
+#define MX6_IOM_GRP_DDRPKE	0x020e04ac
+#define MX6_IOM_GRP_DDRMODE	0x020e04b0
+#define MX6_IOM_GRP_DDR_TYPE	0x020e04b4
+
+#endif	/*__ASM_ARCH_MX6SX_DDR_H__ */

arch/arm/include/asm/arch-mx6/sys_proto.h

@@ -30,9 +30,7 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
-#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
-		     is_cpu_type(MXC_CPU_MX6D)) && \
-		     (soc_rev() >= CHIP_REV_2_0))
 
 /*
  * Initializes on-chip ethernet controllers.

arch/arm/include/asm/arch-vf610/crm_regs.h

@@ -207,6 +207,7 @@ struct anadig_reg {
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
 #define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
+#define CCM_CCGR4_I2C1_CTRL_MASK		(0x3 << 14)
 #define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
 #define CCM_CCGR6_DSPI2_CTRL_MASK		(0x3 << 24)
 #define CCM_CCGR6_DSPI3_CTRL_MASK		(0x3 << 26)
@@ -216,6 +217,8 @@ struct anadig_reg {
 #define CCM_CCGR9_FEC0_CTRL_MASK		0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
 #define CCM_CCGR10_NFC_CTRL_MASK		0x3
+#define CCM_CCGR10_I2C2_CTRL_MASK		(0x3 << 12)
+#define CCM_CCGR10_I2C3_CTRL_MASK		(0x3 << 14)
 
 #define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
 #define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -75,6 +75,9 @@
 #define ESAI_FIFO_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00063000)
 #define WDOG_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00065000)
 #define I2C1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00066000)
+#define I2C2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00067000)
+#define I2C3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000E6000)
+#define I2C4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000E7000)
 #define WKUP_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006A000)
 #define CCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006B000)
 #define GPC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006C000)

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -20,7 +20,8 @@
 #define VF610_DDR_PAD_CTRL_1	(PAD_CTL_DSE_25ohm | \
 				PAD_CTL_INPUT_DIFFERENTIAL)
 #define VF610_I2C_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
-				PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
+				PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \
+				PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_NFC_IO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
 				PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \
 				PAD_CTL_OBE_IBE_ENABLE)
@@ -110,6 +111,8 @@ enum {
 	VF610_PAD_PTA29__ESDHC1_DAT3		= IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTB14__I2C0_SCL		= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
 	VF610_PAD_PTB15__I2C0_SDA		= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTA22__I2C2_SCL		= IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTA23__I2C2_SDA		= IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL),
 	VF610_PAD_PTD31__NF_IO15		= IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD31__GPIO_63		= IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD30__NF_IO14		= IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
@@ -146,10 +149,10 @@ enum {
 	VF610_PAD_PTD12__GPIO_91		= IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD13__GPIO_92		= IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD22__NF_IO6			= IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD21__NF_IO5			= IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
+	VF610_PAD_PTD21__NF_IO5			= IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD20__NF_IO4			= IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
+	VF610_PAD_PTD20__NF_IO4			= IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD19__NF_IO3			= IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD18__NF_IO2			= IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
+	VF610_PAD_PTD18__NF_IO2			= IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD17__NF_IO1			= IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD16__NF_IO0			= IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTB24__NF_WE_B		= IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),

arch/arm/include/asm/imx-common/iomux-v3.h

@@ -98,7 +98,11 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_ODE		(1 << 11)
 
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#define PAD_CTL_SPEED_LOW	(0 << 6)
+#else
 #define PAD_CTL_SPEED_LOW	(1 << 6)
+#endif
 #define PAD_CTL_SPEED_MED	(2 << 6)
 #define PAD_CTL_SPEED_HIGH	(3 << 6)
 
@@ -127,6 +131,8 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_SRE		(1 << 11)
 
+#define PAD_CTL_ODE		(1 << 10)
+
 #define PAD_CTL_DSE_150ohm	(1 << 6)
 #define PAD_CTL_DSE_50ohm	(3 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)

board/compulab/cm_fx6/cm_fx6.c

@@ -13,6 +13,7 @@
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <errno.h>
 #include <fdt_support.h>
 #include <sata.h>
 #include <splash.h>
@@ -51,45 +52,70 @@ int splash_screen_prepare(void)
 #ifdef CONFIG_IMX_HDMI
 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
 {
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	imx_setup_hdmi();
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
 	imx_enable_hdmi_phy();
 }
 
-struct display_info_t const displays[] = {
+static struct display_info_t preset_hdmi_1024X768 = {
-	{
+	.bus	= -1,
-		.bus	= -1,
+	.addr	= 0,
-		.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
-		.pixfmt	= IPU_PIX_FMT_RGB24,
+	.enable	= cm_fx6_enable_hdmi,
-		.detect	= detect_hdmi,
+	.mode	= {
-		.enable	= cm_fx6_enable_hdmi,
+		.name           = "HDMI",
-		.mode	= {
+		.refresh        = 60,
-			.name           = "HDMI",
+		.xres           = 1024,
-			.refresh        = 60,
+		.yres           = 768,
-			.xres           = 1024,
+		.pixclock       = 40385,
-			.yres           = 768,
+		.left_margin    = 220,
-			.pixclock       = 40385,
+		.right_margin   = 40,
-			.left_margin    = 220,
+		.upper_margin   = 21,
-			.right_margin   = 40,
+		.lower_margin   = 7,
-			.upper_margin   = 21,
+		.hsync_len      = 60,
-			.lower_margin   = 7,
+		.vsync_len      = 10,
-			.hsync_len      = 60,
+		.sync           = FB_SYNC_EXT,
-			.vsync_len      = 10,
+		.vmode          = FB_VMODE_NONINTERLACED,
-			.sync           = FB_SYNC_EXT,
+	}
-			.vmode          = FB_VMODE_NONINTERLACED,
-		}
-	},
 };
-size_t display_count = ARRAY_SIZE(displays);
 
 static void cm_fx6_setup_display(void)
 {
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int reg;
 
 	enable_ipu_clock();
-	imx_setup_hdmi();
+	clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
-	reg = __raw_readl(&mxc_ccm->CCGR3);
+}
-	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
+
-	writel(reg, &mxc_ccm->CCGR3);
+int board_video_skip(void)
+{
+	int ret;
+	struct display_info_t *preset;
+	char const *panel = getenv("displaytype");
+
+	if (!panel) /* Also accept panel for backward compatibility */
+		panel = getenv("panel");
+
+	if (!panel)
+		return -ENOENT;
+
+	if (!strcmp(panel, "HDMI"))
+		preset = &preset_hdmi_1024X768;
+	else
+		return -EINVAL;
+
+	ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
+	if (ret) {
+		printf("Can't init display %s: %d\n", preset->mode.name, ret);
+		return ret;
+	}
+
+	preset->enable(preset);
+	printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
+	       preset->mode.yres);
+
+	return 0;
 }
 #else
 static inline void cm_fx6_setup_display(void) {}

board/compulab/cm_fx6/spl.c

@@ -303,7 +303,7 @@ static void cm_fx6_setup_uart(void)
 static void cm_fx6_setup_ecspi(void)
 {
 	cm_fx6_set_ecspi_iomux();
-	enable_cspi_clock(1, 0);
+	enable_spi_clk(1, 0);
 }
 #else
 static void cm_fx6_setup_ecspi(void) { }

board/congatec/cgtqmx6eval/cgtqmx6eval.c

@@ -15,9 +15,18 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
 #include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +36,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define MX6Q_QMX6_PFUZE_MUX		IMX_GPIO_NR(6, 9)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -34,12 +50,12 @@ int dram_init(void)
 	return 0;
 }
 
-iomux_v3_cfg_t const uart2_pads[] = {
+static iomux_v3_cfg_t const uart2_pads[] = {
 	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const usdhc2_pads[] = {
+static iomux_v3_cfg_t const usdhc2_pads[] = {
 	MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -49,7 +65,21 @@ iomux_v3_cfg_t const usdhc2_pads[] = {
 	MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const usdhc4_pads[] = {
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -63,14 +93,92 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+#define I2C_PMIC	1	/* I2C2 port is used to connect to the PMIC */
+
+struct interface_level {
+	char *name;
+	uchar value;
+};
+
+static struct interface_level mipi_levels[] = {
+	{"0V0", 0x00},
+	{"2V5", 0x17},
+};
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	u32 id1, id2, i;
+	int ret;
+	char const *lv_mipi;
+
+	/* configure I2C multiplexer */
+	gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
+
+	power_pfuze100_init(I2C_PMIC);
+	p = pmic_get("PFUZE100");
+	if (!p)
+		return -EINVAL;
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
+	pmic_reg_read(p, PFUZE100_REVID, &id2);
+	printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
+
+	if (id2 >= 0x20)
+		return 0;
+
+	/* set level of MIPI if specified */
+	lv_mipi = getenv("lv_mipi");
+	if (lv_mipi)
+		return 0;
+
+	for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
+		if (!strcmp(mipi_levels[i].name, lv_mipi)) {
+			printf("set MIPI level %s\n",
+			       mipi_levels[i].name);
+			ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
+					     mipi_levels[i].value);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+ 
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[] = {
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
 	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
 };
 
@@ -84,6 +192,9 @@ int board_mmc_getcd(struct mmc *mmc)
 		gpio_direction_input(IMX_GPIO_NR(1, 4));
 		ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 		break;
+	case USDHC3_BASE_ADDR:
+		ret = 1;	/* eMMC is always present */
+		break;
 	case USDHC4_BASE_ADDR:
 		gpio_direction_input(IMX_GPIO_NR(2, 6));
 		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
@@ -98,25 +209,237 @@ int board_mmc_getcd(struct mmc *mmc)
 int board_mmc_init(bd_t *bis)
 {
 	s32 status = 0;
+	int i;
 
 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 
-	imx_iomux_v3_setup_multiple_pads(
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-	imx_iomux_v3_setup_multiple_pads(
+	imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 
-	status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+	for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
-		     fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+		status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (status)
+			return status;
+	}
 
-	return status;
+	return 0;
 }
 #endif
 
+int board_ehci_hcd_init(int port)
+{
+	switch (port) {
+	case 0:
+		imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+						 ARRAY_SIZE(usb_otg_pads));
+		/*
+		 * set daisy chain for otg_pin_id on 6q.
+		 * for 6dl, this bit is reserved
+		 */
+		imx_iomux_set_gpr_register(1, 13, 1, 1);
+		break;
+	case 1:
+		/* nothing to do */
+		break;
+	default:
+		printf("Invalid USB port: %d\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		gpio_direction_output(IMX_GPIO_NR(5, 5), on);
+		break;
+	default:
+		printf("Invalid USB port: %d\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct display_info_t {
+	int bus;
+	int addr;
+	int pixfmt;
+	int (*detect)(struct display_info_t const *dev);
+	void (*enable)(struct display_info_t const *dev);
+	struct fb_videomode mode;
+};
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	disable_lvds(dev);
+	imx_enable_hdmi_phy();
+}
+
+static struct display_info_t const displays[] = {
+{
+	.bus = -1,
+	.addr = 0,
+	.pixfmt = IPU_PIX_FMT_RGB666,
+	.detect = NULL,
+	.enable = NULL,
+	.mode = {
+		.name =
+		"Hannstar-XGA",
+		.refresh = 60,
+		.xres = 1024,
+		.yres = 768,
+		.pixclock = 15385,
+		.left_margin = 220,
+		.right_margin = 40,
+		.upper_margin = 21,
+		.lower_margin = 7,
+		.hsync_len = 60,
+		.vsync_len = 10,
+		.sync = FB_SYNC_EXT,
+		.vmode = FB_VMODE_NONINTERLACED } },
+{
+	.bus = -1,
+	.addr = 0,
+	.pixfmt = IPU_PIX_FMT_RGB24,
+	.detect = NULL,
+	.enable = do_enable_hdmi,
+	.mode = {
+		.name = "HDMI",
+		.refresh = 60,
+		.xres = 1024,
+		.yres = 768,
+		.pixclock = 15385,
+		.left_margin = 220,
+		.right_margin = 40,
+		.upper_margin = 21,
+		.lower_margin = 7,
+		.hsync_len = 60,
+		.vsync_len = 10,
+		.sync = FB_SYNC_EXT,
+		.vmode = FB_VMODE_NONINTERLACED } }
+};
+
+int board_video_skip(void)
+{
+	int i;
+	int ret;
+	char const *panel = getenv("panel");
+	if (!panel) {
+		for (i = 0; i < ARRAY_SIZE(displays); i++) {
+			struct display_info_t const *dev = displays + i;
+			if (dev->detect && dev->detect(dev)) {
+				panel = dev->mode.name;
+				printf("auto-detected panel %s\n", panel);
+				break;
+			}
+		}
+		if (!panel) {
+			panel = displays[0].mode.name;
+			printf("No panel detected: default to %s\n", panel);
+			i = 0;
+		}
+	} else {
+		for (i = 0; i < ARRAY_SIZE(displays); i++) {
+			if (!strcmp(panel, displays[i].mode.name))
+				break;
+		}
+	}
+	if (i < ARRAY_SIZE(displays)) {
+		ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
+		if (!ret) {
+			if (displays[i].enable)
+				displays[i].enable(displays + i);
+			printf("Display: %s (%ux%u)\n",
+			       displays[i].mode.name, displays[i].mode.xres,
+			       displays[i].mode.yres);
+		} else
+			printf("LCD %s cannot be configured: %d\n",
+			       displays[i].mode.name, ret);
+	} else {
+		printf("unsupported panel %s\n", panel);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
+		     MXC_CCM_CCGR3_LDB_DI1_MASK);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+		(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
+		     MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
+
+	setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
+		     MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
+		     CHSCCDR_CLK_SEL_LDB_DI0 <<
+		     MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+		| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+		| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+		| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+		| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+		| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+		| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+		| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
+		| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+		       IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
+		(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+	setup_display();
 
 	return 0;
 }
@@ -126,6 +449,12 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
 	return 0;
 }
 

board/congatec/cgtqmx6eval/imximage.cfg

@@ -30,117 +30,91 @@ BOOT_FROM      sd
  *      Address   absolute address of the register
  *      value     value to be stored in the register
  */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x000c0030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
 DATA 4 0x020e05a8 0x00000030
 DATA 4 0x020e05b0 0x00000030
 DATA 4 0x020e0524 0x00000030
 DATA 4 0x020e051c 0x00000030
-
 DATA 4 0x020e0518 0x00000030
 DATA 4 0x020e050c 0x00000030
 DATA 4 0x020e05b8 0x00000030
 DATA 4 0x020e05c0 0x00000030
-
+DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
 DATA 4 0x020e0784 0x00000030
 DATA 4 0x020e0788 0x00000030
-
 DATA 4 0x020e0794 0x00000030
 DATA 4 0x020e079c 0x00000030
 DATA 4 0x020e07a0 0x00000030
 DATA 4 0x020e07a4 0x00000030
-
 DATA 4 0x020e07a8 0x00000030
 DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e05ac 0x00000030
-DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05b4 0x00000030
-
+DATA 4 0x020e0528 0x00000030
-DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0520 0x00000030
-DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0514 0x00000030
-DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0510 0x00000030
-DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e05bc 0x00000030
-
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+DATA 4 0x021b080c 0x00110019
+DATA 4 0x021b0810 0x00260019
+DATA 4 0x021b480c 0x001A0031
+DATA 4 0x021b4810 0x001A0021
+DATA 4 0x021b083c 0x43100316
+DATA 4 0x021b0840 0x0306027E
+DATA 4 0x021b483c 0x43250330
+DATA 4 0x021b4840 0x0322027B
+DATA 4 0x021b0848 0x47414146
+DATA 4 0x021b4848 0x41434048
+DATA 4 0x021b0850 0x41444A44
+DATA 4 0x021b4850 0x4B444C46
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
 DATA 4 0x021b0824 0x33333333
 DATA 4 0x021b0828 0x33333333
-
 DATA 4 0x021b481c 0x33333333
 DATA 4 0x021b4820 0x33333333
 DATA 4 0x021b4824 0x33333333
 DATA 4 0x021b4828 0x33333333
-
+DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b0018 0x00081740
+DATA 4 0x021b48b8 0x00000800
-
+DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b000c 0x555A79A4
 DATA 4 0x021b0010 0xDB538F64
 DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
+DATA 4 0x021b0018 0x00081740
-
+DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0030 0x005A0E21
-DATA 4 0x021b0004 0x00025576
 DATA 4 0x021b0040 0x00000027
 DATA 4 0x021b0000 0x831A0000
-
+DATA 4 0x021b001c 0x04888032
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
 DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x09308030
-DATA 4 0x021b001c 0x19308030
-DATA 4 0x021b001c 0x19308038
-
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
 DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00022227
+DATA 4 0x021b4818 0x00011117
-
+DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
 DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
 
 /* set the default clock gate to save power */
 DATA 4 0x020c4068 0x00C03F3F

board/freescale/mx6qsabreauto/mx6qp.cfg

@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08c0 0x24912492
+DATA 4 0x021b48c0 0x24912492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x14420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x00bb0008 0x00000004
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717

board/freescale/mx6qsabreauto/mx6qsabreauto.c

@@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
+static void setup_fec(void)
 {
+	if (is_mx6dqp()) {
+		/*
+		 * select ENET MAC0 TX clock from PLL
+		 */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+		enable_fec_anatop_clock(ENET_125MHZ);
+	}
+
 	setup_iomux_enet();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_fec();
 
 	return cpu_eth_init(bis);
 }
@@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int ret;
+	unsigned int value;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
-	ret = pfuze_mode_init(p, APS_PFM);
+	if (is_mx6dqp()) {
-	if (ret < 0)
+		/* set SW2 staby volatage 0.975V*/
-		return ret;
+		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		value &= ~0x3f;
+		value |= 0x17;
+		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+	}
 
-	return 0;
+	return pfuze_mode_init(p, APS_PFM);
 }
 
 #ifdef CONFIG_CMD_BMODE
@@ -522,6 +539,17 @@ int board_late_init(void)
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "SABREAUTO");
+
+	if (is_mx6dqp())
+		setenv("board_rev", "MX6QP");
+	else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		setenv("board_rev", "MX6Q");
+	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+		setenv("board_rev", "MX6DL");
+#endif
+
 	return 0;
 }
 

board/freescale/mx6sabresd/mx6sabresd.c

@@ -631,7 +631,8 @@ int board_init(void)
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int reg, ret;
+	unsigned int reg;
+	int ret;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
@@ -679,6 +680,16 @@ int board_late_init(void)
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "SABRESD");
+
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		setenv("board_rev", "MX6Q");
+	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+		setenv("board_rev", "MX6DL");
+#endif
+
 	return 0;
 }
 

board/freescale/mx6sxsabresd/mx6sxsabresd.c

@@ -199,7 +199,8 @@ static struct i2c_pads_info i2c_pad_info1 = {
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int reg, ret;
+	unsigned int reg;
+	int ret;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)

board/freescale/mx6ul_14x14_evk/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_MX6UL_14X14_EVK
+
+config SYS_BOARD
+	default "mx6ul_14x14_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "mx6ul_14x14_evk"
+
+endif

board/freescale/mx6ul_14x14_evk/MAINTAINERS

@@ -0,0 +1,6 @@
+MX6ULEVK BOARD
+M:	Peng Fan <Peng.Fan@freescale.com>
+S:	Maintained
+F:	board/freescale/mx6ul_14x14_evk/
+F:	include/configs/mx6ul_14x14_evk.h
+F:	configs/mx6ul_14x14_evk_defconfig

board/freescale/mx6ul_14x14_evk/Makefile

@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ul_14x14_evk.o

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

@@ -0,0 +1,636 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	\
+	PAD_CTL_PUS_100K_DOWN  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define IOX_SDI IMX_GPIO_NR(5, 10)
+#define IOX_STCP IMX_GPIO_NR(5, 7)
+#define IOX_SHCP IMX_GPIO_NR(5, 11)
+#define IOX_OE IMX_GPIO_NR(5, 18)
+
+static iomux_v3_cfg_t const iox_pads[] = {
+	/* IOX_SDI */
+	MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOX_SHCP */
+	MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOX_STCP */
+	MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOX_nOE */
+	MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * HDMI_nRST --> Q0
+ * ENET1_nRST --> Q1
+ * ENET2_nRST --> Q2
+ * CAN1_2_STBY --> Q3
+ * BT_nPWD --> Q4
+ * CSI_RST --> Q5
+ * CSI_PWDN --> Q6
+ * LCD_nPWREN --> Q7
+ */
+enum qn {
+	HDMI_NRST,
+	ENET1_NRST,
+	ENET2_NRST,
+	CAN1_2_STBY,
+	BT_NPWD,
+	CSI_RST,
+	CSI_PWDN,
+	LCD_NPWREN,
+};
+
+enum qn_func {
+	qn_reset,
+	qn_enable,
+	qn_disable,
+};
+
+enum qn_level {
+	qn_low = 0,
+	qn_high = 1,
+};
+
+static enum qn_level seq[3][2] = {
+	{0, 1}, {1, 1}, {0, 0}
+};
+
+static enum qn_func qn_output[8] = {
+	qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
+	qn_disable, qn_enable
+};
+
+static void iox74lv_init(void)
+{
+	int i;
+
+	gpio_direction_output(IOX_OE, 0);
+
+	for (i = 7; i >= 0; i--) {
+		gpio_direction_output(IOX_SHCP, 0);
+		gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+		udelay(500);
+		gpio_direction_output(IOX_SHCP, 1);
+		udelay(500);
+	}
+
+	gpio_direction_output(IOX_STCP, 0);
+	udelay(500);
+	/*
+	 * shift register will be output to pins
+	 */
+	gpio_direction_output(IOX_STCP, 1);
+
+	for (i = 7; i >= 0; i--) {
+		gpio_direction_output(IOX_SHCP, 0);
+		gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+		udelay(500);
+		gpio_direction_output(IOX_SHCP, 1);
+		udelay(500);
+	}
+	gpio_direction_output(IOX_STCP, 0);
+	udelay(500);
+	/*
+	 * shift register will be output to pins
+	 */
+	gpio_direction_output(IOX_STCP, 1);
+
+	gpio_direction_output(IOX_OE, 1);
+};
+
+void iox74lv_set(int index)
+{
+	int i;
+
+	gpio_direction_output(IOX_OE, 0);
+
+	for (i = 7; i >= 0; i--) {
+		gpio_direction_output(IOX_SHCP, 0);
+
+		if (i == index)
+			gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+		else
+			gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+		udelay(500);
+		gpio_direction_output(IOX_SHCP, 1);
+		udelay(500);
+	}
+
+	gpio_direction_output(IOX_STCP, 0);
+	udelay(500);
+	/*
+	 * shift register will be output to pins
+	 */
+	gpio_direction_output(IOX_STCP, 1);
+
+	for (i = 7; i >= 0; i--) {
+		gpio_direction_output(IOX_SHCP, 0);
+		gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+		udelay(500);
+		gpio_direction_output(IOX_SHCP, 1);
+		udelay(500);
+	}
+
+	gpio_direction_output(IOX_STCP, 0);
+	udelay(500);
+	/*
+	 * shift register will be output to pins
+	 */
+	gpio_direction_output(IOX_STCP, 1);
+
+	gpio_direction_output(IOX_OE, 1);
+};
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
+		.gp = IMX_GPIO_NR(1, 28),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
+		.gp = IMX_GPIO_NR(1, 29),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * mx6ul_14x14_evk board default supports sd card. If want to use
+ * EMMC, need to do board rework for sd2.
+ * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
+ * emmc, need to define this macro.
+ */
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*
+	 * RST_B
+	 */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
+	/*
+	 * The evk board uses DAT3 to detect CD card plugin,
+	 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+	 */
+	MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
+	MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
+};
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1	\
+	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+					 ARRAY_SIZE(quadspi_pads));
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+	{USDHC2_BASE_ADDR, 0, 8},
+#else
+	{USDHC2_BASE_ADDR, 0, 4},
+#endif
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
+#define USDHC1_PWR_GPIO	IMX_GPIO_NR(1, 9)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 5)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+		ret = 1;
+#else
+		imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
+						 ARRAY_SIZE(usdhc2_cd_pads));
+		gpio_direction_input(USDHC2_CD_GPIO);
+
+		/*
+		 * Since it is the DAT3 pin, this pin is pulled to
+		 * low voltage if no card
+		 */
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+
+		imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
+						 ARRAY_SIZE(usdhc2_dat3_pads));
+#endif
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+	imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
+					 ARRAY_SIZE(usdhc2_emmc_pads));
+#else
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+#endif
+	gpio_direction_output(USDHC2_PWR_GPIO, 0);
+	udelay(500);
+	gpio_direction_output(USDHC2_PWR_GPIO, 1);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+#else
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
+#else
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+#endif
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+			}
+
+			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+			if (ret) {
+				printf("Warning: failed to initialize mmc dev %d\n", i);
+				return ret;
+			}
+	}
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* At default the 3v3 enables the MIC2026 for VBUS power */
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
+
+	iox74lv_init();
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6UL 14x14 EVK\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00070007,
+	.p0_mpdgctrl0 = 0x41490145,
+	.p0_mprddlctl = 0x40404546,
+	.p0_mpwrdlctl = 0x4040524D,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize = 0,
+		.cs_density = 20,
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 2,
+		.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+		.walat = 1,		/* Write additional latency */
+		.ralat = 5,		/* Read additional latency */
+		.mif3_mode = 3,		/* Command prediction working mode */
+		.bi_on = 1,		/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	};
+
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif

board/tqc/tqma6/Kconfig

@@ -64,6 +64,11 @@ config MBA6
 	  Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
 	  etc.
 
+config WRU4
+	bool "OHB WRU-IV"
+	help
+	  Select the OHB Systems AG WRU-IV baseboard.
+
 endchoice
 
 config IMX_CONFIG

board/tqc/tqma6/Makefile

@@ -7,3 +7,4 @@
 obj-y  := tqma6.o
 
 obj-$(CONFIG_MBA6) += tqma6_mba6.o
+obj-$(CONFIG_WRU4) += tqma6_wru4.o

board/tqc/tqma6/tqma6_wru4.c

@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "tqma6_bb.h"
+
+/* UART */
+#define UART4_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_PKE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
+};
+
+static void setup_iomuxc_uart4(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/* MMC */
+#define USDHC2_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_47K_UP |		\
+		PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_80ohm |		\
+		PAD_CTL_SRE_FAST		\
+		)
+
+#define USDHC2_CLK_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_47K_UP |		\
+		PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_FAST		\
+		)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
+
+	NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
+
+static struct fsl_esdhc_cfg usdhc2_cfg = {
+	.esdhc_base = USDHC2_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+
+	return ret;
+}
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		ret = gpio_get_value(USDHC2_WP_GPIO);
+
+	return ret;
+}
+
+int tqma6_bb_board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
+	if (!ret)
+		gpio_direction_input(USDHC2_CD_GPIO);
+	ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
+	if (!ret)
+		gpio_direction_input(USDHC2_WP_GPIO);
+
+	usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
+		puts("WARNING: failed to initialize SD\n");
+
+	return 0;
+}
+
+/* Ethernet */
+#define ENET_PAD_CTRL (				\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_PKE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
+
+	/* ENET1 reset */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
+	/* ENET1 interrupt */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
+};
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
+
+static void setup_iomuxc_enet(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset LAN8720 PHY */
+	ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
+	if (!ret)
+		gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+	udelay(1000);
+	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return cpu_eth_init(bis);
+}
+
+/* GPIO */
+#define GPIO_PAD_CTRL (				\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+#define GPIO_OD_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_ODE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+static iomux_v3_cfg_t const gpio_pads[] = {
+	/* USB_H_PWR */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
+	/* USB_OTG_PWR */
+	NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
+	/* PCIE_RST */
+	NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
+	/* UART1_PWRON */
+	NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
+	/* UART2_PWRON */
+	NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
+	/* UART3_PWRON */
+	NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
+};
+
+#define GPIO_USB_H_PWR		IMX_GPIO_NR(1, 0)
+#define GPIO_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define GPIO_PCIE_RST		IMX_GPIO_NR(6, 7)
+#define GPIO_UART1_PWRON	IMX_GPIO_NR(5, 8)
+#define GPIO_UART2_PWRON	IMX_GPIO_NR(5, 10)
+#define GPIO_UART3_PWRON	IMX_GPIO_NR(5, 12)
+
+static void gpio_init(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+
+	ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_USB_H_PWR, 1);
+	ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_USB_OTG_PWR, 1);
+	ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
+	if (!ret)
+		gpio_direction_output(GPIO_PCIE_RST, 1);
+	ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_UART1_PWRON, 0);
+	ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_UART2_PWRON, 0);
+	ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_UART3_PWRON, 0);
+}
+
+void tqma6_iomuxc_spi(void)
+{
+	/* No SPI on this baseboard */
+}
+
+int tqma6_bb_board_early_init_f(void)
+{
+	setup_iomuxc_uart4();
+
+	return 0;
+}
+
+int tqma6_bb_board_init(void)
+{
+	setup_iomuxc_enet();
+
+	gpio_init();
+
+	/* Turn the UART-couplers on one-after-another */
+	gpio_set_value(GPIO_UART1_PWRON, 1);
+	mdelay(10);
+	gpio_set_value(GPIO_UART2_PWRON, 1);
+	mdelay(10);
+	gpio_set_value(GPIO_UART3_PWRON, 1);
+
+	return 0;
+}
+
+int tqma6_bb_board_late_init(void)
+{
+	return 0;
+}
+
+const char *tqma6_bb_get_boardname(void)
+{
+	return "WRU-IV";
+}
+
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{ NULL, 0 },
+};
+
+int misc_init_r(void)
+{
+	add_board_boot_modes(board_boot_modes);
+
+	return 0;
+}
+
+#define WRU4_USB_H1_PWR		IMX_GPIO_NR(1, 0)
+#define WRU4_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+
+int board_ehci_hcd_init(int port)
+{
+	int ret;
+
+	ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
+	if (!ret)
+		gpio_direction_output(WRU4_USB_H1_PWR, 1);
+
+	ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
+	if (!ret)
+		gpio_direction_output(WRU4_USB_OTG_PWR, 1);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		gpio_set_value(WRU4_USB_OTG_PWR, on);
+	else
+		gpio_set_value(WRU4_USB_H1_PWR, on);
+
+	return 0;
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
+{
+	/* TBD */
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

board/warp/warp.c

@@ -15,13 +15,17 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <watchdog.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
 #include <mmc.h>
 #include <usb.h>
+#include <power/pmic.h>
+#include <power/max77696_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -35,6 +39,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
 	PAD_CTL_LVE)
 
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -88,6 +97,45 @@ int board_usb_phy_mode(int port)
 	return USB_INIT_DEVICE;
 }
 
+/* I2C1 for PMIC */
+#define I2C_PMIC	0
+#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+};
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_max77696_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("MAX77696");
+	if (!p)
+		return -EINVAL;
+
+	ret = pmic_reg_read(p, CID, &reg);
+	if (ret)
+		return ret;
+
+	printf("PMIC:  MAX77696 detected, rev=0x%x\n", reg);
+
+	return pmic_probe(p);
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -99,6 +147,8 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
 	return 0;
 }
 

configs/cgtqmx6qeval_defconfig

@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_CGTQMX6EVAL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
+CONFIG_CMD_NET=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set

configs/cm_fx6_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
 CONFIG_TARGET_CM_FX6=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
@@ -9,4 +10,23 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_USB=y
+CONFIG_CMD_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MX6=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y

configs/mx6qpsabreauto_defconfig

@@ -0,0 +1,4 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
+CONFIG_SPI_FLASH=y

configs/mx6ul_14x14_evk_defconfig

@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SPL=y

configs/tqma6s_wru4_mmc_defconfig

@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TQMA6=y
+CONFIG_TQMA6S=y
+CONFIG_WRU4=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_NET=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
+CONFIG_AUTOBOOT_ENCRYPTION=y
+CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
+CONFIG_PCA9551_LED=y
+CONFIG_SPI_FLASH=y

drivers/gpio/mxc_gpio.c

@@ -45,11 +45,15 @@ static unsigned long gpio_ports[] = {
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[4] = GPIO5_BASE_ADDR,
+#ifndef CONFIG_MX6UL
 	[5] = GPIO6_BASE_ADDR,
 #endif
+#endif
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#ifndef CONFIG_MX6UL
 	[6] = GPIO7_BASE_ADDR,
 #endif
+#endif
 };
 
 static int mxc_gpio_direction(unsigned int gpio,

drivers/i2c/mxc_i2c.c

@@ -523,7 +523,8 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 #endif
 
 static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
+		defined(CONFIG_VF610)
 	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },

drivers/mmc/fsl_esdhc.c

@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif

drivers/mtd/spi/Kconfig

@@ -42,6 +42,50 @@ config SPI_FLASH_BAR
 	  Bank/Extended address registers are used to access the flash
 	  which has size > 16MiB in 3-byte addressing.
 
+if SPI_FLASH
+
+config SPI_FLASH_ATMEL
+	bool "Atmel SPI flash support"
+	help
+	  Add support for various Atmel SPI flash chips (AT45xxx and AT25xxx)
+
+config SPI_FLASH_EON
+	bool "EON SPI flash support"
+	help
+	  Add support for various EON SPI flash chips (EN25xxx)
+
+config SPI_FLASH_GIGADEVICE
+	bool "GigaDevice SPI flash support"
+	help
+	  Add support for various GigaDevice SPI flash chips (GD25xxx)
+
+config SPI_FLASH_MACRONIX
+	bool "Macronix SPI flash support"
+	help
+	  Add support for various Macronix SPI flash chips (MX25Lxxx)
+
+config SPI_FLASH_SPANSION
+	bool "Spansion SPI flash support"
+	help
+	  Add support for various Spansion SPI flash chips (S25FLxxx)
+
+config SPI_FLASH_STMICRO
+	bool "STMicro SPI flash support"
+	help
+	  Add support for various STMicro SPI flash chips (M25Pxxx and N25Qxxx)
+
+config SPI_FLASH_SST
+	bool "SST SPI flash support"
+	help
+	  Add support for various SST SPI flash chips (SST25xxx)
+
+config SPI_FLASH_WINBOND
+	bool "Winbond SPI flash support"
+	help
+	  Add support for various Winbond SPI flash chips (W25xxx)
+
+endif
+
 config SPI_FLASH_DATAFLASH
 	bool "AT45xxx DataFlash support"
 	depends on SPI_FLASH && DM_SPI_FLASH

drivers/net/fec_mxc.c

@@ -67,13 +67,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #undef DEBUG
 
-struct nbuf {
-	uint8_t data[1500];	/**< actual data */
-	int length;		/**< actual length */
-	int used;		/**< buffer in use or not */
-	uint8_t head[16];	/**< MAC header(6 + 6 + 2) + 2(aligned) */
-};
-
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
 static void swap_packet(uint32_t *packet, int length)
 {
@@ -775,7 +768,6 @@ static int fec_recv(struct eth_device *dev)
 	struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
 	unsigned long ievent;
 	int frame_length, len = 0;
-	struct nbuf *frame;
 	uint16_t bd_status;
 	uint32_t addr, size, end;
 	int i;
@@ -835,12 +827,11 @@ static int fec_recv(struct eth_device *dev)
 			/*
 			 * Get buffer address and size
 			 */
-			frame = (struct nbuf *)readl(&rbd->data_pointer);
+			addr = readl(&rbd->data_pointer);
 			frame_length = readw(&rbd->data_length) - 4;
 			/*
 			 * Invalidate data cache over the buffer
 			 */
-			addr = (uint32_t)frame;
 			end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
 			addr &= ~(ARCH_DMA_MINALIGN - 1);
 			invalidate_dcache_range(addr, end);
@@ -849,16 +840,15 @@ static int fec_recv(struct eth_device *dev)
 			 *  Fill the buffer and pass it to upper layers
 			 */
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
-			swap_packet((uint32_t *)frame->data, frame_length);
+			swap_packet((uint32_t *)addr, frame_length);
 #endif
-			memcpy(buff, frame->data, frame_length);
+			memcpy(buff, (char *)addr, frame_length);
 			net_process_received_packet(buff, frame_length);
 			len = frame_length;
 		} else {
 			if (bd_status & FEC_RBD_ERR)
-				printf("error frame: 0x%08lx 0x%08x\n",
+				printf("error frame: 0x%08x 0x%08x\n",
-						(ulong)rbd->data_pointer,
+				       addr, bd_status);
-						bd_status);
 		}
 
 		/*

drivers/power/pmic/Makefile

@@ -9,6 +9,7 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
+obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
 obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
 obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o

drivers/power/pmic/pmic_max77696.c

@@ -0,0 +1,32 @@
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *  Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/max77696_pmic.h>
+
+int power_max77696_init(unsigned char bus)
+{
+	static const char name[] = "MAX77696";
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = PMIC_NUM_OF_REGS;
+	p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	return 0;
+}

drivers/thermal/imx_thermal.c

@@ -115,7 +115,7 @@ static int read_cpu_temperature(struct udevice *dev)
 	writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
 
 	/* milli_Tmeas = c2 - Nmeas * c1 */
-	temperature = (c2 - n_meas * c1)/1000;
+	temperature = (long)(c2 - n_meas * c1)/1000;
 
 	/* power down anatop thermal sensor */
 	writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
@@ -130,16 +130,12 @@ int imx_thermal_get_temp(struct udevice *dev, int *temp)
 	int cpu_tmp = 0;
 
 	cpu_tmp = read_cpu_temperature(dev);
-	while (cpu_tmp > priv->minc && cpu_tmp < priv->maxc) {
+	while (cpu_tmp >= priv->critical) {
-		if (cpu_tmp >= priv->critical) {
+		printf("CPU Temperature (%dC) too close to max (%dC)",
-			printf("CPU Temperature (%dC) too close to max (%dC)",
+		       cpu_tmp, priv->maxc);
-			       cpu_tmp, priv->maxc);
+		puts(" waiting...\n");
-			puts(" waiting...\n");
+		udelay(5000000);
-			udelay(5000000);
+		cpu_tmp = read_cpu_temperature(dev);
-			cpu_tmp = read_cpu_temperature(dev);
-		} else {
-			break;
-		}
 	}
 
 	*temp = cpu_tmp;

drivers/usb/Kconfig

@@ -1,3 +1,4 @@
+menu USB
 config USB_ARCH_HAS_HCD
 	def_bool y
 
@@ -59,4 +60,32 @@ config USB_STORAGE
 	  Say Y here if you want to connect USB mass storage devices to your
 	  board's USB port.
 
+config USB_KEYBOARD
+	bool "USB Keyboard support"
+	---help---
+	  Say Y here if you want to use a USB keyboard for U-Boot command line
+	  input.
+
+if USB_KEYBOARD
+
+choice
+	prompt "USB keyboard polling"
+	optional
+	---help---
+	  Enable a polling mechanism for USB keyboard.
+
+	config SYS_USB_EVENT_POLL
+		bool "Interrupt polling"
+
+	config SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+		bool "Poll via interrupt queue"
+
+	config SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+		bool "Poll via control EP"
+
+endchoice
+
+endif
+
 endif
+endmenu

drivers/usb/host/Kconfig

@@ -52,6 +52,13 @@ config USB_EHCI
 
 if USB_EHCI_HCD
 
+config USB_EHCI_MX6
+	bool "Support for i.MX6 on-chip EHCI USB controller"
+	depends on ARCH_MX6
+	default y
+	---help---
+	  Enables support for the on-chip EHCI controller on i.MX6 SoCs.
+
 config USB_EHCI_UNIPHIER
 	bool "Support for UniPhier on-chip EHCI USB controller"
 	depends on ARCH_UNIPHIER && OF_CONTROL

include/configs/aristainetos-common.h

@@ -26,9 +26,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 

include/configs/cgtqmx6eval.h

@@ -32,36 +32,116 @@
 /* Miscellaneous commands */
 #define CONFIG_CMD_BMODE
 
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
+/* Thermal support */
+#define CONFIG_IMX6_THERMAL
+
+#define CONFIG_CMD_FUSE
+#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#ifdef CONFIG_MX6DL
+#define CONFIG_IPUV3_CLK 198000000
+#else
+#define CONFIG_IPUV3_CLK 264000000
+#endif
+#define CONFIG_IMX_HDMI
+
+/* SATA */
+#define CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+
+/* Command definition */
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONFIG_CONSOLE_DEV	"ttymxc1"
+#define CONFIG_MMCROOT		"/dev/mmcblk0p2"
+#define CONFIG_SYS_MMC_ENV_DEV		0
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdtfile=imx6q-qmx6.dtb\0" \
-	"boot_dir=/boot\0" \
+	"fdt_addr_r=0x18000000\0" \
-	"console=ttymxc1\0" \
-	"fdt_high=0xffffffff\0" \
-	"initrd_high=0xffffffff\0" \
-	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
-	"mmcdev=1\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONFIG_CONSOLE_DEV "\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
 	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
-		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-		"${boot_dir}/${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
-	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
-		"${boot_dir}/${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr_r}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
 					"bootz; " \
@@ -71,27 +151,44 @@
 			"fi; " \
 		"else " \
 			"bootz; " \
-		"fi;\0"
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"bootz ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	   "mmc dev ${mmcdev};" \
+	"mmc dev ${mmcdev};" \
-	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+	"if mmc rescan; then " \
-		   "if run loadbootscript; then " \
+		"if run loadbootscript; then " \
-			   "run bootscript; " \
+		"run bootscript; " \
-		   "else " \
+		"else " \
-			   "if run loadimage; then " \
+			"if run loadimage; then " \
-				   "run mmcboot; " \
+				"run mmcboot; " \
-			   "else "\
+			"else run netboot; " \
-				   "echo ERR: Fail to boot from mmc; " \
+			"fi; " \
-			   "fi; " \
+		"fi; " \
-		   "fi; " \
+	"else run netboot; fi"
-	   "else echo ERR: Fail to boot from mmc; fi"
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT	       "CGT-QMX6-Quad U-Boot > "
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
 #define CONFIG_SYS_MEMTEST_END	       0x10010000

include/configs/cm_fx6.h

@@ -50,7 +50,6 @@
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
 /* SPI flash */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_BUS		0
 #define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		25000000
@@ -163,14 +162,6 @@
 /* SPI */
 #define CONFIG_SPI
 #define CONFIG_MXC_SPI
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_WINBOND
 
 /* NAND */
 #ifndef CONFIG_SPL_BUILD
@@ -199,20 +190,13 @@
 #define CONFIG_NET_RETRY_COUNT		5
 
 /* USB */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
-#define CONFIG_USB_STORAGE
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 #define CONFIG_SYS_STDIO_DEREGISTER
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
@@ -258,7 +242,6 @@
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_IPUV3_CLK          260000000
 #define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV

include/configs/embestmx6boards.h

@@ -29,11 +29,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* I2C Configs */
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C

include/configs/gw_ventana.h

@@ -165,11 +165,6 @@
 #define CONFIG_CMD_EECONFIG      /* Gateworks EEPROM config cmd */
 #define CONFIG_CMD_UBI
 #define CONFIG_RBTREE
-#define CONFIG_CMD_FUSE          /* eFUSE read/write support */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 
 /* Ethernet support */
 #define CONFIG_FEC_MXC

include/configs/imx6_spl.h

@@ -61,7 +61,7 @@
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
 
-#if defined(CONFIG_MX6SX)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
 #define CONFIG_SPL_BSS_START_ADDR      0x88200000
 #define CONFIG_SPL_BSS_MAX_SIZE        0x100000        /* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START    0x88300000

include/configs/mx53loco.h

@@ -43,6 +43,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
@@ -113,11 +114,11 @@
 	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
 	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
 	"loadbootscript=" \
-		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \

include/configs/mx6_common.h

@@ -17,11 +17,11 @@
 #ifndef __MX6_COMMON_H
 #define __MX6_COMMON_H
 
+#ifndef CONFIG_MX6UL
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
 #define CONFIG_ARM_ERRATA_794072
 #define CONFIG_ARM_ERRATA_761320
-#define CONFIG_BOARD_POSTCLK_INIT
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_L2_PL310
@@ -29,6 +29,8 @@
 #endif
 
 #define CONFIG_MP
+#endif
+#define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MXC_GPT_HCLK
 
 #define CONFIG_SYS_NO_FLASH
@@ -52,7 +54,7 @@
 #define CONFIG_REVISION_TAG
 
 /* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
 #define CONFIG_LOADADDR		0x82000000
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0x87800000
@@ -111,4 +113,8 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 
+/* Fuses */
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
 #endif

include/configs/mx6cuboxi.h

@@ -20,8 +20,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_UART
-#define CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR

include/configs/mx6qsabreauto.h

@@ -12,11 +12,6 @@
 #define CONFIG_MACH_TYPE	3529
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc3"
-#if defined CONFIG_MX6Q
-#define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabreauto.dtb"
-#elif defined CONFIG_MX6DL
-#define CONFIG_DEFAULT_FDT_FILE	"imx6dl-sabreauto.dtb"
-#endif
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"
 #define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
 

include/configs/mx6sabre_common.h

@@ -21,11 +21,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_CMD_FUSE
-#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
@@ -75,10 +70,12 @@
 #define EMMC_ENV ""
 #endif
 
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_file=undefined\0" \
 	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
@@ -148,9 +145,26 @@
 			"fi; " \
 		"else " \
 			"bootz; " \
-		"fi;\0"
+		"fi;\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
+					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
+					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
+					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
+					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
+					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; fi; " \
+			"fi;\0" \
+
 
 #define CONFIG_BOOTCOMMAND \
+	"run findfdt;" \
 	"mmc dev ${mmcdev};" \
 	"if mmc rescan; then " \
 		"if run loadbootscript; then " \

include/configs/mx6sabresd.h

@@ -19,11 +19,6 @@
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc0"
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"
-#if defined(CONFIG_MX6Q)
-#define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabresd.dtb"
-#elif defined(CONFIG_MX6DL)
-#define CONFIG_DEFAULT_FDT_FILE	"imx6dl-sabresd.dtb"
-#endif
 #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
 
 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */

include/configs/mx6slevk.h

@@ -192,9 +192,4 @@
 
 #define CONFIG_IMX6_THERMAL
 
-#define CONFIG_CMD_FUSE
-#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
-#define CONFIG_MXC_OCOTP
-#endif
-
 #endif				/* __CONFIG_H */

include/configs/mx6sxsabresd.h

@@ -178,11 +178,6 @@
 
 #define CONFIG_IMX6_THERMAL
 
-#define CONFIG_CMD_FUSE
-#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
-#define CONFIG_MXC_OCOTP
-#endif
-
 #define CONFIG_CMD_TIME
 
 #define CONFIG_FSL_QSPI

include/configs/mx6ul_14x14_evk.h

@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6UL_14X14_EVK_CONFIG_H
+#define __MX6UL_14X14_EVK_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+/* SPL options */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_MX6
+#define CONFIG_ROM_UNIFIED_SECTIONS
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#endif
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6ul-14x14-evk.dtb\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"=> "
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_BMODE
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED	40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_32M
+#endif
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_IMX6_THERMAL
+
+#endif

include/configs/nitrogen6x.h

@@ -26,11 +26,6 @@
 #define CONFIG_USB_ETH_CDC
 #define CONFIG_NETCONSOLE
 
-#define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	       UART2_BASE
 

include/configs/novena.h

@@ -25,7 +25,6 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_FUSE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
@@ -118,11 +117,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* PCI express */
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI

include/configs/ot1200.h

@@ -16,10 +16,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 
-/* FUSE Configs */
-#define CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-
 /* UART Configs */
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE           UART1_BASE

include/configs/platinum.h

@@ -23,7 +23,6 @@
 
 #define CONFIG_CMD_BMODE
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FUSE
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
@@ -103,9 +102,6 @@
 #define CONFIG_APBH_DMA_BURST
 #define CONFIG_APBH_DMA_BURST8
 
-/* Fuse support */
-#define CONFIG_MXC_OCOTP
-
 /* Environment in NAND */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		(16 << 20)

include/configs/tbs2910.h

@@ -173,12 +173,6 @@
 #define CONFIG_I2C_EDID
 #endif
 
-/* Fuses */
-#define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* Environment organization */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		2

include/configs/tqma6.h

@@ -100,10 +100,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 
-/* Fuses */
-#define CONFIG_MXC_OCOTP
-#define CONFIG_CMD_FUSE
-
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
@@ -393,6 +389,8 @@
  */
 #ifdef CONFIG_MBA6
 #include "tqma6_mba6.h"
+#elif CONFIG_WRU4
+#include "tqma6_wru4.h"
 #else
 #error "No baseboard for the TQMa6 defined!"
 #endif

include/configs/tqma6_wru4.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TQMA6_WRU4_H
+#define __CONFIG_TQMA6_WRU4_H
+
+#define CONFIG_DEFAULT_FDT_FILE		"imx6s-wru4.dtb"
+
+/* DTT sensors */
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+#define CONFIG_SYS_DTT_BUS_NUM		2
+
+/* Ethernet */
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0x01
+#define CONFIG_PHY_SMSC
+
+/* UART */
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc3"
+
+#define CONFIG_MISC_INIT_R
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS	60000
+
+/* Config on-board RTC */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_BUS_NUM		2
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+/* Turn off RTC square-wave output to save battery */
+#define CONFIG_SYS_RTC_DS1337_NOOSC
+#define CONFIG_CMD_DATE
+
+#define CONFIG_CMD_GPIO
+
+/* LED */
+#define CONFIG_CMD_LED
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT			0
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1			1
+#define STATUS_LED_STATE1		STATUS_LED_ON
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2			2
+#define STATUS_LED_STATE2		STATUS_LED_ON
+#define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT3			3
+#define STATUS_LED_STATE3		STATUS_LED_ON
+#define STATUS_LED_PERIOD3		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT4			4
+#define STATUS_LED_STATE4		STATUS_LED_ON
+#define STATUS_LED_PERIOD4		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT5			5
+#define STATUS_LED_STATE5		STATUS_LED_ON
+#define STATUS_LED_PERIOD5		(CONFIG_SYS_HZ / 2)
+
+/* Bootcounter */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#endif /* __CONFIG_TQMA6_WRU4_H */

include/configs/wandboard.h

@@ -84,11 +84,6 @@
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
-#define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \

include/configs/warp.h

@@ -94,9 +94,16 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
-/* Fuses */
+/* I2C Configs */
-#define CONFIG_CMD_FUSE
+#define CONFIG_CMD_I2C
-#define CONFIG_MXC_OCOTP
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77696
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \

include/power/max77696_pmic.h

@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *  Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX77696_PMIC_H__
+#define __MAX77696_PMIC_H__
+
+#define CONFIG_POWER_MAX77696_I2C_ADDR	0x3C
+
+enum {
+	L01_CNFG1 =	0x43,
+	L01_CNFG2,
+	L02_CNFG1,
+	L02_CNFG2,
+	L03_CNFG1,
+	L03_CNFG2,
+	L04_CNFG1,
+	L04_CNFG2,
+	L05_CNFG1,
+	L05_CNFG2,
+	L06_CNFG1,
+	L06_CNFG2,
+	L07_CNFG1,
+	L07_CNFG2,
+	L08_CNFG1,
+	L08_CNFG2,
+	L09_CNFG1,
+	L09_CNFG2,
+	L10_CNFG1,
+	L10_CNFG2,
+	LDO_INT1,
+	LDO_INT2,
+	LDO_INT1M,
+	LDO_INT2M,
+	LDO_CNFG3,
+	SW1_CNTRL,
+	SW2_CNTRL,
+	SW3_CNTRL,
+	SW4_CNTRL,
+	EPDCNFG,
+	EPDINTS,
+	EPDINT,
+	EPDINTM,
+	EPDVCOM,
+	EPDVEE,
+	EPDVNEG,
+	EPDVPOS,
+	EPDVDDH,
+	EPDSEQ,
+	EPDOKINTS,
+	CID =	0x9c,
+	PMIC_NUM_OF_REGS,
+};
+
+int power_max77696_init(unsigned char bus);
+
+#endif

include/thermal.h

@@ -13,7 +13,7 @@
 int thermal_get_temp(struct udevice *dev, int *temp);
 
 /**
- * struct struct dm_thermal_ops - Driver model Thermal operations
+ * struct dm_thermal_ops - Driver model Thermal operations
  *
  * The uclass interface is implemented by all Thermal devices which use
  * driver model.
@@ -22,19 +22,11 @@ struct dm_thermal_ops {
 	/**
 	 * Get the current temperature
 	 *
-	 * The device provided is the slave device. It's parent controller
+	 * This must be called before doing any transfers with a Thermal device.
-	 * will be used to provide the communication.
+	 * It will enable and initialize any Thermal hardware as necessary.
-	 *
-	 * This must be called before doing any transfers with a Thermal slave.
-	 * It will enable and initialize any Thermal hardware as necessary,
-	 * and make sure that the SCK line is in the correct idle state. It is
-	 * not allowed to claim the same bus for several slaves without
-	 * releasing the bus in between.
 	 *
 	 * @dev:	The Thermal device
-	 *
+	 * @temp:	pointer that returns the measured temperature
-	 * Returns: 0 if the bus was claimed successfully, or a negative value
-	 * if it wasn't.
 	 */
 	int (*get_temp)(struct udevice *dev, int *temp);
 };

tools/imximage.c

@@ -21,7 +21,10 @@
 static table_entry_t imximage_cmds[] = {
 	{CMD_BOOT_FROM,         "BOOT_FROM",            "boot command",	  },
 	{CMD_BOOT_OFFSET,       "BOOT_OFFSET",          "Boot offset",	  },
-	{CMD_DATA,              "DATA",                 "Reg Write Data", },
+	{CMD_WRITE_DATA,        "DATA",                 "Reg Write Data", },
+	{CMD_WRITE_CLR_BIT,     "CLR_BIT",              "Reg clear bit",  },
+	{CMD_CHECK_BITS_SET,    "CHECK_BITS_SET",   "Reg Check bits set", },
+	{CMD_CHECK_BITS_CLR,    "CHECK_BITS_CLR",   "Reg Check bits clr", },
 	{CMD_CSF,               "CSF",           "Command Sequence File", },
 	{CMD_IMAGE_VERSION,     "IMAGE_VERSION",        "image version",  },
 	{-1,                    "",                     "",	          },
@@ -62,7 +65,7 @@ static table_entry_t imximage_boot_loadsize[] = {
  */
 static table_entry_t imximage_versions[] = {
 	{IMXIMAGE_V1,	"",	" (i.MX25/35/51 compatible)", },
-	{IMXIMAGE_V2,	"",	" (i.MX53/6 compatible)",     },
+	{IMXIMAGE_V2,	"",	" (i.MX53/6/7 compatible)",   },
 	{-1,            "",     " (Invalid)",                 },
 };
 
@@ -79,6 +82,7 @@ static uint32_t imximage_csf_size = UNDEFINED;
 static uint32_t imximage_init_loadsize;
 
 static set_dcd_val_t set_dcd_val;
+static set_dcd_param_t set_dcd_param;
 static set_dcd_rst_t set_dcd_rst;
 static set_imx_hdr_t set_imx_hdr;
 static uint32_t max_dcd_entries;
@@ -156,6 +160,43 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
 	}
 }
 
+static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+		int32_t cmd)
+{
+	dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+
+	switch (cmd) {
+	case CMD_WRITE_DATA:
+		dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+		dcd_v2->write_dcd_command.length = cpu_to_be16(
+				dcd_len * sizeof(dcd_addr_data_t) + 4);
+		dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
+		break;
+	case CMD_WRITE_CLR_BIT:
+		dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+		dcd_v2->write_dcd_command.length = cpu_to_be16(
+				dcd_len * sizeof(dcd_addr_data_t) + 4);
+		dcd_v2->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
+		break;
+	/*
+	 * Check data command only supports one entry,
+	 * so use 0xC = size(address + value + command).
+	 */
+	case CMD_CHECK_BITS_SET:
+		dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+		dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
+		dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+		break;
+	case CMD_CHECK_BITS_CLR:
+		dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+		dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
+		dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+		break;
+	default:
+		break;
+	}
+}
+
 static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
 					int fld, uint32_t value, uint32_t off)
 {
@@ -200,10 +241,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 	dcd_v2->header.length = cpu_to_be16(
 			dcd_len * sizeof(dcd_addr_data_t) + 8);
 	dcd_v2->header.version = DCD_VERSION;
-	dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
+	set_dcd_param_v2(imxhdr, dcd_len, CMD_WRITE_DATA);
-	dcd_v2->write_dcd_command.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 4);
-	dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
 }
 
 static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
@@ -266,12 +304,14 @@ static void set_hdr_func(void)
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
 		set_dcd_val = set_dcd_val_v1;
+		set_dcd_param = NULL;
 		set_dcd_rst = set_dcd_rst_v1;
 		set_imx_hdr = set_imx_hdr_v1;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
 		break;
 	case IMXIMAGE_V2:
 		set_dcd_val = set_dcd_val_v2;
+		set_dcd_param = set_dcd_param_v2;
 		set_dcd_rst = set_dcd_rst_v2;
 		set_imx_hdr = set_imx_hdr_v2;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V2;
@@ -396,8 +436,13 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;
-	case CMD_DATA:
+	case CMD_WRITE_DATA:
+	case CMD_WRITE_CLR_BIT:
+	case CMD_CHECK_BITS_SET:
+	case CMD_CHECK_BITS_CLR:
 		value = get_cfg_value(token, name, lineno);
+		if (set_dcd_param)
+			(*set_dcd_param)(imxhdr, dcd_len, cmd);
 		(*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
@@ -436,20 +481,30 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
 		break;
 	case CFG_REG_ADDRESS:
 	case CFG_REG_VALUE:
-		if (*cmd != CMD_DATA)
+		switch(*cmd) {
-			return;
+		case CMD_WRITE_DATA:
-
+		case CMD_WRITE_CLR_BIT:
-		value = get_cfg_value(token, name, lineno);
+		case CMD_CHECK_BITS_SET:
-		(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
+		case CMD_CHECK_BITS_CLR:
-
+
-		if (fld == CFG_REG_VALUE) {
+			value = get_cfg_value(token, name, lineno);
-			(*dcd_len)++;
+			if (set_dcd_param)
-			if (*dcd_len > max_dcd_entries) {
+				(*set_dcd_param)(imxhdr, *dcd_len, *cmd);
-				fprintf(stderr, "Error: %s[%d] -"
+			(*set_dcd_val)(imxhdr, name, lineno, fld, value,
-					"DCD table exceeds maximum size(%d)\n",
+					*dcd_len);
-					name, lineno, max_dcd_entries);
+
-				exit(EXIT_FAILURE);
+			if (fld == CFG_REG_VALUE) {
+				(*dcd_len)++;
+				if (*dcd_len > max_dcd_entries) {
+					fprintf(stderr, "Error: %s[%d] -"
+						"DCD table exceeds maximum size(%d)\n",
+						name, lineno, max_dcd_entries);
+					exit(EXIT_FAILURE);
+				}
 			}
+			break;
+		default:
+			break;
 		}
 		break;
 	default:

tools/imximage.h

@@ -42,19 +42,27 @@
 #define FLASH_LOADSIZE_SATA		FLASH_LOADSIZE_STANDARD
 #define FLASH_LOADSIZE_QSPI		0x0 /* entire image */
 
-#define IVT_HEADER_TAG 0xD1
+/* Command tags and parameters */
-#define IVT_VERSION 0x40
+#define IVT_HEADER_TAG			0xD1
-#define DCD_HEADER_TAG 0xD2
+#define IVT_VERSION			0x40
-#define DCD_COMMAND_TAG 0xCC
+#define DCD_HEADER_TAG			0xD2
-#define DCD_VERSION 0x40
+#define DCD_VERSION			0x40
-#define DCD_COMMAND_PARAM 0x4
+#define DCD_WRITE_DATA_COMMAND_TAG	0xCC
+#define DCD_WRITE_DATA_PARAM		0x4
+#define DCD_WRITE_CLR_BIT_PARAM	0xC
+#define DCD_CHECK_DATA_COMMAND_TAG	0xCF
+#define DCD_CHECK_BITS_SET_PARAM	0x14
+#define DCD_CHECK_BITS_CLR_PARAM	0x04
 
 enum imximage_cmd {
 	CMD_INVALID,
 	CMD_IMAGE_VERSION,
 	CMD_BOOT_FROM,
 	CMD_BOOT_OFFSET,
-	CMD_DATA,
+	CMD_WRITE_DATA,
+	CMD_WRITE_CLR_BIT,
+	CMD_CHECK_BITS_SET,
+	CMD_CHECK_BITS_CLR,
 	CMD_CSF,
 };
 
@@ -129,6 +137,7 @@ typedef struct {
 	ivt_header_t header;
 	write_dcd_command_t write_dcd_command;
 	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
+	uint32_t padding[1]; /* end up on an 8-byte boundary */
 } dcd_v2_t;
 
 typedef struct {
@@ -167,6 +176,9 @@ typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
 					int fld, uint32_t value,
 					uint32_t off);
 
+typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+					int32_t cmd);
+
 typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
 					uint32_t dcd_len,
 					char *name, int lineno);