Tom Rini
10 years ago
commit
7a1af7a79b
@ -0,0 +1,45 @@ |
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ASM_ARCH_MX6UL_DDR_H__ |
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#define __ASM_ARCH_MX6UL_DDR_H__ |
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#ifndef CONFIG_MX6UL |
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#error "wrong CPU" |
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#endif |
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#define MX6_IOM_DRAM_DQM0 0x020e0244 |
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#define MX6_IOM_DRAM_DQM1 0x020e0248 |
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#define MX6_IOM_DRAM_RAS 0x020e024c |
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#define MX6_IOM_DRAM_CAS 0x020e0250 |
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#define MX6_IOM_DRAM_CS0 0x020e0254 |
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#define MX6_IOM_DRAM_CS1 0x020e0258 |
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#define MX6_IOM_DRAM_SDWE_B 0x020e025c |
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#define MX6_IOM_DRAM_SDODT0 0x020e0260 |
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#define MX6_IOM_DRAM_SDODT1 0x020e0264 |
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#define MX6_IOM_DRAM_SDBA0 0x020e0268 |
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#define MX6_IOM_DRAM_SDBA1 0x020e026c |
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#define MX6_IOM_DRAM_SDBA2 0x020e0270 |
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#define MX6_IOM_DRAM_SDCKE0 0x020e0274 |
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#define MX6_IOM_DRAM_SDCKE1 0x020e0278 |
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#define MX6_IOM_DRAM_SDCLK_0 0x020e027c |
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#define MX6_IOM_DRAM_SDQS0 0x020e0280 |
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#define MX6_IOM_DRAM_SDQS1 0x020e0284 |
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#define MX6_IOM_DRAM_RESET 0x020e0288 |
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#define MX6_IOM_GRP_ADDDS 0x020e0490 |
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#define MX6_IOM_DDRMODE_CTL 0x020e0494 |
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#define MX6_IOM_GRP_B0DS 0x020e0498 |
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#define MX6_IOM_GRP_DDRPK 0x020e049c |
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#define MX6_IOM_GRP_CTLDS 0x020e04a0 |
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#define MX6_IOM_GRP_B1DS 0x020e04a4 |
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#define MX6_IOM_GRP_DDRHYS 0x020e04a8 |
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#define MX6_IOM_GRP_DDRPKE 0x020e04ac |
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#define MX6_IOM_GRP_DDRMODE 0x020e04b0 |
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#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4 |
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#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ |
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Load Diff
@ -0,0 +1,145 @@ |
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/* |
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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/* image version */ |
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#define __ASSEMBLY__ |
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#include <config.h> |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of spi, sd, eimnor, nand, sata: |
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* spinor: flash_offset: 0x0400 |
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* nand: flash_offset: 0x0400 |
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* sata: flash_offset: 0x0400 |
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* sd/mmc: flash_offset: 0x0400 |
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* eimnor: flash_offset: 0x1000 |
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*/ |
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BOOT_FROM sd |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x020e0798 0x000C0000 |
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DATA 4 0x020e0758 0x00000000 |
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DATA 4 0x020e0588 0x00000030 |
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DATA 4 0x020e0594 0x00000030 |
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DATA 4 0x020e056c 0x00000030 |
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DATA 4 0x020e0578 0x00000030 |
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DATA 4 0x020e074c 0x00000030 |
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DATA 4 0x020e057c 0x00000030 |
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DATA 4 0x020e058c 0x00000000 |
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DATA 4 0x020e059c 0x00000030 |
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DATA 4 0x020e05a0 0x00000030 |
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DATA 4 0x020e078c 0x00000030 |
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DATA 4 0x020e0750 0x00020000 |
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DATA 4 0x020e05a8 0x00000030 |
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DATA 4 0x020e05b0 0x00000030 |
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DATA 4 0x020e0524 0x00000030 |
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DATA 4 0x020e051c 0x00000030 |
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DATA 4 0x020e0518 0x00000030 |
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DATA 4 0x020e050c 0x00000030 |
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DATA 4 0x020e05b8 0x00000030 |
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DATA 4 0x020e05c0 0x00000030 |
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DATA 4 0x020e0774 0x00020000 |
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DATA 4 0x020e0784 0x00000030 |
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DATA 4 0x020e0788 0x00000030 |
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DATA 4 0x020e0794 0x00000030 |
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DATA 4 0x020e079c 0x00000030 |
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DATA 4 0x020e07a0 0x00000030 |
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DATA 4 0x020e07a4 0x00000030 |
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DATA 4 0x020e07a8 0x00000030 |
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DATA 4 0x020e0748 0x00000030 |
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DATA 4 0x020e05ac 0x00000030 |
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DATA 4 0x020e05b4 0x00000030 |
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DATA 4 0x020e0528 0x00000030 |
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DATA 4 0x020e0520 0x00000030 |
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DATA 4 0x020e0514 0x00000030 |
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DATA 4 0x020e0510 0x00000030 |
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DATA 4 0x020e05bc 0x00000030 |
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DATA 4 0x020e05c4 0x00000030 |
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DATA 4 0x021b0800 0xa1390003 |
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DATA 4 0x021b080c 0x001b001e |
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DATA 4 0x021b0810 0x002e0029 |
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DATA 4 0x021b480c 0x001b002a |
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DATA 4 0x021b4810 0x0019002c |
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DATA 4 0x021b083c 0x43240334 |
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DATA 4 0x021b0840 0x0324031a |
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DATA 4 0x021b483c 0x43340344 |
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DATA 4 0x021b4840 0x03280276 |
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DATA 4 0x021b0848 0x44383A3E |
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DATA 4 0x021b4848 0x3C3C3846 |
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DATA 4 0x021b0850 0x2e303230 |
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DATA 4 0x021b4850 0x38283E34 |
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DATA 4 0x021b081c 0x33333333 |
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DATA 4 0x021b0820 0x33333333 |
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DATA 4 0x021b0824 0x33333333 |
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DATA 4 0x021b0828 0x33333333 |
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DATA 4 0x021b481c 0x33333333 |
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DATA 4 0x021b4820 0x33333333 |
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DATA 4 0x021b4824 0x33333333 |
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DATA 4 0x021b4828 0x33333333 |
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DATA 4 0x021b08c0 0x24912492 |
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DATA 4 0x021b48c0 0x24912492 |
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DATA 4 0x021b08b8 0x00000800 |
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DATA 4 0x021b48b8 0x00000800 |
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DATA 4 0x021b0004 0x00020036 |
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DATA 4 0x021b0008 0x09444040 |
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DATA 4 0x021b000c 0x898E7955 |
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DATA 4 0x021b0010 0xFF328F64 |
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DATA 4 0x021b0014 0x01FF00DB |
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DATA 4 0x021b0018 0x00001740 |
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DATA 4 0x021b001c 0x00008000 |
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DATA 4 0x021b002c 0x000026d2 |
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DATA 4 0x021b0030 0x008E1023 |
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DATA 4 0x021b0040 0x00000047 |
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DATA 4 0x021b0400 0x14420000 |
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DATA 4 0x021b0000 0x841A0000 |
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DATA 4 0x00bb0008 0x00000004 |
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DATA 4 0x00bb000c 0x2891E41A |
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DATA 4 0x00bb0038 0x00000564 |
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DATA 4 0x00bb0014 0x00000040 |
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DATA 4 0x00bb0028 0x00000020 |
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DATA 4 0x00bb002c 0x00000020 |
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DATA 4 0x021b001c 0x04088032 |
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DATA 4 0x021b001c 0x00008033 |
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DATA 4 0x021b001c 0x00048031 |
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DATA 4 0x021b001c 0x09408030 |
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DATA 4 0x021b001c 0x04008040 |
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DATA 4 0x021b0020 0x00005800 |
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DATA 4 0x021b0818 0x00011117 |
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DATA 4 0x021b4818 0x00011117 |
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DATA 4 0x021b0004 0x00025576 |
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DATA 4 0x021b0404 0x00011006 |
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DATA 4 0x021b001c 0x00000000 |
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/* set the default clock gate to save power */ |
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DATA 4, 0x020c4068, 0x00C03F3F |
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DATA 4, 0x020c406c, 0x0030FC03 |
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DATA 4, 0x020c4070, 0x0FFFC000 |
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DATA 4, 0x020c4074, 0x3FF00000 |
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DATA 4, 0x020c4078, 0xFFFFF300 |
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DATA 4, 0x020c407c, 0x0F0000F3 |
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DATA 4, 0x020c4080, 0x00000FFF |
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/* enable AXI cache for VDOA/VPU/IPU */ |
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DATA 4, 0x020e0010, 0xF00000CF |
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/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ |
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DATA 4, 0x020e0018, 0x77177717 |
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DATA 4, 0x020e001c, 0x77177717 |
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@ -0,0 +1,15 @@ |
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if TARGET_MX6UL_14X14_EVK |
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config SYS_BOARD |
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default "mx6ul_14x14_evk" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "mx6" |
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config SYS_CONFIG_NAME |
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default "mx6ul_14x14_evk" |
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endif |
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@ -0,0 +1,6 @@ |
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MX6ULEVK BOARD |
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M: Peng Fan <Peng.Fan@freescale.com> |
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S: Maintained |
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F: board/freescale/mx6ul_14x14_evk/ |
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F: include/configs/mx6ul_14x14_evk.h |
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F: configs/mx6ul_14x14_evk_defconfig |
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@ -0,0 +1,6 @@ |
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# (C) Copyright 2015 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx6ul_14x14_evk.o
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@ -0,0 +1,636 @@ |
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/mx6ul_pins.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <asm/io.h> |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <i2c.h> |
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#include <linux/sizes.h> |
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#include <mmc.h> |
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#include <usb.h> |
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#include <usb/ehci-fsl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE) |
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#define IOX_SDI IMX_GPIO_NR(5, 10) |
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#define IOX_STCP IMX_GPIO_NR(5, 7) |
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#define IOX_SHCP IMX_GPIO_NR(5, 11) |
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#define IOX_OE IMX_GPIO_NR(5, 18) |
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static iomux_v3_cfg_t const iox_pads[] = { |
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/* IOX_SDI */ |
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MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* IOX_SHCP */ |
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MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* IOX_STCP */ |
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MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* IOX_nOE */ |
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MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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/*
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* HDMI_nRST --> Q0 |
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* ENET1_nRST --> Q1 |
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* ENET2_nRST --> Q2 |
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* CAN1_2_STBY --> Q3 |
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* BT_nPWD --> Q4 |
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* CSI_RST --> Q5 |
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* CSI_PWDN --> Q6 |
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* LCD_nPWREN --> Q7 |
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*/ |
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enum qn { |
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HDMI_NRST, |
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ENET1_NRST, |
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ENET2_NRST, |
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CAN1_2_STBY, |
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BT_NPWD, |
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CSI_RST, |
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CSI_PWDN, |
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LCD_NPWREN, |
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}; |
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enum qn_func { |
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qn_reset, |
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qn_enable, |
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qn_disable, |
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}; |
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enum qn_level { |
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qn_low = 0, |
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qn_high = 1, |
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}; |
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static enum qn_level seq[3][2] = { |
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{0, 1}, {1, 1}, {0, 0} |
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}; |
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static enum qn_func qn_output[8] = { |
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qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, |
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qn_disable, qn_enable |
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}; |
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static void iox74lv_init(void) |
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{ |
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int i; |
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gpio_direction_output(IOX_OE, 0); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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gpio_direction_output(IOX_OE, 1); |
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}; |
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void iox74lv_set(int index) |
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{ |
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int i; |
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gpio_direction_output(IOX_OE, 0); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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if (i == index) |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); |
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else |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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gpio_direction_output(IOX_OE, 1); |
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}; |
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#ifdef CONFIG_SYS_I2C_MXC |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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/* I2C1 for PMIC and EEPROM */ |
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struct i2c_pads_info i2c_pad_info1 = { |
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.scl = { |
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.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, |
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.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, |
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.gp = IMX_GPIO_NR(1, 28), |
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}, |
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.sda = { |
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.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, |
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.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, |
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.gp = IMX_GPIO_NR(1, 29), |
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}, |
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}; |
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#endif |
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int dram_init(void) |
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{ |
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gd->ram_size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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static iomux_v3_cfg_t const uart1_pads[] = { |
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc1_pads[] = { |
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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/* VSELECT */ |
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MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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/* CD */ |
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MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* RST_B */ |
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MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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/*
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* mx6ul_14x14_evk board default supports sd card. If want to use |
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* EMMC, need to do board rework for sd2. |
||||
* Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support |
||||
* emmc, need to define this macro. |
||||
*/ |
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) |
||||
static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { |
||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
|
||||
/*
|
||||
* RST_B |
||||
*/ |
||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
#else |
||||
static iomux_v3_cfg_t const usdhc2_pads[] = { |
||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const usdhc2_cd_pads[] = { |
||||
/*
|
||||
* The evk board uses DAT3 to detect CD card plugin, |
||||
* in u-boot we mux the pin to GPIO when doing board_mmc_getcd. |
||||
*/ |
||||
MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { |
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | |
||||
MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), |
||||
}; |
||||
#endif |
||||
|
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_QSPI |
||||
|
||||
#define QSPI_PAD_CTRL1 \ |
||||
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) |
||||
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = { |
||||
MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
||||
MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
||||
MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
||||
MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
||||
MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
||||
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
||||
}; |
||||
|
||||
int board_qspi_init(void) |
||||
{ |
||||
/* Set the iomux */ |
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads, |
||||
ARRAY_SIZE(quadspi_pads)); |
||||
/* Set the clock */ |
||||
enable_qspi_clk(0); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
||||
{USDHC1_BASE_ADDR, 0, 4}, |
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) |
||||
{USDHC2_BASE_ADDR, 0, 8}, |
||||
#else |
||||
{USDHC2_BASE_ADDR, 0, 4}, |
||||
#endif |
||||
}; |
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) |
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) |
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) |
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret = 0; |
||||
|
||||
switch (cfg->esdhc_base) { |
||||
case USDHC1_BASE_ADDR: |
||||
ret = !gpio_get_value(USDHC1_CD_GPIO); |
||||
break; |
||||
case USDHC2_BASE_ADDR: |
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) |
||||
ret = 1; |
||||
#else |
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, |
||||
ARRAY_SIZE(usdhc2_cd_pads)); |
||||
gpio_direction_input(USDHC2_CD_GPIO); |
||||
|
||||
/*
|
||||
* Since it is the DAT3 pin, this pin is pulled to |
||||
* low voltage if no card |
||||
*/ |
||||
ret = gpio_get_value(USDHC2_CD_GPIO); |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, |
||||
ARRAY_SIZE(usdhc2_dat3_pads)); |
||||
#endif |
||||
break; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
#ifdef CONFIG_SPL_BUILD |
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) |
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, |
||||
ARRAY_SIZE(usdhc2_emmc_pads)); |
||||
#else |
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
||||
#endif |
||||
gpio_direction_output(USDHC2_PWR_GPIO, 0); |
||||
udelay(500); |
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1); |
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); |
||||
#else |
||||
int i, ret; |
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done: |
||||
* (U-boot device node) (Physical Port) |
||||
* mmc0 USDHC1 |
||||
* mmc1 USDHC2 |
||||
*/ |
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
||||
switch (i) { |
||||
case 0: |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
||||
gpio_direction_input(USDHC1_CD_GPIO); |
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 0); |
||||
udelay(500); |
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1); |
||||
break; |
||||
case 1: |
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); |
||||
#else |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
||||
#endif |
||||
gpio_direction_output(USDHC2_PWR_GPIO, 0); |
||||
udelay(500); |
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1); |
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
||||
break; |
||||
default: |
||||
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
||||
if (ret) { |
||||
printf("Warning: failed to initialize mmc dev %d\n", i); |
||||
return ret; |
||||
} |
||||
} |
||||
#endif |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6 |
||||
#define USB_OTHERREGS_OFFSET 0x800 |
||||
#define UCTRL_PWR_POL (1 << 9) |
||||
|
||||
static iomux_v3_cfg_t const usb_otg_pads[] = { |
||||
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
/* At default the 3v3 enables the MIC2026 for VBUS power */ |
||||
static void setup_usb(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
||||
ARRAY_SIZE(usb_otg_pads)); |
||||
} |
||||
|
||||
int board_usb_phy_mode(int port) |
||||
{ |
||||
if (port == 1) |
||||
return USB_INIT_HOST; |
||||
else |
||||
return usb_phy_mode(port); |
||||
} |
||||
|
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
u32 *usbnc_usb_ctrl; |
||||
|
||||
if (port > 1) |
||||
return -EINVAL; |
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
||||
port * 4); |
||||
|
||||
/* Set Power polarity */ |
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); |
||||
|
||||
iox74lv_init(); |
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC |
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6 |
||||
setup_usb(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_QSPI |
||||
board_qspi_init(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, |
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
||||
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, |
||||
{NULL, 0}, |
||||
}; |
||||
#endif |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
#ifdef CONFIG_CMD_BMODE |
||||
add_board_boot_modes(board_boot_modes); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
return get_cpu_rev(); |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: MX6UL 14x14 EVK\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#include <libfdt.h> |
||||
#include <spl.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
|
||||
const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { |
||||
.dram_dqm0 = 0x00000030, |
||||
.dram_dqm1 = 0x00000030, |
||||
.dram_ras = 0x00000030, |
||||
.dram_cas = 0x00000030, |
||||
.dram_odt0 = 0x00000030, |
||||
.dram_odt1 = 0x00000030, |
||||
.dram_sdba2 = 0x00000000, |
||||
.dram_sdclk_0 = 0x00000008, |
||||
.dram_sdqs0 = 0x00000038, |
||||
.dram_sdqs1 = 0x00000030, |
||||
.dram_reset = 0x00000030, |
||||
}; |
||||
|
||||
const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
||||
.grp_addds = 0x00000030, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
.grp_b0ds = 0x00000030, |
||||
.grp_ctlds = 0x00000030, |
||||
.grp_b1ds = 0x00000030, |
||||
.grp_ddrpke = 0x00000000, |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_ddr_type = 0x000c0000, |
||||
}; |
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
||||
.p0_mpwldectrl0 = 0x00070007, |
||||
.p0_mpdgctrl0 = 0x41490145, |
||||
.p0_mprddlctl = 0x40404546, |
||||
.p0_mpwrdlctl = 0x4040524D, |
||||
}; |
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = { |
||||
.mem_speed = 800, |
||||
.density = 4, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 15, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0); |
||||
writel(0xFFFFFFFF, &ccm->CCGR1); |
||||
writel(0xFFFFFFFF, &ccm->CCGR2); |
||||
writel(0xFFFFFFFF, &ccm->CCGR3); |
||||
writel(0xFFFFFFFF, &ccm->CCGR4); |
||||
writel(0xFFFFFFFF, &ccm->CCGR5); |
||||
writel(0xFFFFFFFF, &ccm->CCGR6); |
||||
writel(0xFFFFFFFF, &ccm->CCGR7); |
||||
} |
||||
|
||||
static void spl_dram_init(void) |
||||
{ |
||||
struct mx6_ddr_sysinfo sysinfo = { |
||||
.dsize = 0, |
||||
.cs_density = 20, |
||||
.ncs = 1, |
||||
.cs1_mirror = 0, |
||||
.rtt_wr = 2, |
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */ |
||||
.walat = 1, /* Write additional latency */ |
||||
.ralat = 5, /* Read additional latency */ |
||||
.mif3_mode = 3, /* Command prediction working mode */ |
||||
.bi_on = 1, /* Bank interleaving enabled */ |
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
||||
}; |
||||
|
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
ccgr_init(); |
||||
|
||||
/* iomux and setup of i2c */ |
||||
board_early_init_f(); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* DDR initialization */ |
||||
spl_dram_init(); |
||||
|
||||
/* Clear the BSS. */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
} |
||||
#endif |
||||
@ -0,0 +1,346 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc. |
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com> |
||||
* |
||||
* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) |
||||
* Author: Markus Niebel <markus.niebel@tq-group.com> |
||||
* |
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/imx-common/boot_mode.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
|
||||
#include <common.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <libfdt.h> |
||||
#include <malloc.h> |
||||
#include <i2c.h> |
||||
#include <micrel.h> |
||||
#include <miiphy.h> |
||||
#include <mmc.h> |
||||
#include <netdev.h> |
||||
|
||||
#include "tqma6_bb.h" |
||||
|
||||
/* UART */ |
||||
#define UART4_PAD_CTRL ( \ |
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
) |
||||
|
||||
static iomux_v3_cfg_t const uart4_pads[] = { |
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL), |
||||
}; |
||||
|
||||
static void setup_iomuxc_uart4(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
||||
} |
||||
|
||||
/* MMC */ |
||||
#define USDHC2_PAD_CTRL ( \ |
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST \
|
||||
) |
||||
|
||||
#define USDHC2_CLK_PAD_CTRL ( \ |
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST \
|
||||
) |
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = { |
||||
NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL), |
||||
|
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */ |
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */ |
||||
}; |
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) |
||||
#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) |
||||
|
||||
static struct fsl_esdhc_cfg usdhc2_cfg = { |
||||
.esdhc_base = USDHC2_BASE_ADDR, |
||||
.max_bus_width = 4, |
||||
}; |
||||
|
||||
int tqma6_bb_board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret = 0; |
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR) |
||||
ret = !gpio_get_value(USDHC2_CD_GPIO); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int tqma6_bb_board_mmc_getwp(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret = 0; |
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR) |
||||
ret = gpio_get_value(USDHC2_WP_GPIO); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int tqma6_bb_board_mmc_init(bd_t *bis) |
||||
{ |
||||
int ret; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
||||
|
||||
ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd"); |
||||
if (!ret) |
||||
gpio_direction_input(USDHC2_CD_GPIO); |
||||
ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp"); |
||||
if (!ret) |
||||
gpio_direction_input(USDHC2_WP_GPIO); |
||||
|
||||
usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
||||
if(fsl_esdhc_initialize(bis, &usdhc2_cfg)) |
||||
puts("WARNING: failed to initialize SD\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ethernet */ |
||||
#define ENET_PAD_CTRL ( \ |
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
) |
||||
|
||||
static iomux_v3_cfg_t const enet_pads[] = { |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL), |
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL), |
||||
|
||||
/* ENET1 reset */ |
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL), |
||||
/* ENET1 interrupt */ |
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL), |
||||
}; |
||||
|
||||
#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8) |
||||
|
||||
static void setup_iomuxc_enet(void) |
||||
{ |
||||
int ret; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
||||
|
||||
/* Reset LAN8720 PHY */ |
||||
ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); |
||||
if (!ret) |
||||
gpio_direction_output(ENET_PHY_RESET_GPIO , 0); |
||||
udelay(1000); |
||||
gpio_set_value(ENET_PHY_RESET_GPIO, 1); |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return cpu_eth_init(bis); |
||||
} |
||||
|
||||
/* GPIO */ |
||||
#define GPIO_PAD_CTRL ( \ |
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
) |
||||
|
||||
#define GPIO_OD_PAD_CTRL ( \ |
||||
PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_PUE | \
|
||||
PAD_CTL_ODE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_SLOW \
|
||||
) |
||||
|
||||
static iomux_v3_cfg_t const gpio_pads[] = { |
||||
/* USB_H_PWR */ |
||||
NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL), |
||||
/* USB_OTG_PWR */ |
||||
NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL), |
||||
/* PCIE_RST */ |
||||
NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL), |
||||
/* UART1_PWRON */ |
||||
NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL), |
||||
/* UART2_PWRON */ |
||||
NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL), |
||||
/* UART3_PWRON */ |
||||
NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL), |
||||
}; |
||||
|
||||
#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0) |
||||
#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22) |
||||
#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7) |
||||
#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8) |
||||
#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10) |
||||
#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12) |
||||
|
||||
static void gpio_init(void) |
||||
{ |
||||
int ret; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); |
||||
|
||||
ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(GPIO_USB_H_PWR, 1); |
||||
ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(GPIO_USB_OTG_PWR, 1); |
||||
ret = gpio_request(GPIO_PCIE_RST, "pcie-reset"); |
||||
if (!ret) |
||||
gpio_direction_output(GPIO_PCIE_RST, 1); |
||||
ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(GPIO_UART1_PWRON, 0); |
||||
ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(GPIO_UART2_PWRON, 0); |
||||
ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(GPIO_UART3_PWRON, 0); |
||||
} |
||||
|
||||
void tqma6_iomuxc_spi(void) |
||||
{ |
||||
/* No SPI on this baseboard */ |
||||
} |
||||
|
||||
int tqma6_bb_board_early_init_f(void) |
||||
{ |
||||
setup_iomuxc_uart4(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int tqma6_bb_board_init(void) |
||||
{ |
||||
setup_iomuxc_enet(); |
||||
|
||||
gpio_init(); |
||||
|
||||
/* Turn the UART-couplers on one-after-another */ |
||||
gpio_set_value(GPIO_UART1_PWRON, 1); |
||||
mdelay(10); |
||||
gpio_set_value(GPIO_UART2_PWRON, 1); |
||||
mdelay(10); |
||||
gpio_set_value(GPIO_UART3_PWRON, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int tqma6_bb_board_late_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
const char *tqma6_bb_get_boardname(void) |
||||
{ |
||||
return "WRU-IV"; |
||||
} |
||||
|
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
||||
/* 8 bit bus width */ |
||||
{"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
||||
{ NULL, 0 }, |
||||
}; |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
add_board_boot_modes(board_boot_modes); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0) |
||||
#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22) |
||||
|
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(WRU4_USB_H1_PWR, 1); |
||||
|
||||
ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr"); |
||||
if (!ret) |
||||
gpio_direction_output(WRU4_USB_OTG_PWR, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_ehci_power(int port, int on) |
||||
{ |
||||
if (port) |
||||
gpio_set_value(WRU4_USB_OTG_PWR, on); |
||||
else |
||||
gpio_set_value(WRU4_USB_H1_PWR, on); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Device Tree Support |
||||
*/ |
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) |
||||
void tqma6_bb_ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
/* TBD */ |
||||
} |
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ |
||||
@ -1,6 +1,9 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_CGTQMX6EVAL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" |
||||
CONFIG_CMD_NET=y |
||||
CONFIG_DM=y |
||||
CONFIG_DM_THERMAL=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
|
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_MX6QSABREAUTO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q" |
||||
CONFIG_SPI_FLASH=y |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL" |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_MX6UL_14X14_EVK=y |
||||
CONFIG_SPL=y |
||||
@ -0,0 +1,13 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_TARGET_TQMA6=y |
||||
CONFIG_TQMA6S=y |
||||
CONFIG_WRU4=y |
||||
CONFIG_CMD_SETEXPR=y |
||||
CONFIG_CMD_NET=y |
||||
CONFIG_AUTOBOOT_KEYED=y |
||||
CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" |
||||
CONFIG_AUTOBOOT_ENCRYPTION=y |
||||
CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" |
||||
CONFIG_PCA9551_LED=y |
||||
CONFIG_SPI_FLASH=y |
||||
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc. |
||||
* Fabio Estevam <fabio.estevam@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <i2c.h> |
||||
#include <power/pmic.h> |
||||
#include <power/max77696_pmic.h> |
||||
|
||||
int power_max77696_init(unsigned char bus) |
||||
{ |
||||
static const char name[] = "MAX77696"; |
||||
struct pmic *p = pmic_alloc(); |
||||
|
||||
if (!p) { |
||||
printf("%s: POWER allocation error!\n", __func__); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
p->name = name; |
||||
p->interface = PMIC_I2C; |
||||
p->number_of_regs = PMIC_NUM_OF_REGS; |
||||
p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR; |
||||
p->hw.i2c.tx_num = 1; |
||||
p->bus = bus; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,227 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the Freescale i.MX6UL 14x14 EVK board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __MX6UL_14X14_EVK_CONFIG_H |
||||
#define __MX6UL_14X14_EVK_CONFIG_H |
||||
|
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <linux/sizes.h> |
||||
#include "mx6_common.h" |
||||
#include <asm/imx-common/gpio.h> |
||||
|
||||
/* SPL options */ |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_MMC_SUPPORT |
||||
#define CONFIG_SPL_FAT_SUPPORT |
||||
#include "imx6_spl.h" |
||||
|
||||
#define CONFIG_MX6 |
||||
#define CONFIG_ROM_UNIFIED_SECTIONS |
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
|
||||
#define CONFIG_CMD_FUSE |
||||
#ifdef CONFIG_CMD_FUSE |
||||
#define CONFIG_MXC_OCOTP |
||||
#endif |
||||
|
||||
/* MMC Configs */ |
||||
#ifdef CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
||||
|
||||
/* NAND pin conflicts with usdhc2 */ |
||||
#ifdef CONFIG_NAND_MXS |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
#else |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2 |
||||
#endif |
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ |
||||
#endif |
||||
|
||||
#undef CONFIG_BOOTM_NETBSD |
||||
#undef CONFIG_BOOTM_PLAN9 |
||||
#undef CONFIG_BOOTM_RTEMS |
||||
|
||||
#undef CONFIG_CMD_EXPORTENV |
||||
#undef CONFIG_CMD_IMPORTENV |
||||
|
||||
/* I2C configs */ |
||||
#define CONFIG_CMD_I2C |
||||
#ifdef CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#endif |
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_512M |
||||
|
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx6ul-14x14-evk.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
#define CONFIG_CMD_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_STACKSIZE SZ_128K |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_ENV_SIZE SZ_8K |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ |
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ |
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_BMODE |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
#define CONFIG_FSL_QSPI |
||||
#ifdef CONFIG_FSL_QSPI |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SPI_FLASH_BAR |
||||
#define CONFIG_SF_DEFAULT_BUS 0 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
#define FSL_QSPI_FLASH_NUM 1 |
||||
#define FSL_QSPI_FLASH_SIZE SZ_32M |
||||
#endif |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_CMD_USB |
||||
#ifdef CONFIG_CMD_USB |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX6 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
#endif |
||||
|
||||
#define CONFIG_IMX6_THERMAL |
||||
|
||||
#endif |
||||
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_TQMA6_WRU4_H |
||||
#define __CONFIG_TQMA6_WRU4_H |
||||
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6s-wru4.dtb" |
||||
|
||||
/* DTT sensors */ |
||||
#define CONFIG_DTT_SENSORS { 0, 1 } |
||||
#define CONFIG_SYS_DTT_BUS_NUM 2 |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_FEC_XCV_TYPE RMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 0x01 |
||||
#define CONFIG_PHY_SMSC |
||||
|
||||
/* UART */ |
||||
#define CONFIG_MXC_UART_BASE UART4_BASE |
||||
#define CONFIG_CONSOLE_DEV "ttymxc3" |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/* Watchdog */ |
||||
#define CONFIG_HW_WATCHDOG |
||||
#define CONFIG_IMX_WATCHDOG |
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 |
||||
|
||||
/* Config on-board RTC */ |
||||
#define CONFIG_RTC_DS1337 |
||||
#define CONFIG_SYS_RTC_BUS_NUM 2 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
/* Turn off RTC square-wave output to save battery */ |
||||
#define CONFIG_SYS_RTC_DS1337_NOOSC |
||||
#define CONFIG_CMD_DATE |
||||
|
||||
#define CONFIG_CMD_GPIO |
||||
|
||||
/* LED */ |
||||
#define CONFIG_CMD_LED |
||||
#define CONFIG_STATUS_LED |
||||
#define CONFIG_BOARD_SPECIFIC_LED |
||||
#define STATUS_LED_BIT 0 |
||||
#define STATUS_LED_STATE STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT1 1 |
||||
#define STATUS_LED_STATE1 STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT2 2 |
||||
#define STATUS_LED_STATE2 STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT3 3 |
||||
#define STATUS_LED_STATE3 STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT4 4 |
||||
#define STATUS_LED_STATE4 STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD4 (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT5 5 |
||||
#define STATUS_LED_STATE5 STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD5 (CONFIG_SYS_HZ / 2) |
||||
|
||||
/* Bootcounter */ |
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_BOOTCOUNT_BE |
||||
|
||||
#endif /* __CONFIG_TQMA6_WRU4_H */ |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc. |
||||
* Fabio Estevam <fabio.estevam@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __MAX77696_PMIC_H__ |
||||
#define __MAX77696_PMIC_H__ |
||||
|
||||
#define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C |
||||
|
||||
enum { |
||||
L01_CNFG1 = 0x43, |
||||
L01_CNFG2, |
||||
L02_CNFG1, |
||||
L02_CNFG2, |
||||
L03_CNFG1, |
||||
L03_CNFG2, |
||||
L04_CNFG1, |
||||
L04_CNFG2, |
||||
L05_CNFG1, |
||||
L05_CNFG2, |
||||
L06_CNFG1, |
||||
L06_CNFG2, |
||||
L07_CNFG1, |
||||
L07_CNFG2, |
||||
L08_CNFG1, |
||||
L08_CNFG2, |
||||
L09_CNFG1, |
||||
L09_CNFG2, |
||||
L10_CNFG1, |
||||
L10_CNFG2, |
||||
LDO_INT1, |
||||
LDO_INT2, |
||||
LDO_INT1M, |
||||
LDO_INT2M, |
||||
LDO_CNFG3, |
||||
SW1_CNTRL, |
||||
SW2_CNTRL, |
||||
SW3_CNTRL, |
||||
SW4_CNTRL, |
||||
EPDCNFG, |
||||
EPDINTS, |
||||
EPDINT, |
||||
EPDINTM, |
||||
EPDVCOM, |
||||
EPDVEE, |
||||
EPDVNEG, |
||||
EPDVPOS, |
||||
EPDVDDH, |
||||
EPDSEQ, |
||||
EPDOKINTS, |
||||
CID = 0x9c, |
||||
PMIC_NUM_OF_REGS, |
||||
}; |
||||
|
||||
int power_max77696_init(unsigned char bus); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue