These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
10 years ago
committed by
Tom Rini
parent
93b25c0813
commit
7a2c1b13d7
@ -1,12 +0,0 @@ |
|||||||
if TARGET_OPENRD |
|
||||||
|
|
||||||
config SYS_BOARD |
|
||||||
default "openrd" |
|
||||||
|
|
||||||
config SYS_VENDOR |
|
||||||
default "Marvell" |
|
||||||
|
|
||||||
config SYS_CONFIG_NAME |
|
||||||
default "openrd" |
|
||||||
|
|
||||||
endif |
|
||||||
@ -1,12 +0,0 @@ |
|||||||
OPENRD BOARD |
|
||||||
M: Prafulla Wadaskar <prafulla@marvell.com> |
|
||||||
S: Maintained |
|
||||||
F: board/Marvell/openrd/ |
|
||||||
F: include/configs/openrd.h |
|
||||||
F: configs/openrd_base_defconfig |
|
||||||
|
|
||||||
OPENRD_CLIENT BOARD |
|
||||||
#M: - |
|
||||||
S: Maintained |
|
||||||
F: configs/openrd_client_defconfig |
|
||||||
F: configs/openrd_ultimate_defconfig |
|
||||||
@ -1,14 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2009
|
|
||||||
# Net Insight <www.netinsight.net>
|
|
||||||
# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
|
|
||||||
#
|
|
||||||
# Based on sheevaplug:
|
|
||||||
# (C) Copyright 2009
|
|
||||||
# Marvell Semiconductor <www.marvell.com>
|
|
||||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y := openrd.o
|
|
||||||
@ -1,152 +0,0 @@ |
|||||||
# |
|
||||||
# (C) Copyright 2009 |
|
||||||
# Marvell Semiconductor <www.marvell.com> |
|
||||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
|
||||||
# |
|
||||||
# SPDX-License-Identifier: GPL-2.0+ |
|
||||||
# |
|
||||||
# Refer doc/README.kwbimage for more details about how-to configure |
|
||||||
# and create kirkwood boot image |
|
||||||
# |
|
||||||
|
|
||||||
# Boot Media configurations |
|
||||||
BOOT_FROM nand |
|
||||||
NAND_ECC_MODE default |
|
||||||
NAND_PAGE_SIZE 0x0800 |
|
||||||
|
|
||||||
# SOC registers configuration using bootrom header extension |
|
||||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
|
||||||
|
|
||||||
# Configure RGMII-0 interface pad voltage to 1.8V |
|
||||||
DATA 0xFFD100e0 0x1b1b1b9b |
|
||||||
|
|
||||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
|
||||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
|
||||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) |
|
||||||
# bit23-14: zero |
|
||||||
# bit24: 1= enable exit self refresh mode on DDR access |
|
||||||
# bit25: 1 required |
|
||||||
# bit29-26: zero |
|
||||||
# bit31-30: 01 |
|
||||||
|
|
||||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low |
|
||||||
# bit 4: 0=addr/cmd in smame cycle |
|
||||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX |
|
||||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd |
|
||||||
# bit14: 0=input buffer always powered up |
|
||||||
# bit18: 1=cpu lock transaction enabled |
|
||||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
|
||||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
|
||||||
# bit30-28: 3 required |
|
||||||
# bit31: 0=no additional STARTBURST delay |
|
||||||
|
|
||||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) |
|
||||||
# bit3-0: TRAS lsbs |
|
||||||
# bit7-4: TRCD |
|
||||||
# bit11- 8: TRP |
|
||||||
# bit15-12: TWR |
|
||||||
# bit19-16: TWTR |
|
||||||
# bit20: TRAS msb |
|
||||||
# bit23-21: 0x0 |
|
||||||
# bit27-24: TRRD |
|
||||||
# bit31-28: TRTP |
|
||||||
|
|
||||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) |
|
||||||
# bit6-0: TRFC |
|
||||||
# bit8-7: TR2R |
|
||||||
# bit10-9: TR2W |
|
||||||
# bit12-11: TW2W |
|
||||||
# bit31-13: zero required |
|
||||||
|
|
||||||
DATA 0xFFD01410 0x000000cc # DDR Address Control |
|
||||||
# bit1-0: 00, Cs0width=x8 |
|
||||||
# bit3-2: 11, Cs0size=1Gb |
|
||||||
# bit5-4: 00, Cs1width=x8 |
|
||||||
# bit7-6: 11, Cs1size=1Gb |
|
||||||
# bit9-8: 00, Cs2width=nonexistent |
|
||||||
# bit11-10: 00, Cs2size =nonexistent |
|
||||||
# bit13-12: 00, Cs3width=nonexistent |
|
||||||
# bit15-14: 00, Cs3size =nonexistent |
|
||||||
# bit16: 0, Cs0AddrSel |
|
||||||
# bit17: 0, Cs1AddrSel |
|
||||||
# bit18: 0, Cs2AddrSel |
|
||||||
# bit19: 0, Cs3AddrSel |
|
||||||
# bit31-20: 0 required |
|
||||||
|
|
||||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
|
||||||
# bit0: 0, OpenPage enabled |
|
||||||
# bit31-1: 0 required |
|
||||||
|
|
||||||
DATA 0xFFD01418 0x00000000 # DDR Operation |
|
||||||
# bit3-0: 0x0, DDR cmd |
|
||||||
# bit31-4: 0 required |
|
||||||
|
|
||||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode |
|
||||||
# bit2-0: 2, BurstLen=2 required |
|
||||||
# bit3: 0, BurstType=0 required |
|
||||||
# bit6-4: 4, CL=5 |
|
||||||
# bit7: 0, TestMode=0 normal |
|
||||||
# bit8: 0, DLL reset=0 normal |
|
||||||
# bit11-9: 6, auto-precharge write recovery ???????????? |
|
||||||
# bit12: 0, PD must be zero |
|
||||||
# bit31-13: 0 required |
|
||||||
|
|
||||||
DATA 0xFFD01420 0x00000042 # DDR Extended Mode |
|
||||||
# bit0: 0, DDR DLL enabled |
|
||||||
# bit1: 1, DDR drive strength reduced |
|
||||||
# bit2: 0, DDR ODT control lsd (disabled) |
|
||||||
# bit5-3: 000, required |
|
||||||
# bit6: 1, DDR ODT control msb, (disabled) |
|
||||||
# bit9-7: 000, required |
|
||||||
# bit10: 0, differential DQS enabled |
|
||||||
# bit11: 0, required |
|
||||||
# bit12: 0, DDR output buffer enabled |
|
||||||
# bit31-13: 0 required |
|
||||||
|
|
||||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
|
||||||
# bit2-0: 111, required |
|
||||||
# bit3 : 1 , MBUS Burst Chop disabled |
|
||||||
# bit6-4: 111, required |
|
||||||
# bit7 : 0 |
|
||||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz |
|
||||||
# bit9 : 0 , no half clock cycle addition to dataout |
|
||||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
|
||||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
|
||||||
# bit15-12: 1111 required |
|
||||||
# bit31-16: 0 required |
|
||||||
|
|
||||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) |
|
||||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) |
|
||||||
|
|
||||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
|
||||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
|
||||||
# bit0: 1, Window enabled |
|
||||||
# bit1: 0, Write Protect disabled |
|
||||||
# bit3-2: 00, CS0 hit selected |
|
||||||
# bit23-4: ones, required |
|
||||||
# bit31-24: 0x0F, Size (i.e. 256MB) |
|
||||||
|
|
||||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb |
|
||||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 |
|
||||||
|
|
||||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
|
||||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
|
||||||
|
|
||||||
DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) |
|
||||||
# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 |
|
||||||
# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 |
|
||||||
# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. |
|
||||||
# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. |
|
||||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
|
||||||
|
|
||||||
DATA 0xFFD0149C 0x0000E40f # CPU ODT Control |
|
||||||
# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 |
|
||||||
# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm |
|
||||||
# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm |
|
||||||
# bit14: 1, M_STARTBURST_IN ODT: Enabled |
|
||||||
# bit15: 1, DDR IO ODT Unit: Use ODT block |
|
||||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
|
||||||
#bit0=1, enable DDR init upon this register write |
|
||||||
|
|
||||||
# End of Header extension |
|
||||||
DATA 0x0 0x0 |
|
||||||
@ -1,161 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2009 |
|
||||||
* Net Insight <www.netinsight.net> |
|
||||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
|
||||||
* |
|
||||||
* Based on sheevaplug.c: |
|
||||||
* (C) Copyright 2009 |
|
||||||
* Marvell Semiconductor <www.marvell.com> |
|
||||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <miiphy.h> |
|
||||||
#include <asm/arch/cpu.h> |
|
||||||
#include <asm/arch/soc.h> |
|
||||||
#include <asm/arch/mpp.h> |
|
||||||
#include "openrd.h" |
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR; |
|
||||||
|
|
||||||
int board_early_init_f(void) |
|
||||||
{ |
|
||||||
/*
|
|
||||||
* default gpio configuration |
|
||||||
* There are maximum 64 gpios controlled through 2 sets of registers |
|
||||||
* the below configuration configures mainly initial LED status |
|
||||||
*/ |
|
||||||
mvebu_config_gpio(OPENRD_OE_VAL_LOW, |
|
||||||
OPENRD_OE_VAL_HIGH, |
|
||||||
OPENRD_OE_LOW, OPENRD_OE_HIGH); |
|
||||||
|
|
||||||
/* Multi-Purpose Pins Functionality configuration */ |
|
||||||
static const u32 kwmpp_config[] = { |
|
||||||
MPP0_NF_IO2, |
|
||||||
MPP1_NF_IO3, |
|
||||||
MPP2_NF_IO4, |
|
||||||
MPP3_NF_IO5, |
|
||||||
MPP4_NF_IO6, |
|
||||||
MPP5_NF_IO7, |
|
||||||
MPP6_SYSRST_OUTn, |
|
||||||
MPP7_GPO, |
|
||||||
MPP8_TW_SDA, |
|
||||||
MPP9_TW_SCK, |
|
||||||
MPP10_UART0_TXD, |
|
||||||
MPP11_UART0_RXD, |
|
||||||
MPP12_SD_CLK, |
|
||||||
MPP13_SD_CMD, /* Alt UART1_TXD */ |
|
||||||
MPP14_SD_D0, /* Alt UART1_RXD */ |
|
||||||
MPP15_SD_D1, |
|
||||||
MPP16_SD_D2, |
|
||||||
MPP17_SD_D3, |
|
||||||
MPP18_NF_IO0, |
|
||||||
MPP19_NF_IO1, |
|
||||||
MPP20_GE1_0, |
|
||||||
MPP21_GE1_1, |
|
||||||
MPP22_GE1_2, |
|
||||||
MPP23_GE1_3, |
|
||||||
MPP24_GE1_4, |
|
||||||
MPP25_GE1_5, |
|
||||||
MPP26_GE1_6, |
|
||||||
MPP27_GE1_7, |
|
||||||
MPP28_GPIO, |
|
||||||
MPP29_TSMP9, |
|
||||||
MPP30_GE1_10, |
|
||||||
MPP31_GE1_11, |
|
||||||
MPP32_GE1_12, |
|
||||||
MPP33_GE1_13, |
|
||||||
MPP34_GPIO, /* UART1 / SD sel */ |
|
||||||
MPP35_TDM_CH0_TX_QL, |
|
||||||
MPP36_TDM_SPI_CS1, |
|
||||||
MPP37_TDM_CH2_TX_QL, |
|
||||||
MPP38_TDM_CH2_RX_QL, |
|
||||||
MPP39_AUDIO_I2SBCLK, |
|
||||||
MPP40_AUDIO_I2SDO, |
|
||||||
MPP41_AUDIO_I2SLRC, |
|
||||||
MPP42_AUDIO_I2SMCLK, |
|
||||||
MPP43_AUDIO_I2SDI, |
|
||||||
MPP44_AUDIO_EXTCLK, |
|
||||||
MPP45_TDM_PCLK, |
|
||||||
MPP46_TDM_FS, |
|
||||||
MPP47_TDM_DRX, |
|
||||||
MPP48_TDM_DTX, |
|
||||||
MPP49_TDM_CH0_RX_QL, |
|
||||||
0 |
|
||||||
}; |
|
||||||
|
|
||||||
kirkwood_mpp_conf(kwmpp_config, NULL); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
int board_init(void) |
|
||||||
{ |
|
||||||
/*
|
|
||||||
* arch number of board |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_BOARD_IS_OPENRD_BASE) |
|
||||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; |
|
||||||
#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) |
|
||||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; |
|
||||||
#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) |
|
||||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; |
|
||||||
#endif |
|
||||||
|
|
||||||
/* adress of boot parameters */ |
|
||||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
#ifdef CONFIG_RESET_PHY_R |
|
||||||
/* Configure and enable MV88E1116/88E1121 PHY */ |
|
||||||
void mv_phy_init(char *name) |
|
||||||
{ |
|
||||||
u16 reg; |
|
||||||
u16 devadr; |
|
||||||
|
|
||||||
if (miiphy_set_current_dev(name)) |
|
||||||
return; |
|
||||||
|
|
||||||
/* command to read PHY dev address */ |
|
||||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { |
|
||||||
printf("Err..%s could not read PHY dev address\n", |
|
||||||
__FUNCTION__); |
|
||||||
return; |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable RGMII delay on Tx and Rx for CPU port |
|
||||||
* Ref: sec 4.7.2 of chip datasheet |
|
||||||
*/ |
|
||||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); |
|
||||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); |
|
||||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
|
||||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); |
|
||||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); |
|
||||||
|
|
||||||
/* reset the phy */ |
|
||||||
miiphy_reset(name, devadr); |
|
||||||
|
|
||||||
printf(PHY_NO" Initialized on %s\n", name); |
|
||||||
} |
|
||||||
|
|
||||||
void reset_phy(void) |
|
||||||
{ |
|
||||||
mv_phy_init("egiga0"); |
|
||||||
|
|
||||||
#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT |
|
||||||
/* Kirkwood ethernet driver is written with the assumption that in case
|
|
||||||
* of multiple PHYs, their addresses are consecutive. But unfortunately |
|
||||||
* in case of OpenRD-Client, PHY addresses are not consecutive.*/ |
|
||||||
miiphy_write("egiga1", 0xEE, 0xEE, 24); |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ |
|
||||||
defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) |
|
||||||
/* configure and initialize both PHY's */ |
|
||||||
mv_phy_init("egiga1"); |
|
||||||
#endif |
|
||||||
} |
|
||||||
#endif /* CONFIG_RESET_PHY_R */ |
|
||||||
@ -1,30 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2009 |
|
||||||
* Net Insight <www.netinsight.net> |
|
||||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
|
||||||
* |
|
||||||
* Based on sheevaplug.h: |
|
||||||
* (C) Copyright 2009 |
|
||||||
* Marvell Semiconductor <www.marvell.com> |
|
||||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __OPENRD_BASE_H |
|
||||||
#define __OPENRD_BASE_H |
|
||||||
|
|
||||||
#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ |
|
||||||
#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ |
|
||||||
#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ |
|
||||||
#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ |
|
||||||
|
|
||||||
/* PHY related */ |
|
||||||
#define MV88E1116_LED_FCTRL_REG 10 |
|
||||||
#define MV88E1116_CPRSP_CR3_REG 21 |
|
||||||
#define MV88E1116_MAC_CTRL_REG 21 |
|
||||||
#define MV88E1116_PGADR_REG 22 |
|
||||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) |
|
||||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) |
|
||||||
|
|
||||||
#endif /* __OPENRD_BASE_H */ |
|
||||||
@ -1,7 +0,0 @@ |
|||||||
CONFIG_ARM=y |
|
||||||
CONFIG_KIRKWOOD=y |
|
||||||
CONFIG_TARGET_OPENRD=y |
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" |
|
||||||
# CONFIG_CMD_IMLS is not set |
|
||||||
# CONFIG_CMD_FLASH is not set |
|
||||||
# CONFIG_CMD_SETEXPR is not set |
|
||||||
@ -1,7 +0,0 @@ |
|||||||
CONFIG_ARM=y |
|
||||||
CONFIG_KIRKWOOD=y |
|
||||||
CONFIG_TARGET_OPENRD=y |
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" |
|
||||||
# CONFIG_CMD_IMLS is not set |
|
||||||
# CONFIG_CMD_FLASH is not set |
|
||||||
# CONFIG_CMD_SETEXPR is not set |
|
||||||
@ -1,7 +0,0 @@ |
|||||||
CONFIG_ARM=y |
|
||||||
CONFIG_KIRKWOOD=y |
|
||||||
CONFIG_TARGET_OPENRD=y |
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" |
|
||||||
# CONFIG_CMD_IMLS is not set |
|
||||||
# CONFIG_CMD_FLASH is not set |
|
||||||
# CONFIG_CMD_SETEXPR is not set |
|
||||||
@ -1,137 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2009 |
|
||||||
* Net Insight <www.netinsight.net> |
|
||||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
|
||||||
* |
|
||||||
* Based on sheevaplug.h: |
|
||||||
* (C) Copyright 2009 |
|
||||||
* Marvell Semiconductor <www.marvell.com> |
|
||||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef _CONFIG_OPENRD_H |
|
||||||
#define _CONFIG_OPENRD_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* Version number information |
|
||||||
*/ |
|
||||||
#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE |
|
||||||
# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" |
|
||||||
#else |
|
||||||
# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT |
|
||||||
# define CONFIG_IDENT_STRING "\nOpenRD-Client" |
|
||||||
# else |
|
||||||
# ifdef CONFIG_BOARD_IS_OPENRD_BASE |
|
||||||
# define CONFIG_IDENT_STRING "\nOpenRD-Base" |
|
||||||
# else |
|
||||||
# error Unknown OpenRD board specified |
|
||||||
# endif |
|
||||||
# endif |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ |
|
||||||
#define CONFIG_KW88F6281 1 /* SOC Name */ |
|
||||||
#define CONFIG_MACH_OPENRD_BASE /* Machine type */ |
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Commands configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
|
||||||
#define CONFIG_SYS_MVFS |
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
#define CONFIG_CMD_ENV |
|
||||||
#define CONFIG_CMD_MII |
|
||||||
#define CONFIG_CMD_MMC |
|
||||||
#define CONFIG_CMD_NAND |
|
||||||
#define CONFIG_CMD_PING |
|
||||||
#define CONFIG_CMD_USB |
|
||||||
#define CONFIG_CMD_IDE |
|
||||||
|
|
||||||
/*
|
|
||||||
* mv-common.h should be defined after CMD configs since it used them |
|
||||||
* to enable certain macros |
|
||||||
*/ |
|
||||||
#include "mv-common.h" |
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment variables configurations |
|
||||||
*/ |
|
||||||
#ifdef CONFIG_CMD_NAND |
|
||||||
#define CONFIG_ENV_IS_IN_NAND 1 |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
|
||||||
#else |
|
||||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ |
|
||||||
#endif |
|
||||||
/*
|
|
||||||
* max 4k env size is enough, but in case of nand |
|
||||||
* it has to be rounded to sector size |
|
||||||
*/ |
|
||||||
#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
|
||||||
#define CONFIG_ENV_ADDR 0x60000 |
|
||||||
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ |
|
||||||
/*
|
|
||||||
* Environment is right behind U-Boot in flash. Make sure U-Boot |
|
||||||
* doesn't grow into the environment area. |
|
||||||
*/ |
|
||||||
#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET |
|
||||||
|
|
||||||
/*
|
|
||||||
* Default environment variables |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ |
|
||||||
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
|
|
||||||
"${x_bootcmd_usb}; bootm 0x6400000;" |
|
||||||
|
|
||||||
#define MTDIDS_DEFAULT "nand0=nand_mtd" |
|
||||||
#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ |
|
||||||
"0x400000@0x100000(uImage),"\
|
|
||||||
"0x1fb00000@0x500000(rootfs)" |
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ |
|
||||||
"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
|
|
||||||
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
|
|
||||||
"x_bootcmd_usb=usb start\0" \
|
|
||||||
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
|
|
||||||
"mtdids="MTDIDS_DEFAULT"\0" \
|
|
||||||
"mtdparts="MTDPARTS_DEFAULT"\0" |
|
||||||
|
|
||||||
/*
|
|
||||||
* Ethernet Driver configuration |
|
||||||
*/ |
|
||||||
#ifdef CONFIG_CMD_NET |
|
||||||
# ifdef CONFIG_BOARD_IS_OPENRD_BASE |
|
||||||
# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
|
||||||
# else |
|
||||||
# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ |
|
||||||
# endif |
|
||||||
# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE |
|
||||||
# define CONFIG_PHY_BASE_ADR 0x0 |
|
||||||
# define PHY_NO "88E1121" |
|
||||||
# else |
|
||||||
# define CONFIG_PHY_BASE_ADR 0x8 |
|
||||||
# define PHY_NO "88E1116" |
|
||||||
# endif |
|
||||||
#endif /* CONFIG_CMD_NET */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* SATA Driver configuration |
|
||||||
*/ |
|
||||||
#ifdef CONFIG_MVSATA_IDE |
|
||||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
|
||||||
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET |
|
||||||
#endif /*CONFIG_MVSATA_IDE*/ |
|
||||||
|
|
||||||
#ifdef CONFIG_CMD_MMC |
|
||||||
#define CONFIG_MMC |
|
||||||
#define CONFIG_GENERIC_MMC |
|
||||||
#define CONFIG_MVEBU_MMC |
|
||||||
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE |
|
||||||
#endif /* CONFIG_CMD_MMC */ |
|
||||||
|
|
||||||
#endif /* _CONFIG_OPENRD_BASE_H */ |
|
||||||
Loading…
Reference in new issue