T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.
T1040QDS board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
— SATA 2.0
— Aurora debug with dedicated connectors
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
— Two type A ports with 5V@1.5A per port.
— Second port can be converted to OTG mini-AB
- SDHC
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
— Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
master
Prabhakar Kushwaha
12 years ago
committed by
York Sun
parent
0dd38a35f4
commit
7d436078fe
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS))
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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Overview |
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-------- |
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The T1040QDS is a Freescale reference board that hosts the T1040 SoC |
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(and variants). |
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T1040 SoC Overview |
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------------------ |
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The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA |
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processor cores with high-performance data path acceleration architecture |
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and network peripheral interfaces required for networking & telecommunications. |
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The T1040/T1042 SoC includes the following function and features: |
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- Four e5500 cores, each with a private 256 KB L2 cache |
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- 256 KB shared L3 CoreNet platform cache (CPC) |
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- Interconnect CoreNet platform |
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- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving |
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support |
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration |
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for the following functions: |
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- Packet parsing, classification, and distribution |
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- Queue management for scheduling, packet sequencing, and congestion |
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management |
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- Cryptography Acceleration (SEC 5.0) |
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- RegEx Pattern Matching Acceleration (PME 2.2) |
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- IEEE Std 1588 support |
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- Hardware buffer management for buffer allocation and deallocation |
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- Ethernet interfaces |
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- Integrated 8-port Gigabit Ethernet switch (T1040 only) |
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- Four 1 Gbps Ethernet controllers |
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- Two RGMII interfaces or one RGMII and one MII interfaces |
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- High speed peripheral interfaces |
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- Four PCI Express 2.0 controllers running at up to 5 GHz |
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- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation |
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- Upto two QSGMII interface |
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- Upto six SGMII interface supporting 1000 Mbps |
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- One SGMII interface supporting upto 2500 Mbps |
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- Additional peripheral interfaces |
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- Two USB 2.0 controllers with integrated PHY |
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- SD/eSDHC/eMMC |
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- eSPI controller |
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- Four I2C controllers |
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- Four UARTs |
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- Four GPIO controllers |
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- Integrated flash controller (IFC) |
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- LCD and HDMI interface (DIU) with 12 bit dual data rate |
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- TDM interface |
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- Multicore programmable interrupt controller (PIC) |
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- Two 8-channel DMA engines |
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- Single source clocking implementation |
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- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) |
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T1040QDS board Overview |
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----------------------- |
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- SERDES Connections, 8 lanes supporting: |
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— PCI Express: supporting Gen 1 and Gen 2; |
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— SGMII |
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— QSGMII |
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— SATA 2.0 |
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— Aurora debug with dedicated connectors (T1040 only) |
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- DDR Controller |
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- Supports rates of up to 1600 MHz data-rate |
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- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. |
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-IFC/Local Bus |
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- NAND flash: 8-bit, async, up to 2GB. |
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- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB |
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- GASIC: Simple (minimal) target within Qixis FPGA |
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- PromJET rapid memory download support |
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- Ethernet |
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- Two on-board RGMII 10/100/1G ethernet ports. |
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- PHY #0 remains powered up during deep-sleep (T1040 only) |
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- QIXIS System Logic FPGA |
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- Clocks |
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- System and DDR clock (SYSCLK, “DDRCLK”) |
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- SERDES clocks |
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- Power Supplies |
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- Video |
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- DIU supports video at up to 1280x1024x32bpp |
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- USB |
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- Supports two USB 2.0 ports with integrated PHYs |
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— Two type A ports with 5V@1.5A per port. |
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— Second port can be converted to OTG mini-AB |
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- SDHC |
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- SDHC port connects directly to an adapter card slot, featuring: |
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- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC |
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— Supporting eMMC memory devices |
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- SPI |
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- On-board support of 3 different devices and sizes |
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- Other IO |
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- Two Serial ports |
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- ProfiBus port |
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- Four I2C ports |
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Memory map on T1040QDS |
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---------------------- |
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The addresses in brackets are physical addresses. |
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Start Address End Address Description Size |
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB |
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB |
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB |
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0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB |
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB |
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB |
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB |
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB |
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB |
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB |
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0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB |
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB |
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0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB |
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB |
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0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB |
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0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB |
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0x0_0000_0000 0x0_ffff_ffff DDR 2GB |
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NOR Flash memory Map on T1040QDS |
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-------------------------------- |
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Start End Definition Size |
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0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB |
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0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB |
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0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB |
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0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB |
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0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB |
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB |
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB |
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0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB |
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0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB |
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0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB |
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0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB |
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB |
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB |
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0xE8000000 0xE801FFFF RCW (current bank) 128KB |
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Various Software configurations/environment variables/commands |
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-------------------------------------------------------------- |
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The below commands apply to T1040QDS |
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1. U-boot environment variable hwconfig |
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The default hwconfig is: |
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hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: |
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dr_mode=host,phy_type=utmi |
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Note: For USB gadget set "dr_mode=peripheral" |
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2. FMAN Ucode versions |
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fsl_fman_ucode_t1040.bin |
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3. Switching to alternate bank |
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Commands for switching to alternate bank. |
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1. To change from vbank0 to vbank4 |
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=> qixis_reset altbank (it will boot using vbank4) |
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2.To change from vbank4 to vbank0 |
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=> qixis reset (it will boot using vbank0) |
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T1040 Personality |
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-------------------- |
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T1022 Personality |
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-------------------- |
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T1022 is a reduced personality of T1040 with less core/clusters. |
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T1042 Personality |
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-------------------- |
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T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit |
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Ethernet switch. Rest of the blocks are same as T1040 |
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@ -0,0 +1,117 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <hwconfig.h> |
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#include <asm/mmu.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/fsl_ddr_dimm_params.h> |
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#include <asm/fsl_law.h> |
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#include "ddr.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
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ulong ddr_freq; |
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if (ctrl_num > 2) { |
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printf("Not supported controller number %d\n", ctrl_num); |
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return; |
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} |
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if (!pdimm->n_ranks) |
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return; |
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pbsp = udimms[0]; |
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/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table. |
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*/ |
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ddr_freq = get_ddr_freq(0) / 1000000; |
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while (pbsp->datarate_mhz_high) { |
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if (pbsp->n_ranks == pdimm->n_ranks && |
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(pdimm->rank_density >> 30) >= pbsp->rank_gb) { |
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if (ddr_freq <= pbsp->datarate_mhz_high) { |
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popts->cpo_override = pbsp->cpo; |
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popts->write_data_delay = |
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pbsp->write_data_delay; |
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popts->clk_adjust = pbsp->clk_adjust; |
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popts->wrlvl_start = pbsp->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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popts->twot_en = pbsp->force_2t; |
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goto found; |
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} |
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pbsp_highest = pbsp; |
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} |
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pbsp++; |
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} |
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if (pbsp_highest) { |
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printf("Error: board specific timing not found\n"); |
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printf("for data rate %lu MT/s\n", ddr_freq); |
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printf("Trying to use the highest speed (%u) parameters\n", |
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pbsp_highest->datarate_mhz_high); |
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popts->cpo_override = pbsp_highest->cpo; |
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popts->write_data_delay = pbsp_highest->write_data_delay; |
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popts->clk_adjust = pbsp_highest->clk_adjust; |
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popts->wrlvl_start = pbsp_highest->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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popts->twot_en = pbsp_highest->force_2t; |
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} else { |
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panic("DIMM is not supported by this board"); |
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} |
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found: |
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " |
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"wrlvl_ctrl_3 0x%x\n", |
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
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pbsp->wrlvl_ctl_3); |
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 0; |
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/*
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* Write leveling override |
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*/ |
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popts->wrlvl_override = 1; |
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popts->wrlvl_sample = 0xf; |
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/*
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* rtt and rtt_wr override |
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*/ |
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popts->rtt_override = 0; |
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/* Enable ZQ calibration */ |
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popts->zq_en = 1; |
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/* DHC_EN =1, ODT = 75 Ohm */ |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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phys_size_t dram_size; |
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puts("Initializing....using SPD\n"); |
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dram_size = fsl_ddr_sdram(); |
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dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
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dram_size *= 0x100000; |
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puts(" DDR: "); |
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return dram_size; |
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} |
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@ -0,0 +1,50 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __DDR_H__ |
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#define __DDR_H__ |
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struct board_specific_parameters { |
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u32 n_ranks; |
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u32 datarate_mhz_high; |
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u32 rank_gb; |
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u32 clk_adjust; |
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u32 wrlvl_start; |
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u32 wrlvl_ctl_2; |
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u32 wrlvl_ctl_3; |
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u32 cpo; |
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u32 write_data_delay; |
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u32 force_2t; |
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}; |
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/*
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* These tables contain all valid speeds we want to override with board |
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* specific parameters. datarate_mhz_high values need to be in ascending order |
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* for each n_ranks group. |
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*/ |
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static const struct board_specific_parameters udimm0[] = { |
||||||
|
/*
|
||||||
|
* memory controller 0 |
||||||
|
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
||||||
|
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
||||||
|
*/ |
||||||
|
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
||||||
|
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, |
||||||
|
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, |
||||||
|
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, |
||||||
|
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
||||||
|
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
||||||
|
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
||||||
|
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
||||||
|
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
||||||
|
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
||||||
|
{} |
||||||
|
}; |
||||||
|
|
||||||
|
static const struct board_specific_parameters *udimms[] = { |
||||||
|
udimm0, |
||||||
|
}; |
||||||
|
#endif |
||||||
@ -0,0 +1,32 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <asm/fsl_law.h> |
||||||
|
#include <asm/mmu.h> |
||||||
|
|
||||||
|
struct law_entry law_table[] = { |
||||||
|
#ifndef CONFIG_SYS_NO_FLASH |
||||||
|
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||||
|
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||||
|
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
||||||
|
#endif |
||||||
|
#ifdef QIXIS_BASE_PHYS |
||||||
|
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||||
|
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||||
|
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), |
||||||
|
#endif |
||||||
|
}; |
||||||
|
|
||||||
|
int num_law_entries = ARRAY_SIZE(law_table); |
||||||
@ -0,0 +1,23 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <command.h> |
||||||
|
#include <pci.h> |
||||||
|
#include <asm/fsl_pci.h> |
||||||
|
#include <libfdt.h> |
||||||
|
#include <fdt_support.h> |
||||||
|
#include <asm/fsl_serdes.h> |
||||||
|
|
||||||
|
void pci_init_board(void) |
||||||
|
{ |
||||||
|
fsl_pcie_init_board(0); |
||||||
|
} |
||||||
|
|
||||||
|
void pci_of_setup(void *blob, bd_t *bd) |
||||||
|
{ |
||||||
|
FT_FSL_PCI_SETUP; |
||||||
|
} |
||||||
@ -0,0 +1,255 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <command.h> |
||||||
|
#include <i2c.h> |
||||||
|
#include <netdev.h> |
||||||
|
#include <linux/compiler.h> |
||||||
|
#include <asm/mmu.h> |
||||||
|
#include <asm/processor.h> |
||||||
|
#include <asm/cache.h> |
||||||
|
#include <asm/immap_85xx.h> |
||||||
|
#include <asm/fsl_law.h> |
||||||
|
#include <asm/fsl_serdes.h> |
||||||
|
#include <asm/fsl_portals.h> |
||||||
|
#include <asm/fsl_liodn.h> |
||||||
|
#include <fm_eth.h> |
||||||
|
|
||||||
|
#include "../common/qixis.h" |
||||||
|
#include "t1040qds.h" |
||||||
|
#include "t1040qds_qixis.h" |
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR; |
||||||
|
|
||||||
|
int checkboard(void) |
||||||
|
{ |
||||||
|
char buf[64]; |
||||||
|
u8 sw; |
||||||
|
struct cpu_type *cpu = gd->arch.cpu; |
||||||
|
static const char *const freq[] = {"100", "125", "156.25", "161.13", |
||||||
|
"122.88", "122.88", "122.88"}; |
||||||
|
int clock; |
||||||
|
|
||||||
|
printf("Board: %sQDS, ", cpu->name); |
||||||
|
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", |
||||||
|
QIXIS_READ(id), QIXIS_READ(arch)); |
||||||
|
|
||||||
|
sw = QIXIS_READ(brdcfg[0]); |
||||||
|
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||||
|
|
||||||
|
if (sw < 0x8) |
||||||
|
printf("vBank: %d\n", sw); |
||||||
|
else if (sw == 0x8) |
||||||
|
puts("PromJet\n"); |
||||||
|
else if (sw == 0x9) |
||||||
|
puts("NAND\n"); |
||||||
|
else if (sw == 0x15) |
||||||
|
printf("IFCCard\n"); |
||||||
|
else |
||||||
|
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
||||||
|
|
||||||
|
printf("FPGA: v%d (%s), build %d", |
||||||
|
(int)QIXIS_READ(scver), qixis_read_tag(buf), |
||||||
|
(int)qixis_read_minor()); |
||||||
|
/* the timestamp string contains "\n" at the end */ |
||||||
|
printf(" on %s", qixis_read_time(buf)); |
||||||
|
|
||||||
|
/*
|
||||||
|
* Display the actual SERDES reference clocks as configured by the |
||||||
|
* dip switches on the board. Note that the SWx registers could |
||||||
|
* technically be set to force the reference clocks to match the |
||||||
|
* values that the SERDES expects (or vice versa). For now, however, |
||||||
|
* we just display both values and hope the user notices when they |
||||||
|
* don't match. |
||||||
|
*/ |
||||||
|
puts("SERDES Reference: "); |
||||||
|
sw = QIXIS_READ(brdcfg[2]); |
||||||
|
clock = (sw >> 6) & 3; |
||||||
|
printf("Clock1=%sMHz ", freq[clock]); |
||||||
|
clock = (sw >> 4) & 3; |
||||||
|
printf("Clock2=%sMHz\n", freq[clock]); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
int select_i2c_ch_pca9547(u8 ch) |
||||||
|
{ |
||||||
|
int ret; |
||||||
|
|
||||||
|
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
||||||
|
if (ret) { |
||||||
|
puts("PCA: failed to select proper channel\n"); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
int board_early_init_r(void) |
||||||
|
{ |
||||||
|
#ifdef CONFIG_SYS_FLASH_BASE |
||||||
|
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||||
|
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||||
|
|
||||||
|
/*
|
||||||
|
* Remap Boot flash + PROMJET region to caching-inhibited |
||||||
|
* so that flash can be erased properly. |
||||||
|
*/ |
||||||
|
|
||||||
|
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||||
|
flush_dcache(); |
||||||
|
invalidate_icache(); |
||||||
|
|
||||||
|
/* invalidate existing TLB entry for flash + promjet */ |
||||||
|
disable_tlb(flash_esel); |
||||||
|
|
||||||
|
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||||
|
#endif |
||||||
|
set_liodns(); |
||||||
|
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||||
|
setup_portals(); |
||||||
|
#endif |
||||||
|
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
unsigned long get_board_sys_clk(void) |
||||||
|
{ |
||||||
|
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||||
|
|
||||||
|
switch (sysclk_conf & 0x0F) { |
||||||
|
case QIXIS_SYSCLK_64: |
||||||
|
return 64000000; |
||||||
|
case QIXIS_SYSCLK_83: |
||||||
|
return 83333333; |
||||||
|
case QIXIS_SYSCLK_100: |
||||||
|
return 100000000; |
||||||
|
case QIXIS_SYSCLK_125: |
||||||
|
return 125000000; |
||||||
|
case QIXIS_SYSCLK_133: |
||||||
|
return 133333333; |
||||||
|
case QIXIS_SYSCLK_150: |
||||||
|
return 150000000; |
||||||
|
case QIXIS_SYSCLK_160: |
||||||
|
return 160000000; |
||||||
|
case QIXIS_SYSCLK_166: |
||||||
|
return 166666666; |
||||||
|
} |
||||||
|
return 66666666; |
||||||
|
} |
||||||
|
|
||||||
|
unsigned long get_board_ddr_clk(void) |
||||||
|
{ |
||||||
|
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||||
|
|
||||||
|
switch ((ddrclk_conf & 0x30) >> 4) { |
||||||
|
case QIXIS_DDRCLK_100: |
||||||
|
return 100000000; |
||||||
|
case QIXIS_DDRCLK_125: |
||||||
|
return 125000000; |
||||||
|
case QIXIS_DDRCLK_133: |
||||||
|
return 133333333; |
||||||
|
} |
||||||
|
return 66666666; |
||||||
|
} |
||||||
|
|
||||||
|
static const char *serdes_clock_to_string(u32 clock) |
||||||
|
{ |
||||||
|
switch (clock) { |
||||||
|
case SRDS_PLLCR0_RFCK_SEL_100: |
||||||
|
return "100"; |
||||||
|
case SRDS_PLLCR0_RFCK_SEL_125: |
||||||
|
return "125"; |
||||||
|
case SRDS_PLLCR0_RFCK_SEL_156_25: |
||||||
|
return "156.25"; |
||||||
|
default: |
||||||
|
return "Unknown frequency"; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
#define NUM_SRDS_BANKS 2 |
||||||
|
int misc_init_r(void) |
||||||
|
{ |
||||||
|
u8 sw; |
||||||
|
serdes_corenet_t *srds_regs = |
||||||
|
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
||||||
|
u32 actual[NUM_SRDS_BANKS] = { 0 }; |
||||||
|
int i; |
||||||
|
|
||||||
|
sw = QIXIS_READ(brdcfg[2]); |
||||||
|
for (i = 0; i < NUM_SRDS_BANKS; i++) { |
||||||
|
unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
||||||
|
switch (clock) { |
||||||
|
case 0: |
||||||
|
actual[i] = SRDS_PLLCR0_RFCK_SEL_100; |
||||||
|
break; |
||||||
|
case 1: |
||||||
|
actual[i] = SRDS_PLLCR0_RFCK_SEL_125; |
||||||
|
break; |
||||||
|
case 2: |
||||||
|
actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; |
||||||
|
break; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
puts("SerDes1"); |
||||||
|
for (i = 0; i < NUM_SRDS_BANKS; i++) { |
||||||
|
u32 pllcr0 = srds_regs->bank[i].pllcr0; |
||||||
|
u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; |
||||||
|
if (expected != actual[i]) { |
||||||
|
printf("expects ref clk%d %sMHz, but actual is %sMHz\n", |
||||||
|
i + 1, serdes_clock_to_string(expected), |
||||||
|
serdes_clock_to_string(actual[i])); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
void ft_board_setup(void *blob, bd_t *bd) |
||||||
|
{ |
||||||
|
phys_addr_t base; |
||||||
|
phys_size_t size; |
||||||
|
|
||||||
|
ft_cpu_setup(blob, bd); |
||||||
|
|
||||||
|
base = getenv_bootm_low(); |
||||||
|
size = getenv_bootm_size(); |
||||||
|
|
||||||
|
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||||
|
|
||||||
|
#ifdef CONFIG_PCI |
||||||
|
pci_of_setup(blob, bd); |
||||||
|
#endif |
||||||
|
|
||||||
|
fdt_fixup_liodn(blob); |
||||||
|
|
||||||
|
#ifdef CONFIG_HAS_FSL_DR_USB |
||||||
|
fdt_fixup_dr_usb(blob, bd); |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_DPAA_FMAN |
||||||
|
fdt_fixup_fman_ethernet(blob); |
||||||
|
#endif |
||||||
|
} |
||||||
|
|
||||||
|
void qixis_dump_switch(void) |
||||||
|
{ |
||||||
|
int i, nr_of_cfgsw; |
||||||
|
|
||||||
|
QIXIS_WRITE(cms[0], 0x00); |
||||||
|
nr_of_cfgsw = QIXIS_READ(cms[1]); |
||||||
|
|
||||||
|
puts("DIP switch settings dump:\n"); |
||||||
|
for (i = 1; i <= nr_of_cfgsw; i++) { |
||||||
|
QIXIS_WRITE(cms[0], i); |
||||||
|
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); |
||||||
|
} |
||||||
|
} |
||||||
@ -0,0 +1,13 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __T1040_QDS_H__ |
||||||
|
#define __T1040_QDS_H__ |
||||||
|
|
||||||
|
void fdt_fixup_board_enet(void *blob); |
||||||
|
void pci_of_setup(void *blob, bd_t *bd); |
||||||
|
|
||||||
|
#endif |
||||||
@ -0,0 +1,36 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __T1040QDS_QIXIS_H__ |
||||||
|
#define __T1040QDS_QIXIS_H__ |
||||||
|
|
||||||
|
/* Definitions of QIXIS Registers for T1040QDS */ |
||||||
|
|
||||||
|
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ |
||||||
|
#define BRDCFG4_EMISEL_MASK 0xE0 |
||||||
|
#define BRDCFG4_EMISEL_SHIFT 5 |
||||||
|
|
||||||
|
/* SYSCLK */ |
||||||
|
#define QIXIS_SYSCLK_66 0x0 |
||||||
|
#define QIXIS_SYSCLK_83 0x1 |
||||||
|
#define QIXIS_SYSCLK_100 0x2 |
||||||
|
#define QIXIS_SYSCLK_125 0x3 |
||||||
|
#define QIXIS_SYSCLK_133 0x4 |
||||||
|
#define QIXIS_SYSCLK_150 0x5 |
||||||
|
#define QIXIS_SYSCLK_160 0x6 |
||||||
|
#define QIXIS_SYSCLK_166 0x7 |
||||||
|
#define QIXIS_SYSCLK_64 0x8 |
||||||
|
|
||||||
|
/* DDRCLK */ |
||||||
|
#define QIXIS_DDRCLK_66 0x0 |
||||||
|
#define QIXIS_DDRCLK_100 0x1 |
||||||
|
#define QIXIS_DDRCLK_125 0x2 |
||||||
|
#define QIXIS_DDRCLK_133 0x3 |
||||||
|
|
||||||
|
|
||||||
|
#define QIXIS_SRDS1CLK_122 0x5a |
||||||
|
#define QIXIS_SRDS1CLK_125 0x5e |
||||||
|
#endif |
||||||
@ -0,0 +1,108 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <asm/mmu.h> |
||||||
|
|
||||||
|
struct fsl_e_tlb_entry tlb_table[] = { |
||||||
|
/* TLB 0 - for temp stack in cache */ |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||||
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 0), |
||||||
|
|
||||||
|
/* TLB 1 */ |
||||||
|
/* *I*** - Covers boot page */ |
||||||
|
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) |
||||||
|
/*
|
||||||
|
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the |
||||||
|
* SRAM is at 0xfffc0000, it covered the 0xfffff000. |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 0, BOOKE_PAGESZ_256K, 1), |
||||||
|
#else |
||||||
|
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 0, BOOKE_PAGESZ_4K, 1), |
||||||
|
#endif |
||||||
|
|
||||||
|
/* *I*G* - CCSRBAR */ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 1, BOOKE_PAGESZ_16M, 1), |
||||||
|
|
||||||
|
/* *I*G* - Flash, localbus */ |
||||||
|
/* This will be changed to *I*G* after relocation to RAM. */ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||||
|
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||||
|
0, 2, BOOKE_PAGESZ_256M, 1), |
||||||
|
|
||||||
|
/* *I*G* - PCI */ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 3, BOOKE_PAGESZ_1G, 1), |
||||||
|
|
||||||
|
/* *I*G* - PCI I/O */ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 4, BOOKE_PAGESZ_256K, 1), |
||||||
|
|
||||||
|
/* Bman/Qman */ |
||||||
|
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 5, BOOKE_PAGESZ_16M, 1), |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, |
||||||
|
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 6, BOOKE_PAGESZ_16M, 1), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||||
|
0, 7, BOOKE_PAGESZ_16M, 1), |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, |
||||||
|
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 8, BOOKE_PAGESZ_16M, 1), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 9, BOOKE_PAGESZ_4M, 1), |
||||||
|
#endif |
||||||
|
#ifdef CONFIG_SYS_NAND_BASE |
||||||
|
/*
|
||||||
|
* *I*G - NAND |
||||||
|
* entry 14 and 15 has been used hard coded, they will be disabled |
||||||
|
* in cpu_init_f, so we use entry 16 for nand. |
||||||
|
*/ |
||||||
|
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 10, BOOKE_PAGESZ_64K, 1), |
||||||
|
#endif |
||||||
|
#ifdef QIXIS_BASE |
||||||
|
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, |
||||||
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||||
|
0, 11, BOOKE_PAGESZ_4K, 1), |
||||||
|
#endif |
||||||
|
|
||||||
|
}; |
||||||
|
|
||||||
|
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||||
@ -0,0 +1,16 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
*/ |
||||||
|
#include <common.h> |
||||||
|
#include <phy.h> |
||||||
|
#include <fm_eth.h> |
||||||
|
#include <asm/io.h> |
||||||
|
#include <asm/immap_85xx.h> |
||||||
|
#include <asm/fsl_serdes.h> |
||||||
|
|
||||||
|
phy_interface_t fman_port_enet_if(enum fm_port port) |
||||||
|
{ |
||||||
|
return PHY_INTERFACE_MODE_NONE; |
||||||
|
} |
||||||
@ -0,0 +1,761 @@ |
|||||||
|
/*
|
||||||
|
* Copyright 2013 Freescale Semiconductor, Inc. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __CONFIG_H |
||||||
|
#define __CONFIG_H |
||||||
|
|
||||||
|
/*
|
||||||
|
* T1040 QDS board configuration file |
||||||
|
*/ |
||||||
|
#define CONFIG_T1040QDS |
||||||
|
#define CONFIG_PHYS_64BIT |
||||||
|
|
||||||
|
#ifdef CONFIG_RAMBOOT_PBL |
||||||
|
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
||||||
|
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
||||||
|
#endif |
||||||
|
|
||||||
|
/* High Level Configuration Options */ |
||||||
|
#define CONFIG_BOOKE |
||||||
|
#define CONFIG_E500 /* BOOKE e500 family */ |
||||||
|
#define CONFIG_E500MC /* BOOKE e500mc family */ |
||||||
|
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
||||||
|
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ |
||||||
|
#define CONFIG_MP /* support multiple processors */ |
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_TEXT_BASE |
||||||
|
#define CONFIG_SYS_TEXT_BASE 0xeff80000 |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifndef CONFIG_RESET_VECTOR_ADDRESS |
||||||
|
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
||||||
|
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS |
||||||
|
#define CONFIG_FSL_IFC /* Enable IFC Support */ |
||||||
|
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||||
|
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||||
|
#define CONFIG_PCIE1 /* PCIE controler 1 */ |
||||||
|
#define CONFIG_PCIE2 /* PCIE controler 2 */ |
||||||
|
#define CONFIG_PCIE3 /* PCIE controler 3 */ |
||||||
|
#define CONFIG_PCIE4 /* PCIE controler 4 */ |
||||||
|
|
||||||
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
||||||
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
||||||
|
|
||||||
|
#define CONFIG_FSL_LAW /* Use common FSL init code */ |
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_NO_FLASH |
||||||
|
#define CONFIG_ENV_IS_NOWHERE |
||||||
|
#else |
||||||
|
#define CONFIG_FLASH_CFI_DRIVER |
||||||
|
#define CONFIG_SYS_FLASH_CFI |
||||||
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_NO_FLASH |
||||||
|
#if defined(CONFIG_SPIFLASH) |
||||||
|
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||||
|
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||||
|
#define CONFIG_ENV_SPI_BUS 0 |
||||||
|
#define CONFIG_ENV_SPI_CS 0 |
||||||
|
#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
||||||
|
#define CONFIG_ENV_SPI_MODE 0 |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||||
|
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||||
|
#elif defined(CONFIG_SDCARD) |
||||||
|
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||||
|
#define CONFIG_ENV_IS_IN_MMC |
||||||
|
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
#define CONFIG_ENV_OFFSET (512 * 1105) |
||||||
|
#elif defined(CONFIG_NAND) |
||||||
|
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||||
|
#define CONFIG_ENV_IS_IN_NAND |
||||||
|
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
||||||
|
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||||
|
#else |
||||||
|
#define CONFIG_ENV_IS_IN_FLASH |
||||||
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||||
|
#endif |
||||||
|
#else /* CONFIG_SYS_NO_FLASH */ |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__ |
||||||
|
unsigned long get_board_sys_clk(void); |
||||||
|
unsigned long get_board_ddr_clk(void); |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
||||||
|
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
||||||
|
|
||||||
|
/*
|
||||||
|
* These can be toggled for performance analysis, otherwise use default. |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_CACHE_STASHING |
||||||
|
#define CONFIG_BACKSIDE_L2_CACHE |
||||||
|
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E |
||||||
|
#define CONFIG_BTB /* toggle branch predition */ |
||||||
|
#define CONFIG_DDR_ECC |
||||||
|
#ifdef CONFIG_DDR_ECC |
||||||
|
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||||
|
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_ENABLE_36BIT_PHYS |
||||||
|
|
||||||
|
#define CONFIG_ADDR_MAP |
||||||
|
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
||||||
|
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
||||||
|
#define CONFIG_SYS_ALT_MEMTEST |
||||||
|
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Config the L3 Cache as L3 SRAM |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
||||||
|
|
||||||
|
#define CONFIG_SYS_DCSRBAR 0xf0000000 |
||||||
|
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
||||||
|
|
||||||
|
/* EEPROM */ |
||||||
|
#define CONFIG_ID_EEPROM |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||||
|
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||||
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||||
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
||||||
|
|
||||||
|
/*
|
||||||
|
* DDR Setup |
||||||
|
*/ |
||||||
|
#define CONFIG_VERY_BIG_RAM |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||||
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||||
|
|
||||||
|
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ |
||||||
|
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||||
|
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
||||||
|
|
||||||
|
#define CONFIG_DDR_SPD |
||||||
|
#define CONFIG_FSL_DDR3 |
||||||
|
#define CONFIG_FSL_DDR_INTERACTIVE |
||||||
|
|
||||||
|
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||||
|
#define SPD_EEPROM_ADDRESS 0x51 |
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* IFC Definitions |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_FLASH_BASE 0xe0000000 |
||||||
|
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
||||||
|
|
||||||
|
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
||||||
|
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
||||||
|
+ 0x8000000) | \
|
||||||
|
CSPR_PORT_SIZE_16 | \
|
||||||
|
CSPR_MSEL_NOR | \
|
||||||
|
CSPR_V) |
||||||
|
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) |
||||||
|
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
||||||
|
CSPR_PORT_SIZE_16 | \
|
||||||
|
CSPR_MSEL_NOR | \
|
||||||
|
CSPR_V) |
||||||
|
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||||
|
/* NOR Flash Timing Params */ |
||||||
|
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
||||||
|
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
||||||
|
FTIM0_NOR_TEADC(0x5) | \
|
||||||
|
FTIM0_NOR_TEAHC(0x5)) |
||||||
|
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
||||||
|
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||||
|
FTIM1_NOR_TSEQRAD_NOR(0x13)) |
||||||
|
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
||||||
|
FTIM2_NOR_TCH(0x4) | \
|
||||||
|
FTIM2_NOR_TWPH(0x0E) | \
|
||||||
|
FTIM2_NOR_TWP(0x1c)) |
||||||
|
#define CONFIG_SYS_NOR_FTIM3 0x0 |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||||
|
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||||
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||||
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||||
|
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ |
||||||
|
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
||||||
|
#define CONFIG_FSL_QIXIS /* use common QIXIS code */ |
||||||
|
#define QIXIS_BASE 0xffdf0000 |
||||||
|
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
||||||
|
#define QIXIS_LBMAP_SWITCH 0x06 |
||||||
|
#define QIXIS_LBMAP_MASK 0x0f |
||||||
|
#define QIXIS_LBMAP_SHIFT 0 |
||||||
|
#define QIXIS_LBMAP_DFLTBANK 0x00 |
||||||
|
#define QIXIS_LBMAP_ALTBANK 0x04 |
||||||
|
#define QIXIS_RST_CTL_RESET 0x31 |
||||||
|
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
||||||
|
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
||||||
|
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
||||||
|
|
||||||
|
#define CONFIG_SYS_CSPR3_EXT (0xf) |
||||||
|
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
||||||
|
| CSPR_PORT_SIZE_8 \
|
||||||
|
| CSPR_MSEL_GPCM \
|
||||||
|
| CSPR_V) |
||||||
|
#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) |
||||||
|
#define CONFIG_SYS_CSOR3 0x0 |
||||||
|
/* QIXIS Timing parameters for IFC CS3 */ |
||||||
|
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
||||||
|
FTIM0_GPCM_TEADC(0x0e) | \
|
||||||
|
FTIM0_GPCM_TEAHC(0x0e)) |
||||||
|
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
||||||
|
FTIM1_GPCM_TRAD(0x3f)) |
||||||
|
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
||||||
|
FTIM2_GPCM_TCH(0x0) | \
|
||||||
|
FTIM2_GPCM_TWP(0x1f)) |
||||||
|
#define CONFIG_SYS_CS3_FTIM3 0x0 |
||||||
|
|
||||||
|
#define CONFIG_NAND_FSL_IFC |
||||||
|
#define CONFIG_SYS_NAND_BASE 0xff800000 |
||||||
|
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
||||||
|
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||||
|
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||||
|
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||||
|
| CSPR_V) |
||||||
|
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||||
|
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||||
|
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||||
|
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||||
|
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||||
|
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||||
|
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||||
|
|
||||||
|
/* ONFI NAND Flash mode0 Timing Params */ |
||||||
|
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
||||||
|
FTIM0_NAND_TWP(0x18) | \
|
||||||
|
FTIM0_NAND_TWCHT(0x07) | \
|
||||||
|
FTIM0_NAND_TWH(0x0a)) |
||||||
|
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
||||||
|
FTIM1_NAND_TWBE(0x39) | \
|
||||||
|
FTIM1_NAND_TRR(0x0e) | \
|
||||||
|
FTIM1_NAND_TRP(0x18)) |
||||||
|
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
||||||
|
FTIM2_NAND_TREH(0x0a) | \
|
||||||
|
FTIM2_NAND_TWHRE(0x1e)) |
||||||
|
#define CONFIG_SYS_NAND_FTIM3 0x0 |
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_DDR_LAW 11 |
||||||
|
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||||
|
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||||
|
#define CONFIG_CMD_NAND |
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||||
|
|
||||||
|
#if defined(CONFIG_NAND) |
||||||
|
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||||
|
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
||||||
|
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
||||||
|
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
||||||
|
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||||
|
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||||
|
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||||
|
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||||
|
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||||
|
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR |
||||||
|
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
||||||
|
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
||||||
|
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||||
|
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||||
|
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||||
|
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||||
|
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT |
||||||
|
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR |
||||||
|
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
||||||
|
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
||||||
|
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||||
|
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||||
|
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||||
|
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||||
|
#else |
||||||
|
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||||
|
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
||||||
|
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||||
|
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||||
|
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||||
|
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||||
|
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||||
|
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||||
|
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
||||||
|
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR |
||||||
|
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
||||||
|
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
||||||
|
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||||
|
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||||
|
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||||
|
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||||
|
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||||
|
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
||||||
|
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
||||||
|
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
||||||
|
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||||
|
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||||
|
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||||
|
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||||
|
|
||||||
|
#if defined(CONFIG_RAMBOOT_PBL) |
||||||
|
#define CONFIG_SYS_RAMBOOT |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_R |
||||||
|
#define CONFIG_MISC_INIT_R |
||||||
|
|
||||||
|
#define CONFIG_HWCONFIG |
||||||
|
|
||||||
|
/* define to use L1 as initial stack */ |
||||||
|
#define CONFIG_L1_INIT_RAM |
||||||
|
#define CONFIG_SYS_INIT_RAM_LOCK |
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 |
||||||
|
/* The assembler doesn't like typecast */ |
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
||||||
|
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||||
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
||||||
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
||||||
|
|
||||||
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||||
|
GENERATED_GBL_DATA_SIZE) |
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||||
|
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
||||||
|
|
||||||
|
/* Serial Port - controlled on board with jumper J8
|
||||||
|
* open - index 2 |
||||||
|
* shorted - index 1 |
||||||
|
*/ |
||||||
|
#define CONFIG_CONS_INDEX 1 |
||||||
|
#define CONFIG_SYS_NS16550 |
||||||
|
#define CONFIG_SYS_NS16550_SERIAL |
||||||
|
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||||
|
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
||||||
|
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||||
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
||||||
|
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
||||||
|
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
||||||
|
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ |
||||||
|
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
||||||
|
|
||||||
|
/* Use the HUSH parser */ |
||||||
|
#define CONFIG_SYS_HUSH_PARSER |
||||||
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||||
|
|
||||||
|
/* pass open firmware flat tree */ |
||||||
|
#define CONFIG_OF_LIBFDT |
||||||
|
#define CONFIG_OF_BOARD_SETUP |
||||||
|
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||||
|
|
||||||
|
/* new uImage format support */ |
||||||
|
#define CONFIG_FIT |
||||||
|
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||||
|
|
||||||
|
/* I2C */ |
||||||
|
#define CONFIG_SYS_I2C |
||||||
|
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ |
||||||
|
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ |
||||||
|
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||||
|
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ |
||||||
|
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
||||||
|
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
||||||
|
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 |
||||||
|
|
||||||
|
#define I2C_MUX_PCA_ADDR 0x77 |
||||||
|
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ |
||||||
|
|
||||||
|
|
||||||
|
/* I2C bus multiplexer */ |
||||||
|
#define I2C_MUX_CH_DEFAULT 0x8 |
||||||
|
|
||||||
|
/*
|
||||||
|
* RTC configuration |
||||||
|
*/ |
||||||
|
#define RTC |
||||||
|
#define CONFIG_RTC_DS3231 1 |
||||||
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||||
|
|
||||||
|
/*
|
||||||
|
* eSPI - Enhanced SPI |
||||||
|
*/ |
||||||
|
#define CONFIG_FSL_ESPI |
||||||
|
#define CONFIG_SPI_FLASH |
||||||
|
#define CONFIG_SPI_FLASH_STMICRO |
||||||
|
#define CONFIG_SPI_FLASH_SST |
||||||
|
#define CONFIG_SPI_FLASH_EON |
||||||
|
#define CONFIG_CMD_SF |
||||||
|
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||||
|
#define CONFIG_SF_DEFAULT_MODE 0 |
||||||
|
|
||||||
|
/*
|
||||||
|
* General PCI |
||||||
|
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifdef CONFIG_PCI |
||||||
|
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
||||||
|
#ifdef CONFIG_PCIE1 |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
||||||
|
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
||||||
|
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
||||||
|
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||||
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
||||||
|
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
||||||
|
#ifdef CONFIG_PCIE2 |
||||||
|
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 |
||||||
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
||||||
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
||||||
|
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
||||||
|
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
||||||
|
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
||||||
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
||||||
|
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
||||||
|
#ifdef CONFIG_PCIE3 |
||||||
|
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
||||||
|
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
||||||
|
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
||||||
|
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ |
||||||
|
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
||||||
|
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
||||||
|
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
||||||
|
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/* controller 4, Base address 203000 */ |
||||||
|
#ifdef CONFIG_PCIE4 |
||||||
|
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 |
||||||
|
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
||||||
|
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull |
||||||
|
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ |
||||||
|
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 |
||||||
|
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 |
||||||
|
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
||||||
|
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||||
|
#define CONFIG_E1000 |
||||||
|
|
||||||
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||||
|
#define CONFIG_DOS_PARTITION |
||||||
|
#endif /* CONFIG_PCI */ |
||||||
|
|
||||||
|
/* SATA */ |
||||||
|
#define CONFIG_FSL_SATA_V2 |
||||||
|
#ifdef CONFIG_FSL_SATA_V2 |
||||||
|
#define CONFIG_LIBATA |
||||||
|
#define CONFIG_FSL_SATA |
||||||
|
|
||||||
|
#define CONFIG_SYS_SATA_MAX_DEVICE 2 |
||||||
|
#define CONFIG_SATA1 |
||||||
|
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
||||||
|
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
||||||
|
#define CONFIG_SATA2 |
||||||
|
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
||||||
|
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
||||||
|
|
||||||
|
#define CONFIG_LBA48 |
||||||
|
#define CONFIG_CMD_SATA |
||||||
|
#define CONFIG_DOS_PARTITION |
||||||
|
#define CONFIG_CMD_EXT2 |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* USB |
||||||
|
*/ |
||||||
|
#define CONFIG_HAS_FSL_DR_USB |
||||||
|
|
||||||
|
#ifdef CONFIG_HAS_FSL_DR_USB |
||||||
|
#define CONFIG_USB_EHCI |
||||||
|
|
||||||
|
#ifdef CONFIG_USB_EHCI |
||||||
|
#define CONFIG_CMD_USB |
||||||
|
#define CONFIG_USB_STORAGE |
||||||
|
#define CONFIG_USB_EHCI_FSL |
||||||
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||||
|
#define CONFIG_CMD_EXT2 |
||||||
|
#endif |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_MMC |
||||||
|
|
||||||
|
#ifdef CONFIG_MMC |
||||||
|
#define CONFIG_FSL_ESDHC |
||||||
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
||||||
|
#define CONFIG_CMD_MMC |
||||||
|
#define CONFIG_GENERIC_MMC |
||||||
|
#define CONFIG_CMD_EXT2 |
||||||
|
#define CONFIG_CMD_FAT |
||||||
|
#define CONFIG_DOS_PARTITION |
||||||
|
#endif |
||||||
|
|
||||||
|
/* Qman/Bman */ |
||||||
|
#ifndef CONFIG_NOBQFMAN |
||||||
|
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
||||||
|
#define CONFIG_SYS_BMAN_NUM_PORTALS 25 |
||||||
|
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
||||||
|
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
||||||
|
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
||||||
|
#define CONFIG_SYS_QMAN_NUM_PORTALS 25 |
||||||
|
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
||||||
|
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
||||||
|
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
||||||
|
|
||||||
|
#define CONFIG_SYS_DPAA_FMAN |
||||||
|
#define CONFIG_SYS_DPAA_PME |
||||||
|
|
||||||
|
/* Default address of microcode for the Linux Fman driver */ |
||||||
|
#if defined(CONFIG_SPIFLASH) |
||||||
|
/*
|
||||||
|
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
||||||
|
* env, so we got 0x110000. |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_QE_FW_IN_SPIFLASH |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 |
||||||
|
#elif defined(CONFIG_SDCARD) |
||||||
|
/*
|
||||||
|
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
||||||
|
* about 545KB (1089 blocks), Env is stored after the image, and the env size is |
||||||
|
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) |
||||||
|
#elif defined(CONFIG_NAND) |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||||
|
#else |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 |
||||||
|
#endif |
||||||
|
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
||||||
|
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
||||||
|
#endif /* CONFIG_NOBQFMAN */ |
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_DPAA_FMAN |
||||||
|
#define CONFIG_FMAN_ENET |
||||||
|
#define CONFIG_PHYLIB_10G |
||||||
|
#define CONFIG_PHY_VITESSE |
||||||
|
#define CONFIG_PHY_REALTEK |
||||||
|
#define CONFIG_PHY_TERANETICS |
||||||
|
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
||||||
|
#define SGMII_CARD_PORT2_PHY_ADDR 0x10 |
||||||
|
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
||||||
|
#define SGMII_CARD_PORT4_PHY_ADDR 0x11 |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef CONFIG_FMAN_ENET |
||||||
|
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 |
||||||
|
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 |
||||||
|
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 |
||||||
|
|
||||||
|
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c |
||||||
|
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d |
||||||
|
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e |
||||||
|
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f |
||||||
|
|
||||||
|
#define CONFIG_MII /* MII PHY management */ |
||||||
|
#define CONFIG_ETHPRIME "FM1@DTSEC1" |
||||||
|
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment |
||||||
|
*/ |
||||||
|
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||||
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration. |
||||||
|
*/ |
||||||
|
#include <config_cmd_default.h> |
||||||
|
|
||||||
|
#define CONFIG_CMD_DATE |
||||||
|
#define CONFIG_CMD_DHCP |
||||||
|
#define CONFIG_CMD_EEPROM |
||||||
|
#define CONFIG_CMD_ELF |
||||||
|
#define CONFIG_CMD_ERRATA |
||||||
|
#define CONFIG_CMD_GREPENV |
||||||
|
#define CONFIG_CMD_IRQ |
||||||
|
#define CONFIG_CMD_I2C |
||||||
|
#define CONFIG_CMD_MII |
||||||
|
#define CONFIG_CMD_PING |
||||||
|
#define CONFIG_CMD_REGINFO |
||||||
|
#define CONFIG_CMD_SETEXPR |
||||||
|
|
||||||
|
#ifdef CONFIG_PCI |
||||||
|
#define CONFIG_CMD_PCI |
||||||
|
#define CONFIG_CMD_NET |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||||
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||||
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||||
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||||
|
#ifdef CONFIG_CMD_KGDB |
||||||
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||||
|
#else |
||||||
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||||
|
#endif |
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||||
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
||||||
|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ |
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data |
||||||
|
* have to be in the first 64 MB of memory, since this is |
||||||
|
* the maximum mapped by the Linux kernel during initialization. |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
||||||
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||||
|
|
||||||
|
#ifdef CONFIG_CMD_KGDB |
||||||
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||||
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment Configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||||
|
#define CONFIG_BOOTFILE "uImage" |
||||||
|
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
||||||
|
|
||||||
|
/* default location for tftp and bootm */ |
||||||
|
#define CONFIG_LOADADDR 1000000 |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
|
||||||
|
#define __USB_PHY_TYPE utmi |
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||||
|
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||||
|
"bank_intlv=cs0_cs1;" \
|
||||||
|
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||||
|
"netdev=eth0\0" \
|
||||||
|
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||||
|
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||||
|
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||||
|
"protect off $ubootaddr +$filesize && " \
|
||||||
|
"erase $ubootaddr +$filesize && " \
|
||||||
|
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||||
|
"protect on $ubootaddr +$filesize && " \
|
||||||
|
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||||
|
"consoledev=ttyS0\0" \
|
||||||
|
"ramdiskaddr=2000000\0" \
|
||||||
|
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
|
||||||
|
"fdtaddr=c00000\0" \
|
||||||
|
"fdtfile=t1040qds/t1040qds.dtb\0" \
|
||||||
|
"bdev=sda3\0" \
|
||||||
|
"c=ffe\0" |
||||||
|
|
||||||
|
#define CONFIG_LINUX \ |
||||||
|
"setenv bootargs root=/dev/ram rw " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
|
"setenv ramdiskaddr 0x02000000;" \
|
||||||
|
"setenv fdtaddr 0x00c00000;" \
|
||||||
|
"setenv loadaddr 0x1000000;" \
|
||||||
|
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||||
|
|
||||||
|
#define CONFIG_HDBOOT \ |
||||||
|
"setenv bootargs root=/dev/$bdev rw " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
|
"bootm $loadaddr - $fdtaddr" |
||||||
|
|
||||||
|
#define CONFIG_NFSBOOTCOMMAND \ |
||||||
|
"setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=$serverip:$rootpath " \
|
||||||
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
|
"bootm $loadaddr - $fdtaddr" |
||||||
|
|
||||||
|
#define CONFIG_RAMBOOTCOMMAND \ |
||||||
|
"setenv bootargs root=/dev/ram rw " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
|
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
||||||
|
|
||||||
|
#ifdef CONFIG_SECURE_BOOT |
||||||
|
#include <asm/fsl_secure_boot.h> |
||||||
|
#endif |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue