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ppc4xx: remove VOH405 board

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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
master
Matthias Fuchs 10 years ago committed by Tom Rini
parent d526330479
commit 807db88b62
12 changed files with 1 additions and 8521 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/ppc4xx/Kconfig
  2. 12
      board/esd/voh405/Kconfig
  3. 6
      board/esd/voh405/MAINTAINERS
  4. 10
      board/esd/voh405/Makefile
  5. 85
      board/esd/voh405/flash.c
  6. 4021
      board/esd/voh405/fpgadata.c
  7. 153
      board/esd/voh405/logo_320_240_4bpp.c
  8. 3443
      board/esd/voh405/logo_640_480_24bpp.c
  9. 377
      board/esd/voh405/voh405.c
  10. 3
      configs/VOH405_defconfig
  11. 1
      doc/README.scrapyard
  12. 407
      include/configs/VOH405.h

4
arch/powerpc/cpu/ppc4xx/Kconfig
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@ -134,9 +134,6 @@ config TARGET_PMC405DE
config TARGET_PMC440
bool "Support PMC440"
config TARGET_VOH405
bool "Support VOH405"
config TARGET_VOM405
bool "Support VOM405"
@ -223,7 +220,6 @@ source "board/esd/cpci405/Kconfig"
source "board/esd/plu405/Kconfig"
source "board/esd/pmc405de/Kconfig"
source "board/esd/pmc440/Kconfig"
source "board/esd/voh405/Kconfig"
source "board/esd/vom405/Kconfig"
source "board/esd/wuh405/Kconfig"
source "board/g2000/Kconfig"

12
board/esd/voh405/Kconfig
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@ -1,12 +0,0 @@
if TARGET_VOH405
config SYS_BOARD
default "voh405"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "VOH405"
endif

6
board/esd/voh405/MAINTAINERS
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@ -1,6 +0,0 @@
VOH405 BOARD
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
S: Maintained
F: board/esd/voh405/
F: include/configs/VOH405.h
F: configs/VOH405_defconfig

10
board/esd/voh405/Makefile
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@ -1,10 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = voh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \

85
board/esd/voh405/flash.c
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@ -1,85 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0;
int i;
uint pbcr;
unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
}

4021
board/esd/voh405/fpgadata.c
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153
board/esd/voh405/logo_320_240_4bpp.c
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@ -1,153 +0,0 @@
0x1f, 0x8b, 0x08, 0x08, 0x7f, 0x95, 0xab, 0x3f,
0x00, 0x03, 0x50, 0x50, 0x43, 0x5f, 0x53, 0x74,
0x61, 0x72, 0x74, 0x6c, 0x6f, 0x67, 0x6f, 0x5f,
0x31, 0x36, 0x67, 0x2e, 0x62, 0x6d, 0x70, 0x00,
0xed, 0x9b, 0xcb, 0x71, 0xe3, 0x38, 0x10, 0x86,
0x7b, 0xaa, 0xe6, 0xb6, 0x87, 0x2e, 0x4f, 0x08,
0x3e, 0xed, 0xdd, 0x09, 0x6c, 0x6d, 0xf9, 0x3a,
0x47, 0xa7, 0xe0, 0x10, 0xc6, 0x29, 0x38, 0x82,
0xad, 0x72, 0x0a, 0x4e, 0xc1, 0x29, 0x38, 0x05,
0xa7, 0xe0, 0xea, 0x0c, 0x30, 0x12, 0x89, 0x06,
0x1a, 0x4f, 0x3d, 0x2c, 0x01, 0x9c, 0xad, 0xff,
0xf3, 0x48, 0xa2, 0x44, 0x82, 0xf8, 0xd8, 0x20,
0x5e, 0x24, 0xe7, 0xdf, 0x9f, 0xbf, 0xfe, 0xa3,
0x85, 0x5f, 0xbb, 0xd7, 0xdf, 0xbb, 0xd7, 0x3f,
0xdf, 0x88, 0x64, 0xf7, 0xf9, 0x8d, 0xbe, 0x93,
0xf2, 0xe3, 0xaf, 0xf5, 0x65, 0xb9, 0xb9, 0xb9,
0xa1, 0xdb, 0xdb, 0x5b, 0xba, 0xbb, 0xbb, 0xa3,
0xfb, 0xfb, 0x7b, 0x7a, 0x78, 0x78, 0xa0, 0xc7,
0xc7, 0x47, 0x7a, 0x7a, 0x7a, 0xa2, 0xe7, 0xe7,
0x67, 0x7a, 0x79, 0x79, 0xa1, 0xd7, 0xd7, 0x57,
0x7a, 0x7b, 0x7b, 0xa3, 0xf7, 0xf7, 0x77, 0xfa,
0xf8, 0xf8, 0xa0, 0xcf, 0xcf, 0x4f, 0x72, 0xce,
0xed, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff,
0x02, 0xa1, 0x8b, 0x03, 0x3f, 0xf8, 0xc1, 0x0f,
0x7e, 0xf0, 0xfb, 0xb3, 0xfd, 0xf6, 0x59, 0xf3,
0x66, 0xfd, 0xc2, 0xe6, 0x7d, 0xc5, 0x49, 0x7e,
0xfb, 0xcd, 0x84, 0x59, 0xd8, 0x1d, 0x48, 0x30,
0xc7, 0x6f, 0xd9, 0x88, 0x77, 0x7f, 0x3b, 0x41,
0xd7, 0x0d, 0xe1, 0x14, 0xbf, 0x45, 0x88, 0x97,
0x7f, 0xb2, 0x38, 0xb4, 0x05, 0x67, 0xf8, 0x2d,
0x3a, 0xb2, 0x2a, 0x2e, 0xff, 0xcb, 0xb0, 0x23,
0x38, 0xc1, 0x6f, 0xd5, 0xf3, 0x21, 0x5c, 0xdf,
0xa4, 0x99, 0x68, 0xbc, 0x9f, 0x04, 0xab, 0xf5,
0x4d, 0x5c, 0x4f, 0x70, 0xb8, 0xdf, 0x6a, 0xb2,
0x48, 0xad, 0x7e, 0xde, 0xb2, 0x51, 0xc2, 0xc3,
0xfd, 0x28, 0x37, 0xf3, 0xae, 0x8d, 0x64, 0xa3,
0xfd, 0x24, 0x96, 0xa9, 0xfa, 0xf9, 0x00, 0xd6,
0xd3, 0x8d, 0xf6, 0xb3, 0xe1, 0xd3, 0x0f, 0x31,
0xe6, 0x93, 0xfd, 0xba, 0xd9, 0x6d, 0xc0, 0x8f,
0x4c, 0xc0, 0x42, 0xfc, 0x7a, 0x01, 0x1c, 0xeb,
0x27, 0xb6, 0x5e, 0xc4, 0x4f, 0x97, 0xfe, 0x3c,
0xcf, 0x2f, 0x0d, 0x5f, 0xee, 0x57, 0x4b, 0x39,
0xd4, 0x2f, 0x0b, 0x5f, 0x5c, 0x68, 0x17, 0xf0,
0x58, 0xbf, 0x6a, 0xd8, 0xba, 0x01, 0x1c, 0xea,
0x97, 0x15, 0x6f, 0xe1, 0x27, 0xae, 0x60, 0xa4,
0x5f, 0x5e, 0xbc, 0x66, 0xa9, 0x59, 0xc0, 0x43,
0xfd, 0xea, 0x51, 0x33, 0xab, 0xca, 0xb4, 0x23,
0xfd, 0x7a, 0x35, 0xbb, 0x55, 0xc0, 0x98, 0x5f,
0xfe, 0x39, 0x7e, 0xbb, 0x21, 0x8a, 0x0e, 0x9d,
0xd7, 0x8d, 0x74, 0x58, 0xef, 0xc7, 0xf7, 0x93,
0xdb, 0xbf, 0x5d, 0x56, 0x9c, 0xf8, 0x91, 0xce,
0xdc, 0x7c, 0xa2, 0xc9, 0x7e, 0xe4, 0x0d, 0xd4,
0x4f, 0x38, 0x8e, 0x9d, 0xc3, 0x8a, 0x89, 0x7e,
0x6c, 0xfc, 0x74, 0xe6, 0x46, 0xce, 0x2c, 0xcc,
0xf5, 0x0b, 0x33, 0x36, 0xeb, 0x27, 0x9b, 0xf2,
0x5b, 0xcf, 0x37, 0xbd, 0x2e, 0x54, 0xfa, 0x51,
0x79, 0x29, 0xa1, 0xea, 0xb7, 0xac, 0x89, 0x5f,
0xf9, 0xb4, 0x23, 0xe9, 0xc5, 0xcf, 0x2f, 0x48,
0x33, 0x7e, 0x79, 0xea, 0x4a, 0xae, 0x9c, 0xad,
0x0a, 0x87, 0xb4, 0x5b, 0x32, 0x0d, 0xbc, 0x6d,
0xeb, 0xcd, 0x51, 0x1f, 0xe5, 0x17, 0x95, 0x8e,
0xf5, 0xe3, 0xb0, 0xc8, 0xd9, 0x3a, 0xf3, 0xfd,
0x4b, 0x7e, 0x49, 0xfd, 0x50, 0xb7, 0xa2, 0x7e,
0xb4, 0xfc, 0xd6, 0x5d, 0x67, 0xc5, 0x23, 0x45,
0x71, 0x7d, 0xc5, 0x8f, 0xf4, 0x5a, 0x41, 0x6c,
0x5f, 0xd6, 0x98, 0x9e, 0xe4, 0x97, 0x9c, 0xa0,
0x14, 0x5b, 0xd0, 0xa2, 0x03, 0x3f, 0xd9, 0x4f,
0x7c, 0x36, 0xa1, 0x1a, 0x84, 0x33, 0xdd, 0x1d,
0xac, 0x1f, 0x1c, 0x96, 0xfd, 0xaf, 0xc1, 0x4f,
0x3f, 0xc9, 0x4e, 0xac, 0xcf, 0xf2, 0x2b, 0xa7,
0xe0, 0x47, 0x74, 0xd5, 0xb9, 0x9f, 0x1e, 0x58,
0x38, 0xd4, 0xf0, 0xdd, 0x5c, 0x37, 0xa9, 0xfa,
0x1d, 0xaa, 0xbf, 0xe7, 0x21, 0x66, 0x9f, 0xb6,
0x00, 0xd4, 0x94, 0x5d, 0x72, 0x0c, 0x62, 0x44,
0xe2, 0x1a, 0x3a, 0xe4, 0x57, 0x36, 0x12, 0x7d,
0xf2, 0x3a, 0x9a, 0x16, 0xa7, 0x3d, 0x25, 0x4d,
0xce, 0x13, 0xfd, 0x58, 0x77, 0xc3, 0x59, 0xa6,
0x72, 0x19, 0xbf, 0xf3, 0x09, 0x7e, 0xf1, 0x42,
0xb0, 0xcd, 0x48, 0x74, 0x13, 0x73, 0x29, 0x67,
0x82, 0x9f, 0x5b, 0x4b, 0xf2, 0x9a, 0x7e, 0xc2,
0xbe, 0x02, 0x53, 0xda, 0xd8, 0x2d, 0x27, 0x3d,
0xfb, 0x2a, 0xb9, 0x16, 0x97, 0x6d, 0x63, 0x32,
0x3f, 0x93, 0xa7, 0x89, 0xea, 0x25, 0xfc, 0xa8,
0xe1, 0xb7, 0xef, 0x34, 0xc9, 0xfa, 0x49, 0xdb,
0xcf, 0x5d, 0xd3, 0x8f, 0xaa, 0x7e, 0xe2, 0xf3,
0x26, 0x13, 0xe4, 0xc2, 0x8f, 0xb5, 0xa5, 0xab,
0xfa, 0x91, 0xc5, 0x24, 0xcc, 0xfc, 0xc2, 0xfe,
0x3a, 0x7e, 0x12, 0xfd, 0xfc, 0x4b, 0x7b, 0xe4,
0xe8, 0x47, 0xd2, 0xf6, 0x0b, 0xe1, 0xba, 0xbc,
0x1f, 0x8b, 0xcf, 0x3a, 0xf5, 0xd3, 0x89, 0x47,
0xf0, 0x93, 0x8a, 0x9f, 0xd3, 0x9e, 0xb6, 0xea,
0x27, 0x97, 0xf0, 0x93, 0xa3, 0xfd, 0x78, 0x96,
0x1f, 0x3b, 0x56, 0x3f, 0x3d, 0x65, 0xfd, 0x29,
0x68, 0xeb, 0x07, 0xb9, 0x8e, 0x9f, 0xe3, 0x6b,
0xfa, 0xed, 0x0d, 0xcf, 0xf1, 0xe3, 0xa8, 0xd9,
0x6c, 0xff, 0xcc, 0x6f, 0x76, 0xb5, 0xf1, 0x2b,
0x0f, 0x21, 0xf5, 0x5b, 0xa2, 0x47, 0xd5, 0xf2,
0x75, 0x2e, 0x94, 0x6f, 0x18, 0x14, 0xd6, 0xfd,
0x5c, 0xee, 0x97, 0xe4, 0xfc, 0x05, 0x3f, 0x72,
0x99, 0x9f, 0x39, 0x15, 0xad, 0x9f, 0x56, 0x69,
0xeb, 0xa7, 0x3b, 0xcf, 0xca, 0x33, 0xef, 0x7f,
0x35, 0x9e, 0xe7, 0xfa, 0x91, 0xb8, 0xd2, 0x2f,
0x6f, 0x5f, 0x8e, 0xf0, 0x2b, 0xc6, 0x2f, 0x72,
0x21, 0x3f, 0x52, 0x13, 0xed, 0x0f, 0x54, 0x26,
0xb6, 0xcf, 0xc4, 0x55, 0xbf, 0x38, 0xca, 0x8a,
0x3e, 0x7e, 0x29, 0x0a, 0x6b, 0x07, 0x73, 0x8e,
0x9f, 0xf8, 0xae, 0xc2, 0xfb, 0xed, 0xf1, 0xb9,
0x2c, 0xfd, 0x9b, 0x0e, 0x89, 0x25, 0x9c, 0x53,
0xc6, 0x8f, 0x73, 0xbf, 0x38, 0x90, 0x16, 0x33,
0x60, 0x8d, 0x53, 0x99, 0xba, 0x9f, 0x06, 0xaa,
0xee, 0xc7, 0xb9, 0x1f, 0x7b, 0x3f, 0x9f, 0xd7,
0xb1, 0x7e, 0xe9, 0x15, 0x4c, 0xe3, 0xc9, 0x1a,
0x86, 0x90, 0xf2, 0x14, 0xbf, 0x0e, 0xbd, 0xbb,
0xfb, 0xa1, 0xdf, 0x0d, 0xd9, 0x54, 0x1b, 0xc7,
0x6a, 0xe6, 0x97, 0xf2, 0xeb, 0x53, 0xf8, 0xd9,
0xdd, 0xe7, 0x79, 0xcb, 0x0c, 0xbf, 0x6c, 0x04,
0x6f, 0xf2, 0x2a, 0x32, 0xa7, 0xaf, 0xf9, 0xf9,
0x35, 0xa6, 0xb3, 0x89, 0xeb, 0xd8, 0x6e, 0x91,
0xfb, 0x85, 0x1e, 0x62, 0xd9, 0xbf, 0xa6, 0x0f,
0x15, 0xb2, 0xf8, 0xa1, 0x4f, 0x3b, 0x16, 0xdc,
0xf4, 0x2b, 0x6e, 0x3d, 0x44, 0xbf, 0x46, 0x0e,
0x76, 0x05, 0x9f, 0xa2, 0xd7, 0x29, 0x5f, 0xae,
0x5b, 0x85, 0xa5, 0xc9, 0xf7, 0x67, 0x8a, 0xfb,
0x5b, 0xf9, 0x9d, 0xae, 0x4a, 0xd2, 0x9a, 0x1f,
0x2f, 0xdb, 0x5f, 0xc1, 0x2f, 0x2f, 0xe0, 0xdc,
0xaf, 0xd2, 0xd0, 0x0c, 0xf5, 0xcb, 0x35, 0x24,
0x5d, 0x38, 0xf6, 0xfa, 0xee, 0xf5, 0xfc, 0xb2,
0x02, 0xce, 0x6e, 0x54, 0xd7, 0x52, 0x8e, 0xf5,
0xcb, 0x0a, 0x58, 0x92, 0xcf, 0x0d, 0x3c, 0x7f,
0xd0, 0x3f, 0xe8, 0xea, 0x11, 0x8d, 0xf5, 0x4b,
0x03, 0x98, 0x3c, 0xc7, 0xb1, 0x89, 0xe7, 0x5f,
0xd2, 0xe7, 0x73, 0xc4, 0x7e, 0x34, 0xe6, 0x05,
0x83, 0xfd, 0xec, 0xe3, 0x61, 0x49, 0xaf, 0xd1,
0x78, 0x40, 0x6c, 0xb4, 0x9f, 0xef, 0xdf, 0x6d,
0x4f, 0xb2, 0xa9, 0xe7, 0xc3, 0xe2, 0x8c, 0x3c,
0x98, 0x71, 0xd4, 0xde, 0x82, 0x9f, 0x29, 0xe1,
0xf8, 0xd6, 0x1c, 0xa3, 0x8e, 0xf7, 0xf3, 0x82,
0xec, 0xd5, 0xd6, 0x09, 0x5c, 0x33, 0xd1, 0x04,
0x3f, 0x17, 0x67, 0xfe, 0xea, 0xd9, 0x19, 0x93,
0x4d, 0xf0, 0x73, 0x7a, 0x2d, 0x4f, 0x74, 0xc2,
0xd5, 0xde, 0x74, 0x8a, 0xdf, 0x3a, 0x2a, 0xde,
0x4d, 0xd7, 0xf6, 0x86, 0xcd, 0x2b, 0x72, 0x13,
0xfd, 0xd6, 0x99, 0x21, 0x89, 0x30, 0x1d, 0x78,
0x00, 0x7f, 0x96, 0x5f, 0x6d, 0xea, 0xb2, 0x29,
0xbf, 0x23, 0x81, 0x1f, 0xfc, 0xe0, 0x07, 0x3f,
0xf8, 0x6d, 0xd3, 0x0f, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0x8e, 0xdf,
0xe3, 0xb7, 0xe4, 0x39, 0x76, 0x96, 0x00, 0x00,

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board/esd/voh405/logo_640_480_24bpp.c
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377
board/esd/voh405/voh405.c
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@ -1,377 +0,0 @@
/*
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>
/* ------------------------------------------------------------------------- */
#if 0
#define FPGA_DEBUG
#endif
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};
/*
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp_320[] =
{
#include "logo_320_240_4bpp.c"
};
unsigned char logo_bmp_640[] =
{
#include "logo_640_480_24bpp.c"
};
/*
* include common lcd code (for esd boards)
*/
#include "../common/lcd.c"
#include "../common/s1d13704_320_240_4bpp.h"
#include "../common/s1d13806_320_240_4bpp.h"
#include "../common/s1d13806_640_480_16bpp.h"
int board_early_init_f (void)
{
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned short *lcd_contrast =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
unsigned short *lcd_backlight =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
char *str;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc ('\n');
do_reset(NULL, 0, 0, NULL);
}
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
}
putc ('\n');
free(dst);
/*
* Reset FPGA via FPGA_INIT pin
*/
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Reset external DUARTs
*/
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/*
* Setup EEPROM write protection
*/
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/*
* Enable interrupts in exar duart mcr[3]
*/
out_8(duart0_mcr, 0x08);
out_8(duart1_mcr, 0x08);
/*
* Init lcd interface and display logo
*/
str = getenv("bd_type");
if (strcmp(str, "voh405_bw") == 0) {
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
} else if (strcmp(str, "voh405_bwbw") == 0) {
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
lcd_setup(1, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_320_240_4bpp,
sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
} else if (strcmp(str, "voh405_bwc") == 0) {
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
logo_bmp_640, sizeof(logo_bmp_640));
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
}
/*
* Set invert bit in small lcd controller
*/
out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
/*
* Set default contrast voltage on epson vga controller
*/
out_be16(lcd_contrast, 0x4646);
/*
* Enable backlight
*/
out_be16(lcd_backlight, 0xffff);
/*
* Enable external I2C bus
*/
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
return (0);
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
char str[64];
int i = getenv_f("serial#", str, sizeof(str));
puts ("Board: ");
if (i == -1) {
puts ("### No HW ID - assuming VOH405");
} else {
puts(str);
}
if (getenv_f("bd_type", str, sizeof(str)) != -1) {
printf(" (%s)", str);
} else {
puts(" (Missing bd_type!)");
}
putc ('\n');
return 0;
}
#ifdef CONFIG_IDE_RESET
#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
void ide_set_reset(int on)
{
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
out_be16((void *)FPGA_MODE,
in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
out_be16((void *)FPGA_MODE,
in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
* 1: enable write
* Returns: -1: wrong device address
* 0: dis-/en- able done
* 0/1: current state if <state> was -1.
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO0. */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
break;
}
}
return state;
}
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int query = argc == 1;
int state = 0;
if (query) {
/* Query write access state. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
}
}
return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"Enable / disable / query EEPROM write access",
""
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */

3
configs/VOH405_defconfig
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@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_VOH405=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
VOH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>

407
include/configs/VOH405.h
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@ -1,407 +0,0 @@
/*
* (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_VOH405 1 /* ...on a VOH405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
/*-----------------------------------------------------------------------
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFF80000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CONFIG_SYS_RAMBOOT 1
#else
# undef CONFIG_SYS_RAMBOOT
#endif
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#define CONFIG_SYS_EEPROM_WREN 1
/* CAT24WC32/64... */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CAN_BA 0xF0000000 /* CAN Base Address */
#define DUART0_BA 0xF0000400 /* DUART Base Address */
#define DUART1_BA 0xF0000408 /* DUART Base Address */
#define RTC_BA 0xF0000500 /* RTC Base Address */
#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 4 (Epson VGA) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* LCD Setup
*/
#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
/*-----------------------------------------------------------------------
* FPGA stuff
*/
#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_CTRL 0x000
/* FPGA Control Reg */
#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
* GPIO0[1-9] - Instruction trace outputs -> GPIO
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[24-27] - UART0 control signal inputs/outputs
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
*/
#define CONFIG_SYS_GPIO0_OSRL 0x00000550
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0x777E0017
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
#define CONFIG_SYS_IIC_ON (0x80000000 >> 8)
#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#if 1
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
#endif
#if 0
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
#endif
#endif /* __CONFIG_H */
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