There are two versions of imx6ul pico SOMs: one with 256MB and another one with 512MB of RAM. Convert to SPL so that both versions can be supported. This patch doesn't rework the clock initialization to avoid changing the behavior in this same patch, so it will be cleaned up in future. Currently only the 256MB is tested/supported. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>lime2-spi
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// SPDX-License-Identifier: GPL-2.0+
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#include <asm/arch/clock.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/mx6ul_pins.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/mach-imx/iomux-v3.h> |
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#include <asm/mach-imx/boot_mode.h> |
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#include <linux/libfdt.h> |
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#include <spl.h> |
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#if defined(CONFIG_SPL_BUILD) |
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#include <asm/arch/mx6-ddr.h> |
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
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.grp_addds = 0x00000030, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_b0ds = 0x00000030, |
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.grp_ctlds = 0x00000030, |
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.grp_b1ds = 0x00000030, |
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.grp_ddrpke = 0x00000000, |
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.grp_ddrmode = 0x00020000, |
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.grp_ddr_type = 0x00080000, |
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}; |
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { |
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.dram_dqm0 = 0x00000030, |
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.dram_dqm1 = 0x00000030, |
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.dram_ras = 0x00000030, |
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.dram_cas = 0x00000030, |
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.dram_odt0 = 0x00000030, |
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.dram_odt1 = 0x00000030, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdclk_0 = 0x00000030, |
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.dram_sdqs0 = 0x00000030, |
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.dram_sdqs1 = 0x00000030, |
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.dram_reset = 0x00000030, |
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}; |
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static struct mx6_mmdc_calibration mx6_mmcd_calib = { |
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.p0_mpwldectrl0 = 0x00000000, |
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.p0_mpdgctrl0 = 0x01380134, |
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.p0_mprddlctl = 0x40404244, |
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.p0_mpwrdlctl = 0x40405050, |
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}; |
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static struct mx6_ddr_sysinfo ddr_sysinfo = { |
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.dsize = 0, |
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.cs1_mirror = 0, |
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.cs_density = 32, |
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.ncs = 1, |
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.bi_on = 1, |
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.rtt_nom = 1, |
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.rtt_wr = 0, |
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.ralat = 5, |
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.walat = 0, |
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.mif3_mode = 3, |
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.rst_to_cke = 0x23, |
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.sde_to_rst = 0x10, |
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.refsel = 1, |
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.refr = 3, |
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}; |
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static struct mx6_ddr3_cfg mem_ddr = { |
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.mem_speed = 1333, |
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.density = 2, |
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.width = 16, |
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.banks = 8, |
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.rowaddr = 14, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1350, |
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.trcmin = 4950, |
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.trasmin = 3600, |
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}; |
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static void ccgr_init(void) |
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{ |
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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writel(0xFFFFFFFF, &ccm->CCGR0); |
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writel(0xFFFFFFFF, &ccm->CCGR1); |
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writel(0xFFFFFFFF, &ccm->CCGR2); |
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writel(0xFFFFFFFF, &ccm->CCGR3); |
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writel(0xFFFFFFFF, &ccm->CCGR4); |
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writel(0xFFFFFFFF, &ccm->CCGR5); |
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writel(0xFFFFFFFF, &ccm->CCGR6); |
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} |
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static void spl_dram_init(void) |
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{ |
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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ccgr_init(); |
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arch_cpu_init(); |
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board_early_init_f(); |
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timer_init(); |
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preloader_console_init(); |
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spl_dram_init(); |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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board_init_r(NULL, 0); |
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} |
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void reset_cpu(ulong addr) |
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{ |
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} |
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#endif |
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