@ -91,25 +91,26 @@ static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
# if defined(CONFIG_ARMADA_38X)
# if defined(CONFIG_ARMADA_38X)
# define PCIE_BASE(if) \
# define PCIE_BASE(if) \
( ( if ) = = 0 ? \
( ( if ) = = 0 ? \
MVEBU_REG_PCIE_BASE + 0x40000 : \
MVEBU_REG_PCIE0 _BASE : \
MVEBU_REG_PCIE_BASE + 0x4000 * ( if ) )
( MVEBU_REG_PCIE_BASE + 0x4000 * ( if - 1 ) ) )
/*
/*
* On A38x MV6820 these PEX ports are supported :
* On A38x MV6820 these PEX ports are supported :
* 0 - Port 0.0
* 0 - Port 0.0
* 1 - Port 0.1
* 1 - Port 1.0
* 2 - Port 0.2
* 2 - Port 2.0
* 3 - Port 3.0
*/
*/
# define MAX_PEX 3
# define MAX_PEX 4
static struct mvebu_pcie pcie_bus [ MAX_PEX ] ;
static struct mvebu_pcie pcie_bus [ MAX_PEX ] ;
static void mvebu_get_port_lane ( struct mvebu_pcie * pcie , int pex_idx ,
static void mvebu_get_port_lane ( struct mvebu_pcie * pcie , int pex_idx ,
int * mem_target , int * mem_attr )
int * mem_target , int * mem_attr )
{
{
u8 port [ ] = { 0 , 1 , 2 } ;
u8 port [ ] = { 0 , 1 , 2 , 3 } ;
u8 lane [ ] = { 0 , 0 , 0 } ;
u8 lane [ ] = { 0 , 0 , 0 , 0 } ;
u8 target [ ] = { 8 , 4 , 4 } ;
u8 target [ ] = { 8 , 4 , 4 , 4 } ;
u8 attr [ ] = { 0xe8 , 0xe8 , 0xd8 } ;
u8 attr [ ] = { 0xe8 , 0xe8 , 0xd8 , 0xb8 } ;
pcie - > port = port [ pex_idx ] ;
pcie - > port = port [ pex_idx ] ;
pcie - > lane = lane [ pex_idx ] ;
pcie - > lane = lane [ pex_idx ] ;
@ -351,9 +352,9 @@ void pci_init_board(void)
mvebu_get_port_lane ( pcie , i , & mem_target , & mem_attr ) ;
mvebu_get_port_lane ( pcie , i , & mem_target , & mem_attr ) ;
/* Don't read at all from pci registers if port power is down */
/* Don't read at all from pci registers if port power is down */
if ( pcie - > lane = = 0 & & SELECT ( soc_ctrl , pcie - > port ) = = 0 ) {
if ( SELECT ( soc_ctrl , pcie - > port ) = = 0 ) {
i + = 3 ;
if ( pcie - > lane = = 0 )
debug ( " %s: skipping port %d \n " , __func__ , pcie - > port ) ;
debug ( " %s: skipping port %d \n " , __func__ , pcie - > port ) ;
continue ;
continue ;
}
}