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omap3_dss: cosmetic changes

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Remove unnecessary brackets.
Unwrap lines which are below 80 chars.
Single line comment as single line (as the rest).
Moved init values to the source code.

cc: s-paulraj@ti.com
cc: khasim@ti.com
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
master
Jeroen Hofstee 13 years ago committed by Anatolij Gustschin
parent d9c13aac14
commit 8da2efb661
2 changed files with 17 additions and 40 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 24
      arch/arm/include/asm/arch-omap3/dss.h
  2. 33
      drivers/video/omap3_dss.c

24
arch/arm/include/asm/arch-omap3/dss.h
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@ -28,9 +28,7 @@
#ifndef DSS_H #ifndef DSS_H
#define DSS_H #define DSS_H
/* /* DSS Base Registers */
* DSS Base Registers
*/
#define OMAP3_DSS_BASE 0x48050000 #define OMAP3_DSS_BASE 0x48050000
#define OMAP3_DISPC_BASE 0x48050400 #define OMAP3_DISPC_BASE 0x48050400
#define OMAP3_VENC_BASE 0x48050C00 #define OMAP3_VENC_BASE 0x48050C00
@ -163,26 +161,14 @@ struct venc_regs {
#define GP_OUT0 (1 << 15) #define GP_OUT0 (1 << 15)
#define GP_OUT1 (1 << 16) #define GP_OUT1 (1 << 16)
#define DISPC_ENABLE (LCD_ENABLE | \
DIG_ENABLE | \
GO_LCD | \
GO_DIG | \
GP_OUT0| \
GP_OUT1)
/* Configure VENC DSS Params */ /* Configure VENC DSS Params */
#define VENC_CLK_ENABLE (1 << 3) #define VENC_CLK_ENABLE (1 << 3)
#define DAC_DEMEN (1 << 4) #define DAC_DEMEN (1 << 4)
#define DAC_POWERDN (1 << 5) #define DAC_POWERDN (1 << 5)
#define VENC_OUT_SEL (1 << 6) #define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16 #define DIG_LPP_SHIFT 16
#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
DAC_DEMEN | \ /* Panel Configuration */
DAC_POWERDN | \
VENC_OUT_SEL)
/*
* Panel Configuration
*/
struct panel_config { struct panel_config {
u32 timing_h; u32 timing_h;
u32 timing_v; u32 timing_v;
@ -196,9 +182,7 @@ struct panel_config {
void *frame_buffer; void *frame_buffer;
}; };
/* /* Generic DSS Functions */
* Generic DSS Functions
*/
void omap3_dss_venc_config(const struct venc_regs *venc_cfg, void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width); u32 height, u32 width);
void omap3_dss_panel_config(const struct panel_config *panel_cfg); void omap3_dss_panel_config(const struct panel_config *panel_cfg);

33
drivers/video/omap3_dss.c
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@ -30,9 +30,7 @@
#include <asm/arch/dss.h> #include <asm/arch/dss.h>
#include <video_fb.h> #include <video_fb.h>
/* /* Configure VENC for a given Mode (NTSC / PAL) */
* Configure VENC for a given Mode (NTSC / PAL)
*/
void omap3_dss_venc_config(const struct venc_regs *venc_cfg, void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width) u32 height, u32 width)
{ {
@ -65,10 +63,8 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
writel(venc_cfg->savid__eavid, &venc->savid__eavid); writel(venc_cfg->savid__eavid, &venc->savid__eavid);
writel(venc_cfg->flen__fal, &venc->flen__fal); writel(venc_cfg->flen__fal, &venc->flen__fal);
writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset); writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
writel(venc_cfg->hs_int_start_stop_x, writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x);
&venc->hs_int_start_stop_x); writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x);
writel(venc_cfg->hs_ext_start_stop_x,
&venc->hs_ext_start_stop_x);
writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x); writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
writel(venc_cfg->vs_int_stop_x__vs_int_start_y, writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
&venc->vs_int_stop_x__vs_int_start_y); &venc->vs_int_stop_x__vs_int_start_y);
@ -94,15 +90,14 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c); writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
/* Configure DSS for VENC Settings */ /* Configure DSS for VENC Settings */
writel(VENC_DSS_CONFIG, &dss->control); writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL,
&dss->control);
/* Configure height and width for Digital out */ /* Configure height and width for Digital out */
writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig); writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig);
} }
/* /* Configure Panel Specific Parameters */
* Configure Panel Specific Parameters
*/
void omap3_dss_panel_config(const struct panel_config *panel_cfg) void omap3_dss_panel_config(const struct panel_config *panel_cfg)
{ {
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
@ -117,9 +112,9 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg)
writel(panel_cfg->pol_freq, &dispc->pol_freq); writel(panel_cfg->pol_freq, &dispc->pol_freq);
writel(panel_cfg->divisor, &dispc->divisor); writel(panel_cfg->divisor, &dispc->divisor);
writel(panel_cfg->lcd_size, &dispc->size_lcd); writel(panel_cfg->lcd_size, &dispc->size_lcd);
writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config); writel(panel_cfg->load_mode << FRAME_MODE_SHIFT, &dispc->config);
writel(((panel_cfg->panel_type << TFTSTN_SHIFT) | writel(panel_cfg->panel_type << TFTSTN_SHIFT |
(panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control); panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
writel(panel_cfg->panel_color, &dispc->default_color0); writel(panel_cfg->panel_color, &dispc->default_color0);
writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0); writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
@ -133,16 +128,14 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg)
writel(panel_cfg->lcd_size, &dispc->gfx_size); writel(panel_cfg->lcd_size, &dispc->gfx_size);
} }
/* /* Enable LCD and DIGITAL OUT in DSS */
* Enable LCD and DIGITAL OUT in DSS
*/
void omap3_dss_enable(void) void omap3_dss_enable(void)
{ {
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
u32 l = 0; u32 l;
l = readl(&dispc->control); l = readl(&dispc->control);
l |= DISPC_ENABLE; l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
writel(l, &dispc->control); writel(l, &dispc->control);
} }

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