arm: rmobile: rcar: Stop clock prior to booting kernel

This stops clock except INTC-RT, MSIF, INTC-SYS, IRQC and SCIF before
kernel boots.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Nobuhiro Iwamatsu 10 years ago committed by Nobuhiro Iwamatsu
parent d3a22419cf
commit 8e2e58863a
  1. 38
      board/renesas/rcar-gen2-common/common.c
  2. 10
      include/configs/alt.h
  3. 10
      include/configs/gose.h
  4. 11
      include/configs/koelsch.h
  5. 10
      include/configs/lager.h

@ -16,12 +16,44 @@
#define TSTR0 0x04
#define TSTR0_STR0 0x01
#define TMU0_MSTP125 (1 << 25)
static struct mstp_ctl mstptbl[] = {
{ SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
{ SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
{ SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
{ SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
{ SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
/* No MSTP6 */
{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
{ SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
{ SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
{ SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
};
void arch_preboot_os(void)
{
int i;
/* stop TMU0 */
mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
/* Disable TMU0 */
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
/* Stop module clock */
for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
mstptbl[i].s_ena);
mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
mstptbl[i].r_ena);
}
}

@ -95,4 +95,14 @@
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF2 */
#define CONFIG_SMSTP7_ENA 0x00080000
#endif /* __ALT_H */

@ -91,4 +91,14 @@
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __GOSE_H */

@ -92,4 +92,15 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF*/
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __KOELSCH_H */

@ -93,4 +93,14 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __LAGER_H */

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