Add basic i2c driver for Tegra2 with 8- and 16-bit address support. The driver requires CONFIG_OF_CONTROL to obtain its configuration from the device tree. (Simon Glass: sjg@chromium.org modified for upstream) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>master
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/*
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* NVIDIA Tegra2 I2C controller |
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* |
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* Copyright 2010-2011 NVIDIA Corporation |
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* |
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* This software may be used and distributed according to the |
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* terms of the GNU Public License, Version 2, incorporated |
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* herein by reference. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _TEGRA_I2C_H_ |
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#define _TEGRA_I2C_H_ |
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#include <asm/types.h> |
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enum { |
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I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ |
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I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ |
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}; |
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enum i2c_transaction_flags { |
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I2C_IS_WRITE = 0x1, /* for I2C write operation */ |
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I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ |
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I2C_USE_REPEATED_START = 0x4, /* for repeat start */ |
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I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ |
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I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ |
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I2C_NO_STOP = 0x20, |
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}; |
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|
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/* Contians the I2C transaction details */ |
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struct i2c_trans_info { |
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/* flags to indicate the transaction details */ |
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enum i2c_transaction_flags flags; |
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u32 address; /* I2C slave device address */ |
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u32 num_bytes; /* number of bytes to be transferred */ |
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/*
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* Send/receive buffer. For the I2C send operation this buffer should |
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* be filled with the data to be sent to the slave device. For the I2C |
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* receive operation this buffer is filled with the data received from |
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* the slave device. |
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*/ |
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u8 *buf; |
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int is_10bit_address; |
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}; |
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struct i2c_control { |
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u32 tx_fifo; |
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u32 rx_fifo; |
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u32 packet_status; |
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u32 fifo_control; |
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u32 fifo_status; |
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u32 int_mask; |
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u32 int_status; |
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}; |
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struct dvc_ctlr { |
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u32 ctrl1; /* 00: DVC_CTRL_REG1 */ |
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u32 ctrl2; /* 04: DVC_CTRL_REG2 */ |
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u32 ctrl3; /* 08: DVC_CTRL_REG3 */ |
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u32 status; /* 0C: DVC_STATUS_REG */ |
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u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ |
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u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ |
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u32 reserved_0[2]; /* 18: */ |
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u32 req; /* 20: DVC_REQ_REGISTER */ |
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u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ |
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u32 reserved_1[6]; /* 28: */ |
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u32 cnfg; /* 40: DVC_I2C_CNFG */ |
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u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ |
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u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ |
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u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ |
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u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ |
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u32 reserved_2[2]; /* 54: */ |
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u32 i2c_status; /* 5C: DVC_I2C_STATUS */ |
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struct i2c_control control; /* 60 ~ 78 */ |
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}; |
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struct i2c_ctlr { |
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u32 cnfg; /* 00: I2C_I2C_CNFG */ |
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u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ |
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u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ |
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u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ |
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u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ |
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u32 reserved_0[2]; /* 14: */ |
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u32 status; /* 1C: I2C_I2C_STATUS */ |
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u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ |
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u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ |
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u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ |
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u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ |
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u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ |
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u32 reserved_1[2]; /* 34: */ |
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u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ |
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u32 reserved_2[4]; /* 40: */ |
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struct i2c_control control; /* 50 ~ 68 */ |
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}; |
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/* bit fields definitions for IO Packet Header 1 format */ |
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#define PKT_HDR1_PROTOCOL_SHIFT 4 |
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#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) |
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#define PKT_HDR1_CTLR_ID_SHIFT 12 |
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#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) |
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#define PKT_HDR1_PKT_ID_SHIFT 16 |
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#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) |
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#define PROTOCOL_TYPE_I2C 1 |
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/* bit fields definitions for IO Packet Header 2 format */ |
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#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 |
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#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) |
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/* bit fields definitions for IO Packet Header 3 format */ |
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#define PKT_HDR3_READ_MODE_SHIFT 19 |
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#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) |
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#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 |
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#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) |
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#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 |
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#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ |
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(1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) |
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/* I2C_CNFG */ |
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#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 |
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#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) |
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#define I2C_CNFG_PACKET_MODE_SHIFT 10 |
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#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) |
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/* I2C_SL_CNFG */ |
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#define I2C_SL_CNFG_NEWSL_SHIFT 2 |
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#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) |
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/* I2C_FIFO_STATUS */ |
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#define TX_FIFO_FULL_CNT_SHIFT 0 |
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#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) |
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#define TX_FIFO_EMPTY_CNT_SHIFT 4 |
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#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) |
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/* I2C_INTERRUPT_STATUS */ |
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#define I2C_INT_XFER_COMPLETE_SHIFT 7 |
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#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) |
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#define I2C_INT_NO_ACK_SHIFT 3 |
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#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) |
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#define I2C_INT_ARBITRATION_LOST_SHIFT 2 |
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#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) |
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#endif |
@ -0,0 +1,569 @@ |
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/*
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* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. |
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* Copyright (c) 2010-2011 NVIDIA Corporation |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <fdtdec.h> |
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#include <i2c.h> |
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#include <asm/io.h> |
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#include <asm/arch/clk_rst.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/funcmux.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/arch/tegra_i2c.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static unsigned int i2c_bus_num; |
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/* Information about i2c controller */ |
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struct i2c_bus { |
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int id; |
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enum periph_id periph_id; |
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int speed; |
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int pinmux_config; |
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struct i2c_control *control; |
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struct i2c_ctlr *regs; |
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int is_dvc; /* DVC type, rather than I2C */ |
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int inited; /* bus is inited */ |
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}; |
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static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; |
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static void set_packet_mode(struct i2c_bus *i2c_bus) |
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{ |
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u32 config; |
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config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; |
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if (i2c_bus->is_dvc) { |
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struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; |
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writel(config, &dvc->cnfg); |
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} else { |
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writel(config, &i2c_bus->regs->cnfg); |
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/*
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* program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe |
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* issues, i.e., some slaves may be wrongly detected. |
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*/ |
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setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); |
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} |
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} |
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static void i2c_reset_controller(struct i2c_bus *i2c_bus) |
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{ |
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/* Reset I2C controller. */ |
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reset_periph(i2c_bus->periph_id, 1); |
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/* re-program config register to packet mode */ |
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set_packet_mode(i2c_bus); |
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} |
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static void i2c_init_controller(struct i2c_bus *i2c_bus) |
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{ |
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/*
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* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 |
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* here, in section 23.3.1, but in fact we seem to need a factor of |
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* 16 to get the right frequency. |
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*/ |
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clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, |
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i2c_bus->speed * 2 * 8); |
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/* Reset I2C controller. */ |
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i2c_reset_controller(i2c_bus); |
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/* Configure I2C controller. */ |
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if (i2c_bus->is_dvc) { /* only for DVC I2C */ |
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struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; |
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setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); |
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} |
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funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); |
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} |
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static void send_packet_headers( |
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struct i2c_bus *i2c_bus, |
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struct i2c_trans_info *trans, |
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u32 packet_id) |
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{ |
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u32 data; |
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/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ |
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data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; |
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data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; |
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data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; |
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writel(data, &i2c_bus->control->tx_fifo); |
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debug("pkt header 1 sent (0x%x)\n", data); |
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/* prepare header2 */ |
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data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; |
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writel(data, &i2c_bus->control->tx_fifo); |
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debug("pkt header 2 sent (0x%x)\n", data); |
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/* prepare IO specific header: configure the slave address */ |
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data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; |
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/* Enable Read if it is not a write transaction */ |
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if (!(trans->flags & I2C_IS_WRITE)) |
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data |= PKT_HDR3_READ_MODE_MASK; |
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/* Write I2C specific header */ |
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writel(data, &i2c_bus->control->tx_fifo); |
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debug("pkt header 3 sent (0x%x)\n", data); |
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} |
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static int wait_for_tx_fifo_empty(struct i2c_control *control) |
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{ |
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u32 count; |
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int timeout_us = I2C_TIMEOUT_USEC; |
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while (timeout_us >= 0) { |
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count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) |
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>> TX_FIFO_EMPTY_CNT_SHIFT; |
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if (count == I2C_FIFO_DEPTH) |
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return 1; |
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udelay(10); |
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timeout_us -= 10; |
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} |
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return 0; |
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} |
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static int wait_for_rx_fifo_notempty(struct i2c_control *control) |
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{ |
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u32 count; |
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int timeout_us = I2C_TIMEOUT_USEC; |
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while (timeout_us >= 0) { |
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count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) |
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>> TX_FIFO_FULL_CNT_SHIFT; |
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if (count) |
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return 1; |
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udelay(10); |
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timeout_us -= 10; |
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} |
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return 0; |
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} |
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static int wait_for_transfer_complete(struct i2c_control *control) |
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{ |
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int int_status; |
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int timeout_us = I2C_TIMEOUT_USEC; |
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while (timeout_us >= 0) { |
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int_status = readl(&control->int_status); |
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if (int_status & I2C_INT_NO_ACK_MASK) |
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return -int_status; |
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if (int_status & I2C_INT_ARBITRATION_LOST_MASK) |
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return -int_status; |
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if (int_status & I2C_INT_XFER_COMPLETE_MASK) |
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return 0; |
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udelay(10); |
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timeout_us -= 10; |
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} |
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return -1; |
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} |
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static int send_recv_packets(struct i2c_bus *i2c_bus, |
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struct i2c_trans_info *trans) |
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{ |
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struct i2c_control *control = i2c_bus->control; |
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u32 int_status; |
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u32 words; |
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u8 *dptr; |
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u32 local; |
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uchar last_bytes; |
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int error = 0; |
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int is_write = trans->flags & I2C_IS_WRITE; |
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/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ |
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int_status = readl(&control->int_status); |
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writel(int_status, &control->int_status); |
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send_packet_headers(i2c_bus, trans, 1); |
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words = DIV_ROUND_UP(trans->num_bytes, 4); |
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last_bytes = trans->num_bytes & 3; |
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dptr = trans->buf; |
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while (words) { |
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u32 *wptr = (u32 *)dptr; |
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if (is_write) { |
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/* deal with word alignment */ |
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if ((unsigned)dptr & 3) { |
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memcpy(&local, dptr, sizeof(u32)); |
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writel(local, &control->tx_fifo); |
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debug("pkt data sent (0x%x)\n", local); |
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} else { |
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writel(*wptr, &control->tx_fifo); |
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debug("pkt data sent (0x%x)\n", *wptr); |
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} |
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if (!wait_for_tx_fifo_empty(control)) { |
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error = -1; |
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goto exit; |
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} |
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} else { |
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if (!wait_for_rx_fifo_notempty(control)) { |
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error = -1; |
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goto exit; |
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} |
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/*
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* for the last word, we read into our local buffer, |
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* in case that caller did not provide enough buffer. |
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*/ |
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local = readl(&control->rx_fifo); |
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if ((words == 1) && last_bytes) |
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memcpy(dptr, (char *)&local, last_bytes); |
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else if ((unsigned)dptr & 3) |
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memcpy(dptr, &local, sizeof(u32)); |
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else |
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*wptr = local; |
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debug("pkt data received (0x%x)\n", local); |
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} |
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words--; |
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dptr += sizeof(u32); |
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} |
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if (wait_for_transfer_complete(control)) { |
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error = -1; |
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goto exit; |
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} |
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return 0; |
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exit: |
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/* error, reset the controller. */ |
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i2c_reset_controller(i2c_bus); |
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return error; |
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} |
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static int tegra2_i2c_write_data(u32 addr, u8 *data, u32 len) |
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{ |
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int error; |
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struct i2c_trans_info trans_info; |
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trans_info.address = addr; |
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trans_info.buf = data; |
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trans_info.flags = I2C_IS_WRITE; |
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trans_info.num_bytes = len; |
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trans_info.is_10bit_address = 0; |
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error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); |
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if (error) |
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debug("tegra2_i2c_write_data: Error (%d) !!!\n", error); |
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return error; |
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} |
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static int tegra2_i2c_read_data(u32 addr, u8 *data, u32 len) |
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{ |
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int error; |
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struct i2c_trans_info trans_info; |
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trans_info.address = addr | 1; |
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trans_info.buf = data; |
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trans_info.flags = 0; |
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trans_info.num_bytes = len; |
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trans_info.is_10bit_address = 0; |
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error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); |
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if (error) |
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debug("tegra2_i2c_read_data: Error (%d) !!!\n", error); |
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return error; |
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} |
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#ifndef CONFIG_OF_CONTROL |
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#error "Please enable device tree support to use this driver" |
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#endif |
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unsigned int i2c_get_bus_speed(void) |
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{ |
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return i2c_controllers[i2c_bus_num].speed; |
||||
} |
||||
|
||||
int i2c_set_bus_speed(unsigned int speed) |
||||
{ |
||||
struct i2c_bus *i2c_bus; |
||||
|
||||
i2c_bus = &i2c_controllers[i2c_bus_num]; |
||||
i2c_bus->speed = speed; |
||||
i2c_init_controller(i2c_bus); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) |
||||
{ |
||||
i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); |
||||
|
||||
/*
|
||||
* We don't have a binding for pinmux yet. Leave it out for now. So |
||||
* far no one needs anything other than the default. |
||||
*/ |
||||
i2c_bus->pinmux_config = FUNCMUX_DEFAULT; |
||||
i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); |
||||
i2c_bus->periph_id = clock_decode_periph_id(blob, node); |
||||
|
||||
/*
|
||||
* We can't specify the pinmux config in the fdt, so I2C2 will not |
||||
* work on Seaboard. It normally has no devices on it anyway. |
||||
* You could add in this little hack if you need to use it. |
||||
* The correct solution is a pinmux binding in the fdt. |
||||
* |
||||
* if (i2c_bus->periph_id == PERIPH_ID_I2C2) |
||||
* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; |
||||
*/ |
||||
if (i2c_bus->periph_id == -1) |
||||
return -FDT_ERR_NOTFOUND; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Process a list of nodes, adding them to our list of I2C ports. |
||||
* |
||||
* @param blob fdt blob |
||||
* @param node_list list of nodes to process (any <=0 are ignored) |
||||
* @param count number of nodes to process |
||||
* @param is_dvc 1 if these are DVC ports, 0 if standard I2C |
||||
* @return 0 if ok, -1 on error |
||||
*/ |
||||
static int process_nodes(const void *blob, int node_list[], int count, |
||||
int is_dvc) |
||||
{ |
||||
struct i2c_bus *i2c_bus; |
||||
int i; |
||||
|
||||
/* build the i2c_controllers[] for each controller */ |
||||
for (i = 0; i < count; i++) { |
||||
int node = node_list[i]; |
||||
|
||||
if (node <= 0) |
||||
continue; |
||||
|
||||
i2c_bus = &i2c_controllers[i]; |
||||
i2c_bus->id = i; |
||||
|
||||
if (i2c_get_config(blob, node, i2c_bus)) { |
||||
printf("i2c_init_board: failed to decode bus %d\n", i); |
||||
return -1; |
||||
} |
||||
|
||||
i2c_bus->is_dvc = is_dvc; |
||||
if (is_dvc) { |
||||
i2c_bus->control = |
||||
&((struct dvc_ctlr *)i2c_bus->regs)->control; |
||||
} else { |
||||
i2c_bus->control = &i2c_bus->regs->control; |
||||
} |
||||
debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", |
||||
is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, |
||||
i2c_bus->periph_id, i2c_bus->speed); |
||||
i2c_init_controller(i2c_bus); |
||||
debug("ok\n"); |
||||
i2c_bus->inited = 1; |
||||
|
||||
/* Mark position as used */ |
||||
node_list[i] = -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Sadly there is no error return from this function */ |
||||
void i2c_init_board(void) |
||||
{ |
||||
int node_list[TEGRA_I2C_NUM_CONTROLLERS]; |
||||
const void *blob = gd->fdt_blob; |
||||
int count; |
||||
|
||||
/* First get the normal i2c ports */ |
||||
count = fdtdec_find_aliases_for_id(blob, "i2c", |
||||
COMPAT_NVIDIA_TEGRA20_I2C, node_list, |
||||
TEGRA_I2C_NUM_CONTROLLERS); |
||||
if (process_nodes(blob, node_list, count, 0)) |
||||
return; |
||||
|
||||
/* Now look for dvc ports */ |
||||
count = fdtdec_add_aliases_for_id(blob, "i2c", |
||||
COMPAT_NVIDIA_TEGRA20_DVC, node_list, |
||||
TEGRA_I2C_NUM_CONTROLLERS); |
||||
if (process_nodes(blob, node_list, count, 1)) |
||||
return; |
||||
} |
||||
|
||||
void i2c_init(int speed, int slaveaddr) |
||||
{ |
||||
/* This will override the speed selected in the fdt for that port */ |
||||
debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); |
||||
i2c_set_bus_speed(speed); |
||||
} |
||||
|
||||
/* i2c write version without the register address */ |
||||
int i2c_write_data(uchar chip, uchar *buffer, int len) |
||||
{ |
||||
int rc; |
||||
|
||||
debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); |
||||
debug("write_data: "); |
||||
/* use rc for counter */ |
||||
for (rc = 0; rc < len; ++rc) |
||||
debug(" 0x%02x", buffer[rc]); |
||||
debug("\n"); |
||||
|
||||
/* Shift 7-bit address over for lower-level i2c functions */ |
||||
rc = tegra2_i2c_write_data(chip << 1, buffer, len); |
||||
if (rc) |
||||
debug("i2c_write_data(): rc=%d\n", rc); |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
/* i2c read version without the register address */ |
||||
int i2c_read_data(uchar chip, uchar *buffer, int len) |
||||
{ |
||||
int rc; |
||||
|
||||
debug("inside i2c_read_data():\n"); |
||||
/* Shift 7-bit address over for lower-level i2c functions */ |
||||
rc = tegra2_i2c_read_data(chip << 1, buffer, len); |
||||
if (rc) { |
||||
debug("i2c_read_data(): rc=%d\n", rc); |
||||
return rc; |
||||
} |
||||
|
||||
debug("i2c_read_data: "); |
||||
/* reuse rc for counter*/ |
||||
for (rc = 0; rc < len; ++rc) |
||||
debug(" 0x%02x", buffer[rc]); |
||||
debug("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Probe to see if a chip is present. */ |
||||
int i2c_probe(uchar chip) |
||||
{ |
||||
int rc; |
||||
uchar reg; |
||||
|
||||
debug("i2c_probe: addr=0x%x\n", chip); |
||||
reg = 0; |
||||
rc = i2c_write_data(chip, ®, 1); |
||||
if (rc) { |
||||
debug("Error probing 0x%x.\n", chip); |
||||
return 1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int i2c_addr_ok(const uint addr, const int alen) |
||||
{ |
||||
/* We support 7 or 10 bit addresses, so one or two bytes each */ |
||||
return alen == 1 || alen == 2; |
||||
} |
||||
|
||||
/* Read bytes */ |
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
uint offset; |
||||
int i; |
||||
|
||||
debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", |
||||
chip, addr, len); |
||||
if (!i2c_addr_ok(addr, alen)) { |
||||
debug("i2c_read: Bad address %x.%d.\n", addr, alen); |
||||
return 1; |
||||
} |
||||
for (offset = 0; offset < len; offset++) { |
||||
if (alen) { |
||||
uchar data[alen]; |
||||
for (i = 0; i < alen; i++) { |
||||
data[alen - i - 1] = |
||||
(addr + offset) >> (8 * i); |
||||
} |
||||
if (i2c_write_data(chip, data, alen)) { |
||||
debug("i2c_read: error sending (0x%x)\n", |
||||
addr); |
||||
return 1; |
||||
} |
||||
} |
||||
if (i2c_read_data(chip, buffer + offset, 1)) { |
||||
debug("i2c_read: error reading (0x%x)\n", addr); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Write bytes */ |
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
uint offset; |
||||
int i; |
||||
|
||||
debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", |
||||
chip, addr, len); |
||||
if (!i2c_addr_ok(addr, alen)) { |
||||
debug("i2c_write: Bad address %x.%d.\n", addr, alen); |
||||
return 1; |
||||
} |
||||
for (offset = 0; offset < len; offset++) { |
||||
uchar data[alen + 1]; |
||||
for (i = 0; i < alen; i++) |
||||
data[alen - i - 1] = (addr + offset) >> (8 * i); |
||||
data[alen] = buffer[offset]; |
||||
if (i2c_write_data(chip, data, alen + 1)) { |
||||
debug("i2c_write: error sending (0x%x)\n", addr); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_I2C_MULTI_BUS) |
||||
/*
|
||||
* Functions for multiple I2C bus handling |
||||
*/ |
||||
unsigned int i2c_get_bus_num(void) |
||||
{ |
||||
return i2c_bus_num; |
||||
} |
||||
|
||||
int i2c_set_bus_num(unsigned int bus) |
||||
{ |
||||
if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited) |
||||
return -1; |
||||
i2c_bus_num = bus; |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
Loading…
Reference in new issue