Since the IOP480 (PPC401/3 variant from PLX) is only used on 2 boards that are not actively maintained, lets remove support for it completely. This way the ppc4xx code will get a bit cleaner. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Marek Vasut <marex@denx.de>master
Stefan Roese
13 years ago
committed by
Tom Rini
parent
f2760c4acd
commit
99bcad1809
@ -1,254 +0,0 @@ |
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/*
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* (C) Copyright 2000-2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <commproc.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <watchdog.h> |
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#include <serial.h> |
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#include <linux/compiler.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_IOP480 |
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#define SPU_BASE 0x40000000 |
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#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ |
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#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ |
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#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ |
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#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ |
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#define spu_BRateDivh 0x10 /* Baud rate divisor high */ |
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#define spu_BRateDivl 0x14 /* Baud rate divisor low */ |
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#define spu_CtlReg 0x18 /* Control Register */ |
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#define spu_RxCmd 0x1c /* Rx Command Register */ |
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#define spu_TxCmd 0x20 /* Tx Command Register */ |
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#define spu_RxBuff 0x24 /* Rx data buffer */ |
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#define spu_TxBuff 0x24 /* Tx data buffer */ |
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/*-----------------------------------------------------------------------------+
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| Line Status Register. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncLSRport1 0x40000000 |
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#define asyncLSRport1set 0x40000004 |
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#define asyncLSRDataReady 0x80 |
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#define asyncLSRFramingError 0x40 |
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#define asyncLSROverrunError 0x20 |
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#define asyncLSRParityError 0x10 |
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#define asyncLSRBreakInterrupt 0x08 |
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#define asyncLSRTxHoldEmpty 0x04 |
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#define asyncLSRTxShiftEmpty 0x02 |
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/*-----------------------------------------------------------------------------+
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| Handshake Status Register. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncHSRport1 0x40000008 |
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#define asyncHSRport1set 0x4000000c |
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#define asyncHSRDsr 0x80 |
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#define asyncLSRCts 0x40 |
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/*-----------------------------------------------------------------------------+
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| Control Register. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncCRport1 0x40000018 |
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#define asyncCRNormal 0x00 |
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#define asyncCRLoopback 0x40 |
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#define asyncCRAutoEcho 0x80 |
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#define asyncCRDtr 0x20 |
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#define asyncCRRts 0x10 |
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#define asyncCRWordLength7 0x00 |
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#define asyncCRWordLength8 0x08 |
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#define asyncCRParityDisable 0x00 |
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#define asyncCRParityEnable 0x04 |
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#define asyncCREvenParity 0x00 |
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#define asyncCROddParity 0x02 |
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#define asyncCRStopBitsOne 0x00 |
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#define asyncCRStopBitsTwo 0x01 |
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#define asyncCRDisableDtrRts 0x00 |
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/*-----------------------------------------------------------------------------+
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| Receiver Command Register. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncRCRport1 0x4000001c |
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#define asyncRCRDisable 0x00 |
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#define asyncRCREnable 0x80 |
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#define asyncRCRIntDisable 0x00 |
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#define asyncRCRIntEnabled 0x20 |
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#define asyncRCRDMACh2 0x40 |
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#define asyncRCRDMACh3 0x60 |
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#define asyncRCRErrorInt 0x10 |
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#define asyncRCRPauseEnable 0x08 |
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/*-----------------------------------------------------------------------------+
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| Transmitter Command Register. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncTCRport1 0x40000020 |
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#define asyncTCRDisable 0x00 |
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#define asyncTCREnable 0x80 |
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#define asyncTCRIntDisable 0x00 |
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#define asyncTCRIntEnabled 0x20 |
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#define asyncTCRDMACh2 0x40 |
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#define asyncTCRDMACh3 0x60 |
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#define asyncTCRTxEmpty 0x10 |
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#define asyncTCRErrorInt 0x08 |
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#define asyncTCRStopPause 0x04 |
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#define asyncTCRBreakGen 0x02 |
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/*-----------------------------------------------------------------------------+
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| Miscellanies defines. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncTxBufferport1 0x40000024 |
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#define asyncRxBufferport1 0x40000024 |
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#define asyncDLABLsbport1 0x40000014 |
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#define asyncDLABMsbport1 0x40000010 |
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#define asyncXOFFchar 0x13 |
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#define asyncXONchar 0x11 |
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/*
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* Minimal serial functions needed to use one of the SMC ports |
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* as serial console interface. |
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*/ |
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static int iop480_serial_init(void) |
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{ |
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unsigned short br_reg; |
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br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); |
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/*
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* Init onboard UART |
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*/ |
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out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ |
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out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ |
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out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ |
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out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ |
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out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ |
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out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ |
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out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ |
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in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ |
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return (0); |
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} |
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static void iop480_serial_setbrg(void) |
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{ |
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unsigned short br_reg; |
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br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); |
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out_8((u8 *)SPU_BASE + spu_BRateDivl, |
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(br_reg & 0x00ff)); /* Set baud rate divisor... */ |
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out_8((u8 *)SPU_BASE + spu_BRateDivh, |
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((br_reg & 0xff00) >> 8)); /* ... */ |
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} |
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static void iop480_serial_putc(const char c) |
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{ |
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if (c == '\n') |
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serial_putc ('\r'); |
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/* load status from handshake register */ |
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if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) |
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out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ |
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out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */ |
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while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) { |
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if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) |
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out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ |
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} |
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} |
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static void iop480_serial_puts(const char *s) |
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{ |
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while (*s) { |
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serial_putc (*s++); |
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} |
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} |
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static int iop480_serial_getc(void) |
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{ |
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unsigned char status = 0; |
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while (1) { |
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status = in_8((u8 *)asyncLSRport1); |
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if ((status & asyncLSRDataReady) != 0x0) { |
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break; |
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} |
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if ((status & ( asyncLSRFramingError | |
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asyncLSROverrunError | |
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asyncLSRParityError | |
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asyncLSRBreakInterrupt )) != 0) { |
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(void) out_8((u8 *)asyncLSRport1, |
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asyncLSRFramingError | |
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asyncLSROverrunError | |
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asyncLSRParityError | |
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asyncLSRBreakInterrupt ); |
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} |
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} |
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return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1)); |
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} |
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static int iop480_serial_tstc(void) |
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{ |
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unsigned char status; |
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status = in_8((u8 *)asyncLSRport1); |
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if ((status & asyncLSRDataReady) != 0x0) { |
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return (1); |
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} |
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if ((status & ( asyncLSRFramingError | |
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asyncLSROverrunError | |
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asyncLSRParityError | |
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asyncLSRBreakInterrupt )) != 0) { |
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(void) out_8((u8 *)asyncLSRport1, |
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asyncLSRFramingError | |
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asyncLSROverrunError | |
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asyncLSRParityError | |
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asyncLSRBreakInterrupt); |
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} |
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return 0; |
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} |
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static struct serial_device iop480_serial_drv = { |
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.name = "iop480_serial", |
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.start = iop480_serial_init, |
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.stop = NULL, |
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.setbrg = iop480_serial_setbrg, |
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.putc = iop480_serial_putc, |
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.puts = iop480_serial_puts, |
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.getc = iop480_serial_getc, |
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.tstc = iop480_serial_tstc, |
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}; |
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void iop480_serial_initialize(void) |
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{ |
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serial_register(&iop480_serial_drv); |
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} |
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__weak struct serial_device *default_serial_console(void) |
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{ |
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return &iop480_serial_drv; |
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} |
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#endif /* CONFIG_IOP480 */ |
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@ -1,203 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ |
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#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */ |
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#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#define CONFIG_CPUCLOCK 66 |
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#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) |
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#define CONFIG_BAUDRATE 9600 |
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
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#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#define CONFIG_PHY_ADDR 0 /* PHY address */ |
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#define CONFIG_IPADDR 10.0.18.222 |
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#define CONFIG_SERVERIP 10.0.18.190 |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_IRQ |
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#define CONFIG_CMD_ELF |
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#define CONFIG_CMD_ASKENV |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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/* The following table includes the supported baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } |
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
|
||||||
#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ |
|
||||||
#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ |
|
||||||
/*
|
|
||||||
* The following defines are added for buggy IOP480 byte interface. |
|
||||||
* All other boards should use the standard values (CPCI405 etc.) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */ |
|
||||||
#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */ |
|
||||||
#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
|
||||||
|
|
||||||
#if 1 /* Use NVRAM for environment variables */ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* NVRAM organization |
|
||||||
*/ |
|
||||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
|
||||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */ |
|
||||||
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ |
|
||||||
#define CONFIG_ENV_SIZE 0x0400 /* Size of Environment vars */ |
|
||||||
#define CONFIG_ENV_ADDR \ |
|
||||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
|
||||||
#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/ |
|
||||||
|
|
||||||
#else /* Use FLASH for environment variables */ |
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ |
|
||||||
#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
|
||||||
|
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PCI stuff |
|
||||||
*/ |
|
||||||
#define CONFIG_PCI /* include pci support */ |
|
||||||
#undef CONFIG_PCI_PNP |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_TULIP |
|
||||||
|
|
||||||
#define CONFIG_SYS_ETH_DEV_FN 0x0000 |
|
||||||
#define CONFIG_SYS_ETH_IOBASE 0x0fff0000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller: |
|
||||||
* |
|
||||||
* BR0/1 and OR0/1 (FLASH) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
|
||||||
#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */ |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
@ -1,194 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2001 |
|
||||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ |
|
||||||
#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
|
||||||
#define CONFIG_SYS_LDSCRIPT "board/esd/dasa_sim/u-boot.lds" |
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
|
||||||
|
|
||||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
|
||||||
|
|
||||||
#define CONFIG_CPUCLOCK 66 |
|
||||||
#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 9600 |
|
||||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
|
||||||
#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */ |
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
|
|
||||||
#define CONFIG_IPADDR 10.0.18.222 |
|
||||||
#define CONFIG_SERVERIP 10.0.18.190 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_BSP |
|
||||||
|
|
||||||
|
|
||||||
#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
|
|
||||||
#define CONFIG_SOFT_I2C /* Software I2C support enabled */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
|
||||||
|
|
||||||
/* The following table includes the supported baudrates */ |
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
|
||||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
|
||||||
|
|
||||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 |
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
|
||||||
#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ |
|
||||||
#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ |
|
||||||
/*
|
|
||||||
* The following defines are added for buggy IOP480 byte interface. |
|
||||||
* All other boards should use the standard values (CPCI405 etc.) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */ |
|
||||||
#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */ |
|
||||||
#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ |
|
||||||
#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
|
||||||
|
|
||||||
#if 0 |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ |
|
||||||
#else |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PCI stuff |
|
||||||
*/ |
|
||||||
#define CONFIG_PCI /* include pci support */ |
|
||||||
#undef CONFIG_PCI_PNP |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_TULIP |
|
||||||
|
|
||||||
#define CONFIG_SYS_ETH_DEV_FN 0x0000 |
|
||||||
#define CONFIG_SYS_ETH_IOBASE 0x0fff0000 |
|
||||||
#define CONFIG_SYS_PCI9054_DEV_FN 0x0800 |
|
||||||
#define CONFIG_SYS_PCI9054_IOBASE 0x0eff0000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller: |
|
||||||
* |
|
||||||
* BR0/1 and OR0/1 (FLASH) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
Loading…
Reference in new issue