This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ. Signed-off-by: Lukas Roggli <lukas.roggli@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>master
Heiko Schocher
15 years ago
committed by
Wolfgang Denk
parent
62ddcf05e7
commit
9a276bb093
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* Copyright (C) 2007 Logic Product Development, Inc. |
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* Peter Barada <peterb@logicpd.com> |
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* |
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* Copyright (C) 2007 MontaVista Software, Inc. |
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* Anton Vorontsov <avorontsov@ru.mvista.com> |
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* |
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* (C) Copyright 2008 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* (C) Copyright 2010 |
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* Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_QE /* Has QE */ |
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#define CONFIG_MPC832x /* MPC832x CPU specific */ |
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#define CONFIG_TUXA1 /* TUXA1 board specific */ |
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#define CONFIG_HOSTNAME tuxa1 |
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#define CONFIG_KM_BOARD_NAME "tuxa1" |
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#define CONFIG_SYS_TEXT_BASE 0xF0000000 |
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#define CONFIG_KM_DEF_NETDEV \ |
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"netdev=eth0\0" |
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#define CONFIG_KM_DEF_ROOTPATH \ |
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"rootpath=/opt/eldk/ppc_8xx\0" |
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/* include common defines/options for all 83xx Keymile boards */ |
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#include "km83xx-common.h" |
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#define CONFIG_MISC_INIT_R |
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/*
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* System IO Config |
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*/ |
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#define CONFIG_SYS_SICRL SICRL_IRQ_CKS |
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/*
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* Hardware Reset Configuration Word |
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*/ |
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#define CONFIG_SYS_HRCW_LOW (\ |
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
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HRCWL_DDR_TO_SCB_CLK_2X1 | \
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HRCWL_CSB_TO_CLKIN_2X1 | \
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HRCWL_CORE_TO_CSB_2_5X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X3) |
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#define CONFIG_SYS_HRCW_HIGH (\ |
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HRCWH_PCI_AGENT | \
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HRCWH_PCI_ARBITER_DISABLE | \
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_NORMAL) |
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f |
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ |
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SDRAM_CFG_32_BE | \
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SDRAM_CFG_2T_EN | \
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SDRAM_CFG_SREN) |
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
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#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
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(0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) |
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ |
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CSCONFIG_ODT_WR_CFG | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10) |
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#define CONFIG_SYS_DDR_MODE 0x47860252 |
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#define CONFIG_SYS_DDR_MODE2 0x8080c000 |
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#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ |
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(2 << TIMING_CFG1_WRREC_SHIFT) | \
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(6 << TIMING_CFG1_REFREC_SHIFT) | \
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(2 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(2 << TIMING_CFG1_PRETOACT_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
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#define CONFIG_SYS_PIGGY_BASE 0xE8000000 |
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#define CONFIG_SYS_PIGGY_SIZE 128 |
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#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ |
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#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ |
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#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ |
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#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ |
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/* EEprom support */ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
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/*
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* Local Bus Configuration & Clock Setup |
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*/ |
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) |
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#define CONFIG_SYS_LBC_LBCR 0x00000000 |
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/*
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* Init Local Bus Memory Controller: |
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* |
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* Bank Bus Machine PortSz Size Device |
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* ---- --- ------- ------ ----- ------ |
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* 2 Local GPCM 8 bit 256MB LPXF |
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* 3 Local GPCM 8 bit 256MB PINC2 |
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* |
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*/ |
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/*
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* LPXF on the local bus CS2 |
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* Window base at flash base |
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* Window size: 256 MB |
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*/ |
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE |
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) |
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ |
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V) |
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ |
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_2 | \
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(OR_GPCM_TRLX & \
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(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
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OR_GPCM_EAD) |
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/*
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* PINC2 on the local bus CS3 |
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* Access window base at PINC2 base |
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* Window size: 256 MB |
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*/ |
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE |
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) |
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ |
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V) |
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ |
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OR_GPCM_CSNT | \
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(OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
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(~OR_GPCM_XACS)) | /* XACS = 0 */ \
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(OR_GPCM_SCY_2 & \
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(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
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OR_GPCM_TRLX) |
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ |
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0x0000c000 | \
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MxMR_WLFx_2X) |
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/*
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* MMU Setup |
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*/ |
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/* LPXF: icache cacheable, but dcache-inhibit and guarded */ |
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ |
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BATL_MEMCOHERENCE) |
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ |
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BATU_VS | BATU_VP) |
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
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#ifdef CONFIG_PCI |
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/* PCI MEM space: cacheable */ |
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#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
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#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
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#define CFG_DBAT6L CFG_IBAT6L |
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#define CFG_DBAT6U CFG_IBAT6U |
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/* PCI MMIO space: cache-inhibit and guarded */ |
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#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
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#define CFG_DBAT7L CFG_IBAT7L |
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#define CFG_DBAT7U CFG_IBAT7U |
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#else /* CONFIG_PCI */ |
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/* PINC2: icache cacheable, but dcache-inhibit and guarded */ |
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ |
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BATL_MEMCOHERENCE) |
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ |
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BATU_VS | BATU_VP) |
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
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#define CONFIG_SYS_IBAT7L (0) |
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#define CONFIG_SYS_IBAT7U (0) |
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
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#endif /* CONFIG_PCI */ |
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#endif /* __CONFIG_H */ |
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