Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Patch by Jon Loeliger, 16 Jul 2004:

Browse Source 
- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
master
wdenk 21 years ago
parent 281e00a3be
commit 9aea95307f
19 changed files with 1630 additions and 1483 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 12
      CHANGELOG
  2. 2
      board/mpc8540ads/flash.c
  3. 320
      board/mpc8540ads/init.S
  4. 159
      board/mpc8540ads/mpc8540ads.c
  5. 2
      board/mpc8560ads/flash.c
  6. 320
      board/mpc8560ads/init.S
  7. 162
      board/mpc8560ads/mpc8560ads.c
  8. 2
      board/stxgp3/flash.c
  9. 299
      board/stxgp3/init.S
  10. 144
      board/stxgp3/stxgp3.c
  11. 58
      cpu/mpc85xx/pci.c
  12. 396
      cpu/mpc85xx/spd_sdram.c
  13. 36
      cpu/mpc85xx/start.S
  14. 6
      cpu/mpc85xx/traps.c
  15. 554
      doc/README.mpc85xxads
  16. 123
      include/configs/MPC8540ADS.h
  17. 117
      include/configs/MPC8560ADS.h
  18. 196
      include/configs/stxgp3.h
  19. 15
      include/e500.h

12
CHANGELOG
Unescape View File

@ -2,6 +2,18 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
* Patch by Sascha Hauer, 28 Jun:
- add generic support for Motorola i.MX architecture
- add support for mx1ads, mx1fs2 and scb9328 boards

2
board/mpc8540ads/flash.c
Unescape View File

@ -86,14 +86,12 @@ unsigned long flash_init (void)
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */

320
board/mpc8540ads/init.S
Unescape View File

@ -1,26 +1,26 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@ -29,6 +29,24 @@
#include <config.h>
#include <mpc85xx.h>
/*
* TLB0 and TLB1 Entries
*
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
* these TLB entries are established.
*
* The TLB entries for DDR are dynamically setup in spd_sdram()
* and use TLB1 Entries 8 through 15 as needed according to the
* size of DDR memory.
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
* MAS2: epn, sharen, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
mflr r1 ; \
bl 0f ;
@ -38,119 +56,174 @@
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
/* Number of entries in the following table */
.long 0x0c
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if defined(CFG_FLASH_PORT_WIDTH_16)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
#if !defined(CONFIG_SPD_EEPROM)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,9,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
/*
* Number of TLB0 and TLB1 entries in the following table
*/
.long 13
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/*
* RapidIO MMU for 512M
* Two entries, 10 and 11
* TLB0 4K Non-cacheable, guarded
* 0xff700000 4K Initial CCSRBAR mapping
*
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
#else
#error("Update the number of table entries in tlb1_entry")
#endif
/*
* TLB0 16K Cacheable, non-guarded
* 0xd001_0000 16K Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
* controler and real memory have been configured.
*
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
.long TLB1_MAS0(1,10,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,11,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
.long TLB1_MAS0(1, 1, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
.long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
.long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 8, 9: 128M DDR
* 0x00000000 64M DDR System memory
* 0x04000000 64M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 9, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/*
@ -184,13 +257,8 @@ tlb1_entry:
/*
* This is not so much the SDRAM map as it is the whole localbus map.
*/
#if !defined(CONFIG_RAM_AS_FLASH)
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))

159
board/mpc8540ads/mpc8540ads.c
Unescape View File

@ -26,6 +26,7 @@
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
@ -36,6 +37,7 @@ extern void ddr_enable_ecc(unsigned int dram_size);
extern long int spd_sdram(void);
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
@ -43,7 +45,7 @@ long int fixed_sdram(void);
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xffffffdf; /* disable master abort */
@ -63,6 +65,11 @@ int checkboard (void)
printf(" PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init();
return 0;
}
@ -114,55 +121,79 @@ initdram(int board_type)
/*
* Initialize SDRAM memory on the Local Bus.
* Initialize Local Bus
*/
void sdram_init (void)
void
local_bus_init(void)
{
#if !defined(CONFIG_RAM_AS_FLASH)
sys_info_t sysinfo;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
puts (" SDRAM: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* LocalBus SDRAM is not emulating flash.
*/
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
/*
* Fix Local Bus clock glitch. Errata LBC11.
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is less than 66Mhz, use bypass mode,
* otherwise use DLL.
* lcrr is the local-bus clock ratio register.
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
get_sys_info (&sysinfo);
if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
volatile ccsr_gur_t *gur = &immap->im_gur;
uint pvr = get_pvr ();
uint pvr = get_pvr();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
/* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay (200);
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
udelay(200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
asm ("sync;isync;msync");
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm("sync;isync;msync");
}
}
/*
* Initialize SDRAM memory on the Local Bus.
*/
void
sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts(" SDRAM: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
@ -170,46 +201,44 @@ void sdram_init (void)
lbc->or2 = CFG_OR2_PRELIM;
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
asm ("msync");
asm("msync");
lbc->lsrt = CFG_LBC_LSRT;
lbc->mrtpr = CFG_LBC_MRTPR;
asm ("sync");
asm("sync");
/*
* Configure the SDRAM controller.
*/
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
#endif
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
}
@ -282,3 +311,41 @@ long int fixed_sdram (void)
return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
} },
{ }
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}

2
board/mpc8560ads/flash.c
Unescape View File

@ -86,14 +86,12 @@ unsigned long flash_init (void)
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */

320
board/mpc8560ads/init.S
Unescape View File

@ -1,26 +1,26 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@ -29,6 +29,24 @@
#include <config.h>
#include <mpc85xx.h>
/*
* TLB0 and TLB1 Entries
*
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
* these TLB entries are established.
*
* The TLB entries for DDR are dynamically setup in spd_sdram()
* and use TLB1 Entries 8 through 15 as needed according to the
* size of DDR memory.
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
* MAS2: epn, sharen, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
mflr r1 ; \
bl 0f ;
@ -38,119 +56,174 @@
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
/* Number of entries in the following table */
.long 0x0c
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if defined(CFG_FLASH_PORT_WIDTH_16)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
#if !defined(CONFIG_SPD_EEPROM)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,9,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
/*
* Number of TLB0 and TLB1 entries in the following table
*/
.long 13
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/*
* RapidIO MMU for 512M
* Two entries, 10 and 11
* TLB0 4K Non-cacheable, guarded
* 0xff700000 4K Initial CCSRBAR mapping
*
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
#else
#error("Update the number of table entries in tlb1_entry")
#endif
/*
* TLB0 16K Cacheable, non-guarded
* 0xd001_0000 16K Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
* controler and real memory have been configured.
*
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
.long TLB1_MAS0(1,10,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,11,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
.long TLB1_MAS0(1, 1, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
.long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
.long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 7: 16K Non-cacheable, guarded
* 0xf8000000 16K BCSR registers
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 8, 9: 128M DDR
* 0x00000000 64M DDR System memory
* 0x04000000 64M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 9, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/*
@ -184,13 +257,8 @@ tlb1_entry:
/*
* This is not so much the SDRAM map as it is the whole localbus map.
*/
#if !defined(CONFIG_RAM_AS_FLASH)
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))

162
board/mpc8560ads/mpc8560ads.c
Unescape View File

@ -26,6 +26,7 @@
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
@ -38,6 +39,7 @@ extern void ddr_enable_ecc(unsigned int dram_size);
extern long int spd_sdram(void);
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
@ -209,10 +211,11 @@ typedef struct bcsr_ {
volatile unsigned char bcsr5;
} bcsr_t;
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xffffffdf; /* disable master abort */
@ -247,6 +250,7 @@ void reset_phy (void)
#endif /* CONFIG_MII */
}
int checkboard (void)
{
puts("Board: ADS\n");
@ -257,6 +261,12 @@ int checkboard (void)
#else
printf(" PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init();
return 0;
}
@ -308,55 +318,79 @@ initdram(int board_type)
/*
* Initialize SDRAM memory on the Local Bus.
* Initialize Local Bus
*/
void sdram_init (void)
void
local_bus_init(void)
{
#if !defined(CONFIG_RAM_AS_FLASH)
sys_info_t sysinfo;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
puts (" SDRAM: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* LocalBus SDRAM is not emulating flash.
*/
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
/*
* Fix Local Bus clock glitch. Errata LBC11.
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is less than 66Mhz, use bypass mode,
* otherwise use DLL.
* lcrr is the local-bus clock ratio register.
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
get_sys_info (&sysinfo);
if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
volatile ccsr_gur_t *gur = &immap->im_gur;
uint pvr = get_pvr ();
uint pvr = get_pvr();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
/* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay (200);
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
udelay(200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
asm ("sync;isync;msync");
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm("sync;isync;msync");
}
}
/*
* Initialize SDRAM memory on the Local Bus.
*/
void
sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts(" SDRAM: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
@ -364,46 +398,44 @@ void sdram_init (void)
lbc->or2 = CFG_OR2_PRELIM;
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
asm ("msync");
asm("msync");
lbc->lsrt = CFG_LBC_LSRT;
lbc->mrtpr = CFG_LBC_MRTPR;
asm ("sync");
asm("sync");
/*
* Configure the SDRAM controller.
*/
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm ("sync");
asm("sync");
*sdram_addr = 0xff;
ppcDcbf ((unsigned long) sdram_addr);
udelay (100);
#endif
ppcDcbf((unsigned long) sdram_addr);
udelay(100);
}
@ -476,3 +508,41 @@ long int fixed_sdram (void)
return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
} },
{ }
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}

2
board/stxgp3/flash.c
Unescape View File

@ -92,14 +92,12 @@ unsigned long flash_init (void)
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */

299
board/stxgp3/init.S
Unescape View File

@ -1,10 +1,11 @@
/*
* Copyright (C) 2003 Embedded Edge, LLC
* Copyright (C) 2004 Embedded Edge, LLC
* Dan Malek <dan@embeddededge.com>
* Copied from ADS85xx.
* Updates for Silicon Tx GP3 8560. We only support 32-bit flash
* and DDR with SPD EEPROM configuration.
*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
@ -34,6 +35,24 @@
#include <config.h>
#include <mpc85xx.h>
/*
* TLB0 and TLB1 Entries
*
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
* these TLB entries are established.
*
* The TLB entries for DDR are dynamically setup in spd_sdram()
* and use TLB1 Entries 8 through 15 as needed according to the
* size of DDR memory.
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
* MAS2: epn, sharen, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
mflr r1 ; \
bl 0f ;
@ -43,111 +62,225 @@
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
/* If RAMBOOT, we are testing and the BDI has set up
* much of the MMU already.
* TLB 4,5 SDRAM
* TLB 15 is default CCSRBAR.
*/
.long 0x09 /* the following data table uses a few of 16 TLB entries */
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
/*
* Number of TLB0 and TLB1 entries in the following table
*/
.long 13
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/*
* TLB0 4K Non-cacheable, guarded
* 0xff700000 4K Initial CCSRBAR mapping
*
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#error("Update the number of table entries in tlb1_entry")
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
/*
* TLB0 16K Cacheable, non-guarded
* 0xd001_0000 16K Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
* controler and real memory have been configured.
*
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff000000 16M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
.long TLB1_MAS0(1, 1, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
.long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
.long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 6: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 7: 16K Non-cacheable, guarded
* 0xfc000000 16K Configuration Latch register
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 8, 9: 128M DDR
* 0x00000000 64M DDR System memory
* 0x04000000 64M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 9, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/* LAW(Local Access Window) configuration:
* 0000_0000-8000_0000: Up to 2G DDR
* f000_0000-f3ff_ffff: PCI(256M)
* f400_0000-f7ff_ffff: RapidIO(128M)
* f800_0000-ffff_ffff: localbus(128M)
* f800_0000-fbff_ffff: LBC SDRAM(64M)
* fc00_0000-fcff_ffff: LBC BCSR (1M, Chip select 1)
* fdf0_0000-fdff_ffff: CCSRBAR(1M)
* ff00_0000-ffff_ffff: Flash(16M)
* We don't need a local window for CCSRBAR and flash because they
* reside in their default mapped spaces.
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xfc00_0000 0xfc00_ffff Config Latch 64K
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G)) & ~LAWAR_EN)
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#if !defined(CONFIG_RAM_AS_FLASH)
/*
* This is not so much the SDRAM map as it is the whole localbus map.
*/
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
/*
* Rapid IO at 0xc000_0000 for 512 M
*/
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x03
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
.long 0x05
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
.long LAWBAR4,LAWAR4
entry_end

144
board/stxgp3/stxgp3.c
Unescape View File

@ -32,6 +32,7 @@
extern long int spd_sdram (void);
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
@ -198,7 +199,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
static uint64_t next_led_update;
static uint led_bit;
int board_pre_init (void)
int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
@ -209,7 +211,8 @@ int board_pre_init (void)
return 0;
}
void reset_phy (void)
void
reset_phy(void)
{
volatile uint *blatch;
@ -243,25 +246,10 @@ void reset_phy (void)
#endif
}
int checkboard (void)
int
checkboard(void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: Silicon Tx GPPP 8560 Board\n");
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
@ -285,13 +273,15 @@ show_activity(int flag)
next_led_update += (get_tbclk() / 4);
}
long int initdram (int board_type)
long int
initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur= &immap->im_gur;
uint temp_ddrdll = 0;
@ -299,54 +289,15 @@ long int initdram (int board_type)
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
}
#endif
dram_size = spd_sdram ();
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
/* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
return dram_size;
@ -387,37 +338,40 @@ int testdram (void)
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_stxgp3_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
} },
{ }
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_stxgp3_config_table,
#endif
};
#endif /* CONFIG_PCI */
void
pci_init_board(void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
return ( CFG_SDRAM_SIZE * 1024 * 1024);
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */

58
cpu/mpc85xx/pci.c
Unescape View File

@ -32,34 +32,10 @@
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER}},
{}
};
#endif
struct pci_controller local_hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxads_config_table,
#endif
};
void pci_init_board (void)
void
pci_mpc85xx_init(struct pci_controller *hose)
{
struct pci_controller *hose = (struct pci_controller *) &local_hose;
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_pcix_t *pcix = &immap->im_pcix;
u16 reg16;
@ -67,27 +43,33 @@ void pci_init_board (void)
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region (hose->regions + 0,
pci_set_region(hose->regions + 0,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region (hose->regions + 1,
pci_set_region(hose->regions + 1,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 2;
pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
pci_setup_indirect(hose,
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
@ -108,8 +90,8 @@ void pci_init_board (void)
/*
* Hose scan.
*/
pci_register_hose (hose);
hose->last_busno = pci_hose_scan (hose);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */

396
cpu/mpc85xx/spd_sdram.c
Unescape View File

@ -30,133 +30,171 @@
#ifdef CONFIG_SPD_EEPROM
#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1) + 1)
long int spd_sdram(void) {
#if defined(CONFIG_DDR_ECC)
extern void dma_init(void);
extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
#endif
#ifndef CFG_READ_SPD
#define CFG_READ_SPD i2c_read
#endif
/*
* Convert picoseconds into clock cycles (rounding up if needed).
*/
int
picos_to_clk(int picos)
{
int clks;
clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
clks++;
}
return clks;
}
unsigned int
banksize(unsigned char row_dens)
{
return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
}
long int
spd_sdram(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
spd_eeprom_t spd;
unsigned int memsize,tmp,tmp1,tmp2;
unsigned tmp, tmp1;
unsigned int memsize;
unsigned int tlb_size;
unsigned int law_size;
unsigned char caslat;
unsigned int ram_tlb_index;
unsigned int ram_tlb_address;
i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
if ( spd.nrows > 2 ) {
printf("DDR:Only two chip selects are supported on ADS.\n");
if (spd.nrows > 2) {
puts("DDR:Only two chip selects are supported on ADS.\n");
return 0;
}
if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
printf("DDR:Row or Col number unsupported.\n");
if (spd.nrow_addr < 12
|| spd.nrow_addr > 14
|| spd.ncol_addr < 8
|| spd.ncol_addr > 11) {
puts("DDR:Row or Col number unsupported.\n");
return 0;
}
ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
debug ("\n");
debug ("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
debug ("cs0_config = 0x%08x\n",ddr->cs0_config);
if ( spd.nrows == 2 ) {
ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
debug ("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
debug ("cs1_config = 0x%08x\n",ddr->cs1_config);
ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs0_config = ( 1 << 31
| (spd.nrow_addr - 12) << 8
| (spd.ncol_addr - 8) );
debug("\n");
debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
debug("cs0_config = 0x%08x\n",ddr->cs0_config);
if (spd.nrows == 2) {
ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
| ((banksize(spd.row_dens) >> 23) - 1) );
ddr->cs1_config = ( 1<<31
| (spd.nrow_addr-12) << 8
| (spd.ncol_addr-8) );
debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
debug("cs1_config = 0x%08x\n",ddr->cs1_config);
}
memsize = spd.nrows * (4 * spd.row_dens);
if( spd.mem_type != 0x07 ) {
printf("No DDR module found!\n");
if (spd.mem_type != 0x07) {
puts("No DDR module found!\n");
return 0;
}
/*
* Figure out memory size in Megabytes.
*/
memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
/*
* First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
*/
law_size = 19 + __ilog2(memsize);
/*
* Determine size of each TLB1 entry.
*/
switch (memsize) {
case 16:
tmp = 7; /* TLB size */
tmp1 = 1; /* TLB entry number */
tmp2 = 23; /* Local Access Window size */
break;
case 32:
tmp = 7;
tmp1 = 2;
tmp2 = 24;
tlb_size = BOOKE_PAGESZ_16M;
break;
case 64:
tmp = 8;
tmp1 = 1;
tmp2 = 25;
break;
case 128:
tmp = 8;
tmp1 = 2;
tmp2 = 26;
tlb_size = BOOKE_PAGESZ_64M;
break;
case 256:
tmp = 9;
tmp1 = 1;
tmp2 = 27;
break;
case 512:
tmp = 9;
tmp1 = 2;
tmp2 = 28;
break;
case 1024:
tmp = 10;
tmp1 = 1;
tmp2 = 29;
case 2048:
tlb_size = BOOKE_PAGESZ_256M;
break;
default:
printf ("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
return 0;
break;
}
/* configure DDR TLB to TLB1 Entry 4,5 */
mtspr(MAS0, TLB1_MAS0(1,4,0));
mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0));
debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
& 0xfffff),0,0,0,0,0,0,0,0));
debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
if(tmp1 == 2) {
mtspr(MAS0, TLB1_MAS0(1,5,0));
mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
/*
* Configure DDR TLB1 entries.
* Starting at TLB1 8, use no more than 8 TLB1 entries.
*/
ram_tlb_index = 8;
ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize * 1024 * 1024)
&& ram_tlb_index < 16) {
mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
0, 0, 0, 0, 0, 0, 0, 0));
mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
asm volatile("isync;msync;tlbwe;isync");
debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0));
debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0));
debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
debug("DDR:MAS2=0x%08x\n",
TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
0, 0, 0, 0, 0, 0, 0, 0));
debug("DDR:MAS3=0x%08x\n",
TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
ram_tlb_index++;
}
#if defined(CONFIG_RAM_AS_FLASH)
ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
debug ("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2);
debug ("DDR:LARAR2=0x%08x\n",ecm->lawar2);
#else
/*
* Set up LAWBAR for all of DDR.
*/
ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
debug ("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1);
debug ("DDR:LARAR1=0x%08x\n",ecm->lawar1);
#endif
tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
debug ("DDR:Module maximum data rate is: %dMhz\n",tmp);
ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
/* find the largest CAS */
/*
* find the largest CAS
*/
if(spd.cas_lat & 0x40) {
caslat = 7;
} else if (spd.cas_lat & 0x20) {
@ -172,46 +210,65 @@ long int spd_sdram(void) {
} else if (spd.cas_lat & 0x01) {
caslat = 1;
} else {
printf("DDR:no valid CAS Latency information.\n");
puts("DDR:no valid CAS Latency information.\n");
return 0;
}
tmp1 = get_bus_freq(0)/1000000;
if(tmp1<230 && tmp1>=90 && tmp>=230) {
tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+ (spd.clk_cycle & 0x0f));
debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
tmp1 = get_bus_freq(0) / 1000000;
if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
/* 90~230 range, treated as DDR 200 */
if(spd.clk_cycle3 == 0xa0) caslat -= 2;
else if(spd.clk_cycle2 == 0xa0) caslat--;
} else if(tmp1<280 && tmp1>=230 && tmp>=280) {
if (spd.clk_cycle3 == 0xa0)
caslat -= 2;
else if(spd.clk_cycle2 == 0xa0)
caslat--;
} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
/* 230-280 range, treated as DDR 266 */
if(spd.clk_cycle3 == 0x75) caslat -= 2;
else if(spd.clk_cycle2 == 0x75) caslat--;
} else if(tmp1<350 && tmp1>=280 && tmp>=350) {
if (spd.clk_cycle3 == 0x75)
caslat -= 2;
else if (spd.clk_cycle2 == 0x75)
caslat--;
} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
/* 280~350 range, treated as DDR 333 */
if(spd.clk_cycle3 == 0x60) caslat -= 2;
else if(spd.clk_cycle2 == 0x60) caslat--;
} else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
printf("DDR:platform frequency is not fit for DDR rate\n");
if (spd.clk_cycle3 == 0x60)
caslat -= 2;
else if (spd.clk_cycle2 == 0x60)
caslat--;
} else if (tmp1 < 90 || tmp1 >= 350) {
/* DDR rate out-of-range */
puts("DDR:platform frequency is not fit for DDR rate\n");
return 0;
}
/* note: caslat must also be programmed into ddr->sdram_mode
register */
/* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use
conservative value here */
ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
((caslat & 0x07)<< 16 ) | \
(((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
( 0x300 ) | \
((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
debug ("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1);
/*
* note: caslat must also be programmed into ddr->sdram_mode
* register.
*
* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
* use conservative value here.
*/
ddr->timing_cfg_1 =
(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
((caslat & 0x07) << 16 ) |
(((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
( 0x300 ) |
((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
ddr->timing_cfg_2 = 0x00000800;
debug ("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2);
/* only DDR I is supported, DDR I and II have different mode-register-set definition */
debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
/*
* Only DDR I is supported
* DDR I and II have different mode-register-set definition
*/
/* burst length is always 4 */
switch(caslat) {
case 2:
@ -227,53 +284,58 @@ long int spd_sdram(void) {
ddr->sdram_mode = 0x32; /* 3.0 */
break;
default:
printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
return 0;
}
debug ("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode);
debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
switch(spd.refresh) {
case 0x00:
case 0x80:
tmp = ns2clk(15625);
tmp = picos_to_clk(15625000);
break;
case 0x01:
case 0x81:
tmp = ns2clk(3900);
tmp = picos_to_clk(3900000);
break;
case 0x02:
case 0x82:
tmp = ns2clk(7800);
tmp = picos_to_clk(7800000);
break;
case 0x03:
case 0x83:
tmp = ns2clk(31300);
tmp = picos_to_clk(31300000);
break;
case 0x04:
case 0x84:
tmp = ns2clk(62500);
tmp = picos_to_clk(62500000);
break;
case 0x05:
case 0x85:
tmp = ns2clk(125000);
tmp = picos_to_clk(125000000);
break;
default:
tmp = 0x512;
break;
}
/* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
/*
* Set BSTOPRE to 0x100 for page mode
* If auto-charge is used, set BSTOPRE = 0
*/
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
debug ("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval);
debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
/* is this an ECC DDR chip? */
/*
* Is this an ECC DDR chip?
*/
#if defined(CONFIG_DDR_ECC)
if(spd.config == 0x02) {
if (spd.config == 0x02) {
ddr->err_disable = 0x0000000d;
ddr->err_sbe = 0x00ff0000;
}
debug ("DDR:err_disable=0x%08x\n",ddr->err_disable);
debug ("DDR:err_sbe=0x%08x\n",ddr->err_sbe);
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
asm("sync;isync;msync");
@ -287,7 +349,8 @@ long int spd_sdram(void) {
ddr->sdram_clk_cntl = 0x83000000;
#endif
/* Figure out the settings for the sdram_cfg register. Build up
/*
* Figure out the settings for the sdram_cfg register. Build up
* the entire register in 'tmp' before writing since the write into
* the register will actually enable the memory controller, and all
* settings must be done before enabling.
@ -298,7 +361,8 @@ long int spd_sdram(void) {
*/
tmp = 0xc2000000;
/* sdram_cfg[3] = RD_EN - registered DIMM enable
/*
* sdram_cfg[3] = RD_EN - registered DIMM enable
* A value of 0x26 indicates micron registered DIMMS (micron.com)
*/
if (spd.mod_attr == 0x26) {
@ -306,13 +370,14 @@ long int spd_sdram(void) {
}
#if defined(CONFIG_DDR_ECC)
/* If the user wanted ECC (enabled via sdram_cfg[2]) */
/*
* If the user wanted ECC (enabled via sdram_cfg[2])
*/
if (spd.config == 0x02) {
tmp |= 0x20000000;
}
#endif
/*
* REV1 uses 1T timing.
* REV2 may use 1T or 2T as configured by the user.
@ -333,12 +398,71 @@ long int spd_sdram(void) {
ddr->sdram_cfg = tmp;
asm("sync;isync;msync");
udelay(500);
debug ("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg);
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
return (memsize*1024*1024);
return memsize * 1024 * 1024;
}
#endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC)
/*
* Initialize all of memory for ECC, then enable errors.
*/
void
ddr_enable_ecc(unsigned int dram_size)
{
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) {
ppcDcbz((unsigned long) p);
}
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) {
ppcDcbf((unsigned long) p);
}
}
/* 8K */
dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
/* 16K */
dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
/* 32K */
dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
/* 64K */
dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
/* 128k */
dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
/* 256k */
dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
/* 512k */
dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
/* 1M */
dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
/* 2M */
dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
/* 4M */
dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
}
/*
* Enable errors for ECC.
*/
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif /* CONFIG_DDR_ECC */

36
cpu/mpc85xx/start.S
Unescape View File

@ -218,7 +218,19 @@ _start_e500:
mtspr MMUCSR0, r2
isync
/* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
/*
* Invalidate all TLB0 entries.
*/
li r3,4
li r4,0
tlbivax r4,r3
/*
* To avoid REV1 Errata CPU6 issues, make sure
* the instruction following tlbivax is not a store.
*/
/*
* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
* 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
* region before we can access any CCSR registers such as L2
* registers, Local Access Registers,etc. We will also re-allocate
@ -230,7 +242,7 @@ _start_e500:
*/
bl tlb1_entry
mr r5,r0
li r1,0x000f /* max 16 TLB1 entries */
li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
mtctr r1
lwzu r4,0(r5) /* how many TLB1 entries we actually use */
@ -273,15 +285,6 @@ _start_e500:
isync
#endif
/* invalidate all TLB0 entries */
li r3,4
li r4,0
tlbivax r4,r3
/*
* To avoid REV1 Errata CPU6 issues, make sure
* the instruction following tlbivax is not a store.
*/
/* set up local access windows, defined at board/<boardname>/init.S */
lis r7,CFG_CCSRBAR@h
@ -289,21 +292,12 @@ _start_e500:
bl law_entry
mr r6,r0
#if defined(CONFIG_RAM_AS_FLASH)
li r1,0x0006
#else
li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */
#endif
li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
mtctr r1
lwzu r5,0(r6) /* how many windows we actually use */
#if defined(CONFIG_RAM_AS_FLASH)
li r2,0x0c48
li r1,0x0c50
#else
li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
li r1,0x0c30
#endif
0: cmpwi r5,0
beq 1f

6
cpu/mpc85xx/traps.c
Unescape View File

@ -46,9 +46,10 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0;
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
/*
* End of memory as shown by board info and determined by DDR setup.
*/
#define END_OF_MEM (CFG_SDRAM_SIZE * 1024 * 1024)
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
static __inline__ void set_tsr(unsigned long val)
@ -82,6 +83,7 @@ extern void do_bedbug_breakpoint(struct pt_regs *);
void
print_backtrace(unsigned long *sp)
{
DECLARE_GLOBAL_DATA_PTR;
int cnt = 0;
unsigned long i;

554
doc/README.mpc85xxads
Unescape View File

@ -1,17 +1,47 @@
Motorola MPC8540ADS and MPC8560ADS board
Xianghua Xiao(X.Xiao@motorola.com)
Created 10/15/03
Created 10/15/03 Xianghua Xiao
Updated 13-July-2004 Jon Loeliger
-----------------------------------------
0. Toolchain
The Binutils in ELDK toolchain 3.0 or earlier does not support the
MPC85xx chip. You need use the newest binutils-2.14.tar.bz2 from
http://ftp.gnu.org/gnu/binutils.
The Binutils in current ELDK toolchain will not support MPC85xx
chip. You need use the newest binutils-2.14.tar.bz2 from
http://ftp.gnu.org/gnu/binutils.
The 8540/8560 ADS code base is known to compile using:
gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
1. SWITCH SETTINGS & JUMPERS
1.1 First, make sure the board default setting is consistent with the document
1.0 Nomenclature
For some reason, the HW designers describe the switch settings
in terms of 0 and 1, and then map that to physical switches where
the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
Luckily, we're SW types and virtual settings are handled daily.
The switches for the Rev A board are numbered differently than
for the Pilot board. Oh yeah.
Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
bits may contribute to signals that are numbered based at 0,
and some of those signals may be high-bit-number-0 too. Heed
well the names and labels and do not get confused.
"Off" == 1
"On" == 0
SW18 is switch 18 as silk-screened onto the board.
SW4[8] is the bit labled 8 on Switch 4.
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
1.1 For the MPC85xxADS Pilot Board
First, make sure the board default setting is consistent with the document
shipped with your board. Then apply the following changes:
SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
@ -22,16 +52,53 @@ http://ftp.gnu.org/gnu/binutils.
SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
J1 = "Enable Prog" (Make sure your flash is programmable for development)
1.2 If you want to test PCI functionality with a 33Mhz PCI card, you will
If you want to test PCI functionality with a 33Mhz PCI card, you will
have to change the system clock from the default 66Mhz to 33Mhz by
setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
double your platform clock(SW6) because the system clock is now only
half of its original value. For example, if at 66MHz your system
clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
1.3 SW6 is a very important switch, it decides your platform clock and CPU
clock based on the on-board system clock(default 66MHz). Check the
document along with your board for details.
SW17[8] ------+ SW6
SW15[1] ----+ | [0:1]
V V V V
33MHz 1 1 1 0
66MHz 0 0 0 1
Hmmm... That SW6 setting description is incomplete but it works.
1.3 For the MPC85xxADS Rev A Board
As shipped, the board should be a 33MHz PCI bus with a CPU Clock
rate of 825 +/- fuzz:
Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
For 33MHz PCI, the switch settings should be like this:
SW18[7:1] = 0100001 = M==33 => 33MHz
SW18[8] = 1 => PWD Divider == 16
SW16[1:2] = 11 => N == 16 as PWD==1
Use the magical formula:
Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz
SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
For 66MHz PCI, the switch settings should be like this:
SW18[7:1] = 0100001 = M==33 => 33MHz
SW18[8] = 0 => PWD Divider == 1
SW16[1:2] = 01 => N == 8 as PWD == 0
Use the magical formula:
Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz
SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
2. MEMORY MAP TO WORK WITH LINUX KERNEL
@ -77,13 +144,6 @@ http://ftp.gnu.org/gnu/binutils.
CONFIG_DDR_ECC only for ECC DDR module
CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
stability.
CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into
localbus SDRAM and treat localbus SDRAM as a
flash. We use this memory based U-Boot
before flash is working while Metrowerks and
Windriver are still working on their
flash/JTAG tools. if you can program the
flash directly, undef this.
Other than the above definitions, the rest in the config files are
straightforward.
@ -139,25 +199,26 @@ straightforward.
4.5 Reflash U-Boot with a BDI-2000
BDI> erase 0xFFF80000 0x2000 0x40
BDI> erase 0xFFF80000 0x4000 0x20
BDI> prog 0xfff80000 u-boot.bin.8560ads
BDI> verify
5. Screen dump:
5.1 MPC8540ADS board
U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33)
5. Screen dump MPC8540ADS board
Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
Board: Motorola MPC8540ADS Board
CPU: 792 MHz
CCB: 264 MHz
DDR: 132 MHz
LBC: 66 MHz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25)
Freescale PowerPC
Core: E500, Version: 2.0, (0x80200020)
System: 8540, Version: 2.0, (0x80300020)
Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
Board: ADS
PCI1: 32 bit, 66 MHz (compiled)
I2C: ready
DRAM: DDR module detected, total size:128MB.
128 MB
DRAM: Initializing
SDRAM: 64 MB
DDR: 256 MB
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment
@ -165,9 +226,13 @@ L2 cache enabled: 256KB
In: serial
Out: serial
Err: serial
Net: MOTOROLA ETHERNE
Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
MOTO ENET2: PHY is Davicom DM9161E (181b881)
MOTO ENET0, MOTO ENET1, MOTO ENET2
Hit any key to stop autoboot: 0
MPC8540ADS=> fli
=>
=> fli
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
Size: 16 MB in 64 Sectors
@ -185,410 +250,51 @@ Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
MPC8540ADS=> imi ff000000
## Checking Image at ff000000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 800594 Bytes = 781.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
MPC8540ADS=> bdinfo
=> bdinfo
memstart = 0x00000000
memsize = 0x08000000
memsize = 0x10000000
flashstart = 0xFF000000
flashsize = 0x01000000
flashoffset = 0x00000000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFDF00000
bootflags = 0x40003F80
intfreq = 792 MHz
busfreq = 264 MHz
ethaddr = 00:01:AF:07:9B:8A
eth1addr = 00:01:AF:07:9B:8B
eth2addr = 00:01:AF:07:9B:8C
IP addr = 10.82.0.105
immr_base = 0xE0000000
bootflags = 0xE4013F80
intfreq = 825 MHz
busfreq = 330 MHz
ethaddr = 00:E0:0C:00:00:FD
eth1addr = 00:E0:0C:00:01:FD
eth2addr = 00:E0:0C:00:02:FD
IP addr = 192.168.1.253
baudrate = 115200 bps
MPC8540ADS=> printenv
bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
bootcmd=bootm 0xff300000 0xff700000
bootdelay=3
baudrate=115200
loads_echo=1
ethaddr=00:01:af:07:9b:8a
eth1addr=00:01:af:07:9b:8b
eth2addr=00:01:af:07:9b:8c
ipaddr=10.82.0.105
serverip=163.12.64.52
rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
gatewayip=10.82.1.254
netmask=255.255.254.0
hostname=MPC8560ADS_PILOT_003
bootfile=pImage
stdin=serial
stdout=serial
stderr=serial
Environment size: 560/8188 bytes
MPC8540ADS=> bootm ff000000
## Booting image at ff000000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 800594 Bytes = 781.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
mpc85xx_init(): exit
id mach(): done
MMU:enter
Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
MMU:hw init
MMU:mapin
MMU:mapin_ram done
MMU:setio
MMU:exit
Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #1 Wed Oct 15 09:05:42 CDT 2003
setup_arch: enter
setup_arch: bootmem
mpc85xx_setup_arch
Host Bridge Vendor ID = 1057
Host Bridge Device ID = 3
Host Bridge header = 0
arch: exit
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
openpic: enter
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
openpic: timer
openpic: external
openpic: spurious
openpic: exit
time_init: decrementer frequency = 33.000000 MHz
Calibrating delay loop... 226.09 BogoMIPS
Memory: 127488k available (1344k kernel code, 448k data, 248k init, 0k highmem)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
pty: 256 Unix98 ptys configured
Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
ttyS00 at 0xfdf04500 (irq = 90) is a 16550A
ttyS01 at 0xfdf04600 (irq = 0) is a 16550A
eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
Copyright (c) 1999-2003 Intel Corporation.
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 8192)
IP-Config: Complete:
device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
host=mpc8540ads-003, domain=, nis-domain=(none),
bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 163.12.64.52
Looking up port of RPC 100005/1 on 163.12.64.52
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 248k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: rp_filter.
Disable TCP/IP Explicit Congestion Notification: done.
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Cleaning: /tmp /var/lock /var/run.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
mpc8540ads-003 login: root
Last login: Thu Jan 1 00:00:07 1970 on console
Linux mpc8540ads-003 2.4.21-rc5 #1 Wed Oct 15 09:05:42 CDT 2003 ppc unknown
root@mpc8540ads-003:~# ls
21142.o aa e100.o hello.o mii.o timer.o
root@mpc8540ads-003:~# /sbin/ifconfig
eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4576 errors:0 dropped:0 overruns:0 frame:0
TX packets:2587 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:100
RX bytes:4457023 (4.2 Mb) TX bytes:437770 (427.5 Kb)
Base address:0x4000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
root@mpc8540ads-003:~# ping 163.12.64.52
PING 163.12.64.52 (163.12.64.52): 56 data bytes
64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.2 ms
64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
--- 163.12.64.52 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.1/0.1/0.2 ms
root@mpc8540ads-003:~#
5.2 MPC8560ADS board
U-Boot 1.0.0-pre (Oct 15 2003 - 13:42:04)
Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
Board: Motorola MPC8560ADS Board
CPU: 792 MHz
CCB: 264 MHz
DDR: 132 MHz
LBC: 66 MHz
CPM: 264 Mhz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
I2C: ready
DRAM: DDR module detected, total size:128MB.
128 MB
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: MOTOROLA ETHERNE
Hit any key to stop autoboot: 3
MPC8560ADS=> bdinfo
memstart = 0x00000000
memsize = 0x08000000
flashstart = 0xFF000000
flashsize = 0x01000000
flashoffset = 0x00000000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFDF00000
bootflags = 0x00000000
vco = 528 MHz
sccfreq = 132 MHz
brgfreq = 132 MHz
intfreq = 792 MHz
cpmfreq = 264 MHz
busfreq = 264 MHz
ethaddr = 00:01:AF:07:9B:8A
eth1addr = 00:01:AF:07:9B:8B
eth2addr = 00:01:AF:07:9B:8C
IP addr = 10.82.0.105
baudrate = 115200 bps
MPC8560ADS=> printenv
bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
bootcmd=bootm 0xff400000 0xff700000
bootdelay=3
=> printenv
bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
bootdelay=10
baudrate=115200
loads_echo=1
ethaddr=00:01:af:07:9b:8a
eth1addr=00:01:af:07:9b:8b
eth2addr=00:01:af:07:9b:8c
ipaddr=10.82.0.105
serverip=163.12.64.52
rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
gatewayip=10.82.1.254
netmask=255.255.254.0
hostname=MPC8560ADS_PILOT_003
bootfile=pImage
ethaddr=00:E0:0C:00:00:FD
eth1addr=00:E0:0C:00:01:FD
eth2addr=00:E0:0C:00:02:FD
ipaddr=192.168.1.253
serverip=192.168.1.1
rootpath=/nfsroot
gatewayip=192.168.1.1
netmask=255.255.255.0
hostname=unknown
bootfile=your.uImage
loadaddr=200000
netdev=eth0
consoledev=ttyS0
ramdiskaddr=400000
ramdiskfile=your.ramdisk.u-boot
stdin=serial
stdout=serial
stderr=serial
ethact=MOTO ENET0
Environment size: 560/8188 bytes
MPC8560ADS=> fli
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
Size: 16 MB in 64 Sectors
Sector Start Addresses:
FF000000 FF040000 FF080000 FF0C0000 FF100000
FF140000 FF180000 FF1C0000 FF200000 FF240000
FF280000 FF2C0000 FF300000 FF340000 FF380000
FF3C0000 FF400000 FF440000 FF480000 FF4C0000
FF500000 FF540000 FF580000 FF5C0000 FF600000
FF640000 FF680000 FF6C0000 FF700000 FF740000
FF780000 FF7C0000 FF800000 FF840000 FF880000
FF8C0000 FF900000 FF940000 FF980000 FF9C0000
FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
MPC8560ADS=> imi ff100000
## Checking Image at ff100000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 755361 Bytes = 737.7 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
MPC8560ADS=> tftp 1000000 pImage.dracom.public
TFTP from server 163.12.64.52; our IP address is 10.82.0.105; sending through gateway 10.82.1.254
Filename 'pImage.dracom.public'.
Load address: 0x1000000
Loading: *#################################################################
#################################################################
##################
done
Bytes transferred = 755425 (b86e1 hex)
MPC8560ADS=> bootm ff100000
## Booting image at ff100000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 755361 Bytes = 737.7 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
mpc85xx_init(): exit
id mach(): done
MMU:enter
Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
MMU:hw init
MMU:mapin
MMU:mapin_ram done
MMU:setio
MMU:exit
Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #2 Wed Oct 15 09:13:46 CDT 2003
setup_arch: enter
setup_arch: bootmem
mpc85xx_setup_arch
Host Bridge Vendor ID = 1057
Host Bridge Device ID = 3
Host Bridge header = 0
arch: exit
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
openpic: enter
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
openpic: timer
openpic: external
openpic: spurious
openpic: exit
time_init: decrementer frequency = 33.000000 MHz
Calibrating delay loop... 226.09 BogoMIPS
Memory: 127624k available (1276k kernel code, 384k data, 236k init, 0k highmem)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
CPM UART driver version 0.01
ttyS0 on SCC1 at 0x8000, BRG1
UART interrupt installed(40)
pty: 256 Unix98 ptys configured
eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
Copyright (c) 1999-2003 Intel Corporation.
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 8192)
IP-Config: Complete:
device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
host=mpc8560ads-003, domain=, nis-domain=(none),
bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 163.12.64.52
Looking up port of RPC 100005/1 on 163.12.64.52
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 236k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: FAILED
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Cleaning: /tmp /var/lock /var/run.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
mpc8560ads-003 login: root
Last login: Thu Jan 1 00:00:05 1970 on console
Linux mpc8560ads-003 2.4.21-rc5 #2 Wed Oct 15 09:13:46 CDT 2003 ppc unknown
root@mpc8560ads-003:~# ls
21142.o aa e100.o hello.o mii.o timer.o
root@mpc8560ads-003:~# cd /
root@mpc8560ads-003:/# ls
bin boot dev etc home lib mnt opt proc root sbin tmp usr var
root@mpc8560ads-003:/# /sbin/ifconfig
eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4608 errors:0 dropped:0 overruns:0 frame:0
TX packets:2610 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:100
RX bytes:4465943 (4.2 Mb) TX bytes:440944 (430.6 Kb)
Base address:0x4000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
root@mpc8560ads-003:/# ping 163.12.64.52
PING 163.12.64.52 (163.12.64.52): 56 data bytes
64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
--- 163.12.64.52 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.1/0.1/0.1 ms
root@mpc8560ads-003:/#
Environment size: 1020/8188 bytes

123
include/configs/MPC8540ADS.h
Unescape View File

@ -49,12 +49,6 @@
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/*
* Use Localbus SDRAM to emulate flash before we can program the flash.
* Normally you need a flash-boot image(u-boot.bin).
* If unsure #undef this.
*/
#undef CONFIG_RAM_AS_FLASH
/*
* sysclk for MPC85xx
@ -64,24 +58,17 @@
* 66000000
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here. The board, however, can run and
* defaults to 66Mhz. In any event, this value must match the settings
* of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
*
* SW17[8] ------+ SW6
* SW15[1] ----+ | [0:1]
* V V V V
* 33MHz 1 1 1 0
* 66MHz 0 0 0 1
* is likely the desired value here, so that is now the default.
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#if !defined(CONFIG_SPD_EEPROM)
#define CONFIG_DDR_SETTING /* manually set up DDR parameters */
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
@ -104,27 +91,42 @@
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
#endif
/*
* SDRAM on the Local Bus
*/
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
#else
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#endif
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
#else /* Boot from real Flash */
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
#endif
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
@ -142,20 +144,9 @@
#undef CFG_RAMBOOT
#endif
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
#if defined(CONFIG_DDR_SETTING)
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
#endif
/*
* Local Bus Definitions
@ -244,28 +235,27 @@
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/
| CFG_LBC_LSDMR_OP_NORMAL)
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#else
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#endif
/*
* 32KB, 8-bit wide for ADS config reg
*/
#define CFG_BR4_PRELIM 0xf8000801
#define CFG_OR4_PRELIM 0xffffe1f1
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
@ -347,13 +337,15 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_FEC 1
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_MPC85XX_FEC 1
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define CONFIG_ETHPRIME "MOTO ENET0"
#endif /* CONFIG_TSEC_ENET */
@ -363,27 +355,21 @@
* Environment
*/
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#endif
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
@ -462,9 +448,10 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*****************************/
/* Environment Configuration */
/*****************************/
/*
* Environment Configuration
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)

117
include/configs/MPC8560ADS.h
Unescape View File

@ -50,12 +50,6 @@
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/*
* Use Localbus SDRAM to emulate flash before we can program the flash.
* Normally you need a flash-boot image(u-boot.bin).
* If unsure #undef this.
*/
#undef CONFIG_RAM_AS_FLASH
/*
* sysclk for MPC85xx
@ -65,24 +59,17 @@
* 66000000
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here. The board, however, can run and
* defaults to 66Mhz. In any event, this value must match the settings
* of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
*
* SW17[8] ------+ SW6
* SW15[1] ----+ | [0:1]
* V V V V
* 33MHz 1 1 1 0
* 66MHz 0 0 0 1
* is likely the desired value here, so that is now the default.
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#if !defined(CONFIG_SPD_EEPROM)
#define CONFIG_DDR_SETTING /* manually set up DDR parameters */
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
@ -107,27 +94,42 @@
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
#endif
/*
* SDRAM on the Local Bus
*/
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
#else
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#endif
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
#else /* Boot from real Flash */
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
#endif
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
@ -145,20 +147,9 @@
#undef CFG_RAMBOOT
#endif
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
#if defined(CONFIG_DDR_SETTING)
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
#endif
/*
* Local Bus Definitions
@ -247,28 +238,27 @@
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/
| CFG_LBC_LSDMR_OP_NORMAL)
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#else
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#endif
/*
* 32KB, 8-bit wide for ADS config reg
*/
#define CFG_BR4_PRELIM 0xf8000801
#define CFG_OR4_PRELIM 0xffffe1f1
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
@ -402,31 +392,25 @@
* Environment
*/
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#endif
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_PCI \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
@ -510,6 +494,11 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD

196
include/configs/stxgp3.h
Unescape View File

@ -39,7 +39,6 @@
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
#define CONFIG_MPC8560 1 /* MPC8560 specific */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
@ -49,15 +48,12 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#if defined(CONFIG_MPC85xx_REV1)
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#endif
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/* Using Localbus SDRAM to emulate flash before we can program the flash,
* normally you need a flash-boot image(u-boot.bin), if so undef this.
/* sysclk for MPC85xx
*/
#undef CONFIG_RAM_AS_FLASH
#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
@ -65,55 +61,29 @@
*/
#define CONFIG_SHOW_ACTIVITY 1
#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
#define CONFIG_DDR_SETTING
#endif
/* below can be toggled for performance analysis. otherwise use default */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#undef CONFIG_BTB /* toggle branch predition */
#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
#endif
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
/* GPPP supports up to 2G of DRAM. Allocate up to 1G until we get
* a chance to try it out. Actual size is always read from sdram eeprom.
*/
#define CFG_SDRAM_SIZE 1024 /* DDR is 1GB */
/* Localbus SDRAM is an option, not all boards have it.
*/
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
#else
#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
#endif
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
#else /* Boot from real Flash */
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
#endif
#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
@ -123,7 +93,7 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* The configuration latch is Chip Select 1.
* It's an 8-bit latch in the upper 8 bits of the word.
* It's an 8-bit latch in the lower 8 bits of the word.
*/
#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */
#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
@ -146,17 +116,18 @@
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
/*
* DDR Setup
*/
#if defined(CONFIG_DDR_SETTING)
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
#endif
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
@ -213,37 +184,65 @@
#undef CFG_I2C_NOPROBES
#endif
#define CFG_PCI_MEM_BASE 0xe0000000
#define CFG_PCI_MEM_PHYS 0xe0000000
#define CFG_PCI_MEM_SIZE 0x10000000
/* RapdIO Map configuration, mapped 1:1.
*/
#define CFG_RIO_MEM_BASE 0xc0000000
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */
/* Standard 8560 PCI addressing, mapped 1:1.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */
#define CFG_PCI_SUBSYS_DEVICEID 0x0003
#else
#define CFG_PCI_SUBSYS_DEVICEID 0x0009
#endif
#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
#undef CONFIG_PCI_SCAN_SHOW
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC2 1
#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_ETHPRIME "MOTO ENET0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
#if (CONFIG_ETHER_INDEX == 2)
/*
* - Rx-CLK is CLK13
* - Tx-CLK is CLK14
@ -259,59 +258,41 @@
#define CFG_FCC_PSMR 0
#endif
#define FETH2_RST 0x01
#elif (CONFIG_ETHER_INDEX == 3)
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
#endif /* CONFIG_ETHER_INDEX */
/* MDIO is done through the TSEC0 control.
*/
#define CONFIG_MII /* MII PHY management */
#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
/*
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
else iop->pdat &= ~0x00400000
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
else iop->pdat &= ~0x00200000
#define MIIDELAY udelay(1)
#endif
/* Environment */
/* We use the top boot sector flash, so we have some 16K sectors for env
* But....functions don't seem smart enough yet.
*/
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
#define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
#endif
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xff900000"
#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
CFG_CMD_PING | CFG_CMD_I2C) & \
@ -329,13 +310,13 @@
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
CFG_CMD_PING | CFG_CMD_I2C)
CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
CFG_CMD_MII | CFG_CMD_I2C)
CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
#elif defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
CFG_CMD_PING | CFG_CMD_I2C)
CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
#endif
#endif
#include <cmd_confdefs.h>
@ -387,9 +368,9 @@
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_ETHADDR 00:01:af:07:9b:8a
#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
#endif
#define CONFIG_SERVERIP 192.168.85.1
@ -399,5 +380,6 @@
#define CONFIG_HOSTNAME STX_GP3
#define CONFIG_ROOTPATH /gppproot
#define CONFIG_BOOTFILE uImage
#define CONFIG_LOADADDR 0x1000000
#endif /* __CONFIG_H */

15
include/e500.h
Unescape View File

@ -20,14 +20,29 @@ typedef struct
* initial memory mapping like legacy BAT registers do. Usually we
* use four MAS registers(MAS0-3) to operate on TLB1 entries.
*
* While there are 16 Entries with variable Page Sizes in TLB1,
* there are also 256 Entries with fixed 4K pages in TLB0.
*
* We also need LAWs(Local Access Window) to associate a range of
* the local 32-bit address space with a particular target interface
* such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
*
* We put TLB1/LAW code here because memory mapping is board-specific
* instead of cpu-specific.
*
* While these macros are all nominally for TLB1 by name, they can
* also be used for TLB0 as well.
*/
/*
* Convert addresses to Effective and Real Page Numbers.
* Grab the high 20-bits and shift 'em down, dropping the "byte offset".
*/
#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff)
#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff)
/* MAS0
* tlbsel(TLB Select):0,1
* esel(Entry Select): 0,1,2,...,15 for TLB1

Write Preview
Loading…
Cancel
Save