Tom Rini
10 years ago
commit
a0573d1988
@ -0,0 +1,9 @@ |
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y += time.o
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obj-y += interrupts.o
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obj-y += cpu.o
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@ -0,0 +1,38 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <linux/compiler.h> |
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#include <asm/mipsregs.h> |
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#include <asm/reboot.h> |
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void __weak _machine_restart(void) |
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{ |
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fprintf(stderr, "*** reset failed ***\n"); |
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while (1) |
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/* NOP */; |
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} |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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_machine_restart(); |
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return 0; |
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} |
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) |
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{ |
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write_c0_entrylo0(low0); |
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write_c0_pagemask(pagemask); |
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write_c0_entrylo1(low1); |
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write_c0_entryhi(hi); |
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write_c0_index(index); |
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tlb_write_indexed(); |
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} |
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@ -1,12 +0,0 @@ |
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y = cache.o
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obj-y += cpu.o interrupts.o time.o
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obj-$(CONFIG_SOC_AU1X00) += au1x00/
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y = cpu.o interrupts.o time.o cache.o
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@ -1,213 +0,0 @@ |
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/* |
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* Cache-handling routined for MIPS CPUs |
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* |
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm-offsets.h> |
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#include <config.h> |
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#include <asm/asm.h> |
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#include <asm/regdef.h> |
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#include <asm/mipsregs.h> |
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#include <asm/addrspace.h> |
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#include <asm/cacheops.h> |
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#define RA t9 |
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/* |
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* 16kB is the maximum size of instruction and data caches on MIPS 4K, |
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* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. |
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* |
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* Note that the above size is the maximum size of primary cache. U-Boot |
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* doesn't have L2 cache support for now. |
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*/ |
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#define MIPS_MAX_CACHE_SIZE 0x10000 |
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#define INDEX_BASE CKSEG0 |
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.macro cache_op op addr |
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.set push
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.set noreorder
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.set mips3
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cache \op, 0(\addr) |
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.set pop
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.endm |
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.macro f_fill64 dst, offset, val |
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) |
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#if LONGSIZE == 4 |
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LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) |
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LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) |
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#endif |
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.endm |
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/* |
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* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) |
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*/ |
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LEAF(mips_init_icache) |
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blez a1, 9f |
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mtc0 zero, CP0_TAGLO |
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/* clear tag to invalidate */ |
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PTR_LI t0, INDEX_BASE |
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PTR_ADDU t1, t0, a1 |
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1: cache_op INDEX_STORE_TAG_I t0 |
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PTR_ADDU t0, a2 |
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bne t0, t1, 1b |
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/* fill once, so data field parity is correct */ |
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PTR_LI t0, INDEX_BASE |
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2: cache_op FILL t0 |
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PTR_ADDU t0, a2 |
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bne t0, t1, 2b |
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/* invalidate again - prudent but not strictly neccessary */ |
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PTR_LI t0, INDEX_BASE |
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1: cache_op INDEX_STORE_TAG_I t0 |
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PTR_ADDU t0, a2 |
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bne t0, t1, 1b |
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9: jr ra |
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END(mips_init_icache) |
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/* |
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* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) |
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*/ |
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LEAF(mips_init_dcache) |
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blez a1, 9f |
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mtc0 zero, CP0_TAGLO |
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/* clear all tags */ |
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PTR_LI t0, INDEX_BASE |
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PTR_ADDU t1, t0, a1 |
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1: cache_op INDEX_STORE_TAG_D t0 |
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PTR_ADDU t0, a2 |
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bne t0, t1, 1b |
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/* load from each line (in cached space) */ |
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PTR_LI t0, INDEX_BASE |
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2: LONG_L zero, 0(t0) |
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PTR_ADDU t0, a2 |
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bne t0, t1, 2b |
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/* clear all tags */ |
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PTR_LI t0, INDEX_BASE |
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1: cache_op INDEX_STORE_TAG_D t0 |
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PTR_ADDU t0, a2 |
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bne t0, t1, 1b |
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9: jr ra |
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END(mips_init_dcache) |
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/* |
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* mips_cache_reset - low level initialisation of the primary caches |
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* |
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* This routine initialises the primary caches to ensure that they have good |
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* parity. It must be called by the ROM before any cached locations are used |
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* to prevent the possibility of data with bad parity being written to memory. |
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* |
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* To initialise the instruction cache it is essential that a source of data |
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* with good parity is available. This routine will initialise an area of |
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* memory starting at location zero to be used as a source of parity. |
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* |
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* RETURNS: N/A |
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* |
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*/ |
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NESTED(mips_cache_reset, 0, ra) |
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move RA, ra |
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li t2, CONFIG_SYS_ICACHE_SIZE |
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li t3, CONFIG_SYS_DCACHE_SIZE |
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li t8, CONFIG_SYS_CACHELINE_SIZE |
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li v0, MIPS_MAX_CACHE_SIZE |
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/* |
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* Now clear that much memory starting from zero. |
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*/ |
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PTR_LI a0, CKSEG1 |
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PTR_ADDU a1, a0, v0 |
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2: PTR_ADDIU a0, 64 |
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f_fill64 a0, -64, zero |
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bne a0, a1, 2b |
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/* |
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* The caches are probably in an indeterminate state, |
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* so we force good parity into them by doing an |
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* invalidate, load/fill, invalidate for each line. |
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*/ |
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/* |
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* Assume bottom of RAM will generate good parity for the cache. |
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*/ |
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/* |
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* Initialize the I-cache first, |
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*/ |
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move a1, t2 |
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move a2, t8 |
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PTR_LA v1, mips_init_icache |
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jalr v1 |
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/* |
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* then initialize D-cache. |
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*/ |
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move a1, t3 |
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move a2, t8 |
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PTR_LA v1, mips_init_dcache |
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jalr v1 |
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jr RA |
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END(mips_cache_reset) |
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/* |
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* dcache_status - get cache status |
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* |
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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* |
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*/ |
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LEAF(dcache_status) |
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mfc0 t0, CP0_CONFIG |
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li t1, CONF_CM_UNCACHED |
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andi t0, t0, CONF_CM_CMASK |
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move v0, zero |
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beq t0, t1, 2f |
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li v0, 1 |
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2: jr ra |
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END(dcache_status) |
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/* |
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* dcache_disable - disable cache |
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* |
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* RETURNS: N/A |
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* |
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*/ |
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LEAF(dcache_disable) |
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mfc0 t0, CP0_CONFIG |
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li t1, -8 |
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and t0, t0, t1 |
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ori t0, t0, CONF_CM_UNCACHED |
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mtc0 t0, CP0_CONFIG |
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jr ra |
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END(dcache_disable) |
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/* |
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* dcache_enable - enable cache |
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* |
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* RETURNS: N/A |
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* |
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*/ |
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LEAF(dcache_enable) |
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mfc0 t0, CP0_CONFIG |
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ori t0, CONF_CM_CMASK |
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xori t0, CONF_CM_CMASK |
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ori t0, CONF_CM_CACHABLE_NONCOHERENT |
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mtc0 t0, CP0_CONFIG |
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jr ra |
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END(dcache_enable) |
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@ -1,95 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <asm/mipsregs.h> |
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#include <asm/cacheops.h> |
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#include <asm/reboot.h> |
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#define cache_op(op, addr) \ |
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noreorder\n" \
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" .set mips64\n" \
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" cache %0, %1\n" \
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" .set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr))) |
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void __attribute__((weak)) _machine_restart(void) |
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{ |
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fprintf(stderr, "*** reset failed ***\n"); |
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while (1) |
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/* NOP */; |
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} |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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_machine_restart(); |
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return 0; |
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} |
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void flush_cache(ulong start_addr, ulong size) |
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{ |
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
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unsigned long addr = start_addr & ~(lsize - 1); |
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); |
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/* aend will be miscalculated when size is zero, so we return here */ |
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if (size == 0) |
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return; |
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while (1) { |
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cache_op(HIT_WRITEBACK_INV_D, addr); |
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cache_op(HIT_INVALIDATE_I, addr); |
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if (addr == aend) |
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break; |
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addr += lsize; |
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} |
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} |
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void flush_dcache_range(ulong start_addr, ulong stop) |
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{ |
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
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unsigned long addr = start_addr & ~(lsize - 1); |
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unsigned long aend = (stop - 1) & ~(lsize - 1); |
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while (1) { |
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cache_op(HIT_WRITEBACK_INV_D, addr); |
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if (addr == aend) |
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break; |
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addr += lsize; |
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} |
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} |
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void invalidate_dcache_range(ulong start_addr, ulong stop) |
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{ |
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
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unsigned long addr = start_addr & ~(lsize - 1); |
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unsigned long aend = (stop - 1) & ~(lsize - 1); |
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while (1) { |
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cache_op(HIT_INVALIDATE_D, addr); |
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if (addr == aend) |
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break; |
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addr += lsize; |
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} |
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} |
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) |
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{ |
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write_c0_entrylo0(low0); |
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write_c0_pagemask(pagemask); |
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write_c0_entrylo1(low1); |
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write_c0_entryhi(hi); |
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write_c0_index(index); |
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tlb_write_indexed(); |
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} |
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@ -1,22 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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int interrupt_init(void) |
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{ |
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return 0; |
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} |
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void enable_interrupts(void) |
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{ |
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} |
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int disable_interrupts(void) |
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{ |
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return 0; |
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} |
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@ -1,291 +0,0 @@ |
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/* |
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* Startup Code for MIPS64 CPU-core |
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* |
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm-offsets.h> |
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#include <config.h> |
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#include <asm/regdef.h> |
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#include <asm/mipsregs.h> |
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|
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE |
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT |
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#endif |
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|
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#ifndef CONFIG_SYS_INIT_SP_ADDR |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
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CONFIG_SYS_INIT_SP_OFFSET) |
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#endif |
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|
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#ifdef CONFIG_SYS_LITTLE_ENDIAN |
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#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ |
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(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) |
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#else |
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#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ |
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((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) |
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#endif |
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|
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/* |
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* For the moment disable interrupts, mark the kernel mode and |
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* set ST0_KX so that the CPU does not spit fire when using |
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* 64-bit addresses. |
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*/ |
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.macro setup_c0_status set clr |
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.set push
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mfc0 t0, CP0_STATUS |
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or t0, ST0_CU0 | \set | 0x1f | \clr |
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xor t0, 0x1f | \clr |
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mtc0 t0, CP0_STATUS |
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.set noreorder
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sll zero, 3 # ehb |
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.set pop
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.endm |
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|
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.set noreorder
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|
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.globl _start
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.text |
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_start: |
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/* U-boot entry point */ |
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b reset |
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nop |
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|
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.org 0x200
|
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/* TLB refill, 32 bit task */ |
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1: b 1b |
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nop |
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|
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.org 0x280
|
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/* XTLB refill, 64 bit task */ |
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1: b 1b |
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nop |
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|
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.org 0x300
|
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/* Cache error exception */ |
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1: b 1b |
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nop |
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|
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.org 0x380
|
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/* General exception */ |
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1: b 1b |
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nop |
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|
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.org 0x400
|
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/* Catch interrupt exceptions */ |
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1: b 1b |
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nop |
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|
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.org 0x480
|
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/* EJTAG debug exception */ |
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1: b 1b |
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nop |
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|
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.align 4
|
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reset: |
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|
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/* Clear watch registers */ |
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dmtc0 zero, CP0_WATCHLO |
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dmtc0 zero, CP0_WATCHHI |
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|
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/* WP(Watch Pending), SW0/1 should be cleared */ |
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mtc0 zero, CP0_CAUSE |
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|
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setup_c0_status ST0_KX 0 |
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|
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/* Init Timer */ |
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mtc0 zero, CP0_COUNT |
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mtc0 zero, CP0_COMPARE |
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|
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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/* CONFIG0 register */ |
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dli t0, CONF_CM_UNCACHED |
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mtc0 t0, CP0_CONFIG |
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#endif |
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|
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/* |
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* Initialize $gp, force 8 byte alignment of bal instruction to forbid |
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* the compiler to put nop's between bal and _gp. This is required to |
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* keep _gp and ra aligned to 8 byte. |
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*/ |
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.align 3
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bal 1f |
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nop |
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.dword _gp
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1: |
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ld gp, 0(ra) |
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|
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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/* Initialize any external memory */ |
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dla t9, lowlevel_init |
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jalr t9 |
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nop |
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|
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/* Initialize caches... */ |
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dla t9, mips_cache_reset |
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jalr t9 |
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nop |
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|
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/* ... and enable them */ |
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dli t0, CONFIG_SYS_MIPS_CACHE_MODE |
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mtc0 t0, CP0_CONFIG |
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#endif |
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|
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/* Set up temporary stack */ |
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dli t0, -16 |
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dli t1, CONFIG_SYS_INIT_SP_ADDR |
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and sp, t1, t0 # force 16 byte alignment |
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dsub sp, sp, GD_SIZE # reserve space for gd |
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and sp, sp, t0 # force 16 byte alignment |
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move k0, sp # save gd pointer |
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#ifdef CONFIG_SYS_MALLOC_F_LEN |
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dli t2, CONFIG_SYS_MALLOC_F_LEN |
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dsub sp, sp, t2 # reserve space for early malloc |
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and sp, sp, t0 # force 16 byte alignment |
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#endif |
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move fp, sp |
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|
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/* Clear gd */ |
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move t0, k0 |
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1: |
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sw zero, 0(t0) |
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blt t0, t1, 1b |
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daddi t0, 4 |
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|
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#ifdef CONFIG_SYS_MALLOC_F_LEN |
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daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset |
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sw sp, 0(t0) |
||||
#endif |
||||
|
||||
dla t9, board_init_f |
||||
jr t9 |
||||
move ra, zero |
||||
|
||||
/* |
||||
* void relocate_code (addr_sp, gd, addr_moni) |
||||
* |
||||
* This "function" does not return, instead it continues in RAM |
||||
* after relocating the monitor code. |
||||
* |
||||
* a0 = addr_sp |
||||
* a1 = gd |
||||
* a2 = destination address |
||||
*/ |
||||
.globl relocate_code
|
||||
.ent relocate_code
|
||||
relocate_code: |
||||
move sp, a0 # set new stack pointer |
||||
move fp, sp |
||||
|
||||
move s0, a1 # save gd in s0 |
||||
move s2, a2 # save destination address in s2 |
||||
|
||||
dli t0, CONFIG_SYS_MONITOR_BASE |
||||
dsub s1, s2, t0 # s1 <-- relocation offset |
||||
|
||||
dla t3, in_ram |
||||
ld t2, -24(t3) # t2 <-- __image_copy_end |
||||
move t1, a2 |
||||
|
||||
dadd gp, s1 # adjust gp |
||||
|
||||
/* |
||||
* t0 = source address |
||||
* t1 = target address |
||||
* t2 = source end address |
||||
*/ |
||||
1: |
||||
lw t3, 0(t0) |
||||
sw t3, 0(t1) |
||||
daddu t0, 4 |
||||
blt t0, t2, 1b |
||||
daddu t1, 4 |
||||
|
||||
/* If caches were enabled, we would have to flush them here. */ |
||||
dsub a1, t1, s2 # a1 <-- size |
||||
dla t9, flush_cache |
||||
jalr t9 |
||||
move a0, s2 # a0 <-- destination address |
||||
|
||||
/* Jump to where we've relocated ourselves */ |
||||
daddi t0, s2, in_ram - _start |
||||
jr t0 |
||||
nop |
||||
|
||||
.dword __rel_dyn_end
|
||||
.dword __rel_dyn_start
|
||||
.dword __image_copy_end
|
||||
.dword _GLOBAL_OFFSET_TABLE_
|
||||
.dword num_got_entries
|
||||
|
||||
in_ram: |
||||
/* |
||||
* Now we want to update GOT. |
||||
* |
||||
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object |
||||
* generated by GNU ld. Skip these reserved entries from relocation. |
||||
*/ |
||||
ld t3, -8(t0) # t3 <-- num_got_entries |
||||
ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ |
||||
dadd t8, s1 # t8 now holds relocated _G_O_T_ |
||||
daddi t8, t8, 16 # skipping first two entries |
||||
dli t2, 2 |
||||
1: |
||||
ld t1, 0(t8) |
||||
beqz t1, 2f |
||||
dadd t1, s1 |
||||
sd t1, 0(t8) |
||||
2: |
||||
daddi t2, 1 |
||||
blt t2, t3, 1b |
||||
daddi t8, 8 |
||||
|
||||
/* Update dynamic relocations */ |
||||
ld t1, -32(t0) # t1 <-- __rel_dyn_start |
||||
ld t2, -40(t0) # t2 <-- __rel_dyn_end |
||||
|
||||
b 2f # skip first reserved entry |
||||
daddi t1, 16 |
||||
|
||||
1: |
||||
lw t8, -4(t1) # t8 <-- relocation info |
||||
|
||||
dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) |
||||
bne t8, t3, 2f # skip non R_MIPS_REL32 entries |
||||
nop |
||||
|
||||
ld t3, -16(t1) # t3 <-- location to fix up in FLASH |
||||
|
||||
ld t8, 0(t3) # t8 <-- original pointer |
||||
dadd t8, s1 # t8 <-- adjusted pointer |
||||
|
||||
dadd t3, s1 # t3 <-- location to fix up in RAM |
||||
sd t8, 0(t3) |
||||
|
||||
2: |
||||
blt t1, t2, 1b |
||||
daddi t1, 16 # each rel.dyn entry is 16 bytes |
||||
|
||||
/* |
||||
* Clear BSS |
||||
* |
||||
* GOT is now relocated. Thus __bss_start and __bss_end can be |
||||
* accessed directly via $gp. |
||||
*/ |
||||
dla t1, __bss_start # t1 <-- __bss_start |
||||
dla t2, __bss_end # t2 <-- __bss_end |
||||
|
||||
1: |
||||
sd zero, 0(t1) |
||||
blt t1, t2, 1b |
||||
daddi t1, 8 |
||||
|
||||
move a0, s0 # a0 <-- gd |
||||
move a1, s2 |
||||
dla t9, board_init_r |
||||
jr t9 |
||||
move ra, zero |
||||
|
||||
.end relocate_code
|
||||
@ -1,19 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mipsregs.h> |
||||
|
||||
unsigned long notrace timer_read_counter(void) |
||||
{ |
||||
return read_c0_count(); |
||||
} |
||||
|
||||
ulong notrace get_tbclk(void) |
||||
{ |
||||
return CONFIG_SYS_MIPS_TIMER_FREQ; |
||||
} |
||||
Loading…
Reference in new issue