Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>master
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#
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# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o fpga.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,25 @@ |
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#
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# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp |
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TEXT_BASE = 0xFFF00000
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@ -0,0 +1,188 @@ |
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/*
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* (C) Copyright 2002 |
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
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* Keith Outwater, keith_outwater@mvis.com. |
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* |
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* (C) Copyright 2008 |
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <ACEX1K.h> |
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#include <command.h> |
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#include "fpga.h" |
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#include "mvblm7.h" |
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#ifdef FPGA_DEBUG |
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#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) |
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#else |
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#define fpga_debug(fmt, args...) |
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#endif |
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Altera_CYC2_Passive_Serial_fns altera_fns = { |
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fpga_null_fn, |
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fpga_config_fn, |
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fpga_status_fn, |
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fpga_done_fn, |
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fpga_wr_fn, |
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fpga_null_fn, |
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fpga_null_fn, |
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0 |
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}; |
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Altera_desc cyclone2 = { |
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Altera_CYC2, |
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passive_serial, |
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Altera_EP2C20_SIZE, |
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(void *) &altera_fns, |
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NULL, |
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0 |
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}; |
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DECLARE_GLOBAL_DATA_PTR; |
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int mvblm7_init_fpga(void) |
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{ |
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fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", |
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gd->reloc_off); |
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fpga_init(gd->reloc_off); |
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fpga_add(fpga_altera, &cyclone2); |
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fpga_config_fn(0, 1, 0); |
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udelay(60); |
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return 1; |
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} |
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int fpga_null_fn(int cookie) |
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{ |
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return 0; |
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} |
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int fpga_config_fn(int assert, int flush, int cookie) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; |
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u32 dvo = gpio->dat; |
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fpga_debug("SET config : %s\n", assert ? "low" : "high"); |
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if (assert) |
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dvo |= FPGA_CONFIG; |
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else |
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dvo &= ~FPGA_CONFIG; |
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if (flush) |
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gpio->dat = dvo; |
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return assert; |
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} |
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int fpga_done_fn(int cookie) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; |
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int result = 0; |
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udelay(10); |
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fpga_debug("CONF_DONE check ... "); |
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if (gpio->dat & FPGA_CONF_DONE) { |
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fpga_debug("high\n"); |
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result = 1; |
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} else |
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fpga_debug("low\n"); |
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return result; |
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} |
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int fpga_status_fn(int cookie) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; |
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int result = 0; |
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fpga_debug("STATUS check ... "); |
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if (gpio->dat & FPGA_STATUS) { |
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fpga_debug("high\n"); |
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result = 1; |
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} else |
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fpga_debug("low\n"); |
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return result; |
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} |
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int fpga_clk_fn(int assert_clk, int flush, int cookie) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; |
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u32 dvo = gpio->dat; |
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fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); |
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if (assert_clk) |
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dvo |= FPGA_CCLK; |
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else |
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dvo &= ~FPGA_CCLK; |
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if (flush) |
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gpio->dat = dvo; |
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return assert_clk; |
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} |
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static inline int _write_fpga(u8 val, int dump) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; |
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int i; |
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u32 dvo = gpio->dat; |
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if (dump) |
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fpga_debug(" %02x -> ", val); |
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for (i = 0; i < 8; i++) { |
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dvo &= ~FPGA_CCLK; |
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gpio->dat = dvo; |
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dvo &= ~FPGA_DIN; |
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if (dump) |
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fpga_debug("%d ", val&1); |
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if (val & 1) |
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dvo |= FPGA_DIN; |
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gpio->dat = dvo; |
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dvo |= FPGA_CCLK; |
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gpio->dat = dvo; |
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val >>= 1; |
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} |
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if (dump) |
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fpga_debug("\n"); |
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return 0; |
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} |
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int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) |
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{ |
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unsigned char *data = (unsigned char *) buf; |
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int i; |
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fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); |
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for (i = 0; i < len; i++) |
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_write_fpga(data[i], 0); |
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fpga_debug("\n"); |
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return FPGA_SUCCESS; |
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} |
@ -0,0 +1,34 @@ |
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/*
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* (C) Copyright 2002 |
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
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* Keith Outwater, keith_outwater@mvis.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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extern int mvblm7_init_fpga(void); |
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extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); |
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extern int fpga_status_fn(int cookie); |
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extern int fpga_config_fn(int assert, int flush, int cookie); |
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extern int fpga_done_fn(int cookie); |
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extern int fpga_clk_fn(int assert_clk, int flush, int cookie); |
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extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); |
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extern int fpga_null_fn(int cookie); |
@ -0,0 +1,157 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
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* |
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* (C) Copyright 2008 |
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <asm/mpc8349_pci.h> |
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#include <pci.h> |
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#include <spi.h> |
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#include <asm/mmu.h> |
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#if defined(CONFIG_OF_LIBFDT) |
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#include <libfdt.h> |
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#endif |
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#include "mvblm7.h" |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *)CFG_IMMR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CFG_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); |
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ddr_size = ddr_size >> 1, ddr_size_log2++) { |
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if (ddr_size & 1) |
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return -1; |
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} |
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im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); |
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & |
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LAWAR_SIZE); |
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im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; |
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; |
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; |
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CFG_DDR_MODE; |
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im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; |
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udelay(300); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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return CFG_DDR_SIZE; |
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} |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 msize = 0; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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msize = fixed_sdram(); |
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/* return total bus RAM size(bytes) */ |
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return msize * 1024 * 1024; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: Matrix Vision mvBlueLYNX-M7 " MV_VERSION "\n"); |
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return 0; |
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} |
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u8 *dhcp_vendorex_prep(u8 *e) |
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{ |
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char *ptr; |
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/* DHCP vendor-class-identifier = 60 */ |
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ptr = getenv("dhcp_vendor-class-identifier"); |
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if (ptr) { |
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*e++ = 60; |
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*e++ = strlen(ptr); |
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while (*ptr) |
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*e++ = *ptr++; |
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} |
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/* DHCP_CLIENT_IDENTIFIER = 61 */ |
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ptr = getenv("dhcp_client_id"); |
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if (ptr) { |
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*e++ = 61; |
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*e++ = strlen(ptr); |
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while (*ptr) |
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*e++ = *ptr++; |
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} |
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return e; |
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} |
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u8 *dhcp_vendorex_proc(u8 *popt) |
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{ |
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return NULL; |
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} |
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|
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#ifdef CONFIG_HARD_SPI |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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return bus == 0 && cs == 0; |
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} |
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|
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; |
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|
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iopd->dat &= ~MVBLM7_MMC_CS; |
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} |
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|
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; |
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|
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iopd->dat |= ~MVBLM7_MMC_CS; |
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} |
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#endif |
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|
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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} |
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|
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#endif |
@ -0,0 +1,21 @@ |
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#ifndef __MVBC_H__ |
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#define __MVBC_H__ |
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|
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#define MV_GPIO |
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|
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#define FPGA_CONFIG 0x80000000 |
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#define FPGA_CCLK 0x40000000 |
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#define FPGA_DIN 0x20000000 |
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#define FPGA_STATUS 0x10000000 |
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#define FPGA_CONF_DONE 0x08000000 |
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#define MMC_CS 0x04000000 |
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|
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#define WD_WDI 0x00400000 |
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#define WD_TS 0x00200000 |
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#define MAN_RST 0x00100000 |
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|
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#define MV_GPIO_DAT (WD_TS) |
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#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS) |
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#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) |
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|
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#endif |
@ -0,0 +1,37 @@ |
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echo |
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echo "==== running autoscript ====" |
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echo |
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setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} |
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setenv ramkernel setenv kernel_boot \${loadaddr} |
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setenv flashkernel setenv kernel_boot \${mv_kernel_addr} |
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setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} |
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setenv bootfromflash run flashkernel cpird ramparam bootdtb |
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setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} |
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setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 |
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setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup |
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setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel |
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setenv set_static_ip setenv ipaddr \${static_ipaddr} |
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setenv set_static_nm setenv netmask \${static_netmask} |
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setenv set_static_gw setenv gatewayip \${static_gateway} |
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setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} |
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setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs |
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if test ${autoscr_boot} != no; |
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then |
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if test ${netboot} = yes; |
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then |
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bootp |
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if test $? = 0; |
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then |
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echo "=== bootp succeeded -> netboot ===" |
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run set_ip |
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run getdtb rundtb bootfromnet ramparam bootdtb |
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else |
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echo "=== netboot failed ===" |
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fi |
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fi |
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run set_static_ip set_static_nm set_static_gw set_ip |
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echo "=== bootfromflash ===" |
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run cpdtb rundtb bootfromflash |
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else |
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echo "=== boot stopped with autoscr_boot no ===" |
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fi |
@ -0,0 +1,165 @@ |
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/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* (C) Copyright 2008 |
||||
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#if defined(CONFIG_OF_LIBFDT) |
||||
#include <libfdt.h> |
||||
#endif |
||||
#include <pci.h> |
||||
#include <mpc83xx.h> |
||||
#include "mvblm7.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* System RAM mapped to PCI space */ |
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE |
||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE |
||||
|
||||
#define SLOT0_IRQ 3 |
||||
#define SLOT1_IRQ 4 |
||||
void pci_mvblm7_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
||||
{ |
||||
unsigned char line = 0xff; |
||||
|
||||
if (PCI_BUS(dev) == 0) { |
||||
switch (PCI_DEV(dev)) { |
||||
case 0x0: |
||||
return; |
||||
case 0xb: |
||||
line = 0; |
||||
break; |
||||
case 0xc: |
||||
line = 1; |
||||
break; |
||||
default: |
||||
printf("***pci_scan: illegal dev = 0x%08x\n", |
||||
PCI_DEV(dev)); |
||||
line = 0xff; |
||||
break; |
||||
} |
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line); |
||||
} |
||||
} |
||||
|
||||
static struct pci_controller pci_hose = { |
||||
fixup_irq:pci_mvblm7_fixup_irq |
||||
}; |
||||
|
||||
int mvblm7_load_fpga(void) |
||||
{ |
||||
size_t data_size = 0; |
||||
void *fpga_data = NULL; |
||||
char *datastr = getenv("fpgadata"); |
||||
char *sizestr = getenv("fpgadatasize"); |
||||
|
||||
if (datastr) |
||||
fpga_data = (void *)simple_strtoul(datastr, NULL, 16); |
||||
if (sizestr) |
||||
data_size = (size_t)simple_strtoul(sizestr, NULL, 16); |
||||
|
||||
return fpga_load(0, fpga_data, data_size); |
||||
} |
||||
|
||||
static struct pci_region pci_regions[] = { |
||||
{ |
||||
bus_start: CFG_PCI1_MEM_BASE, |
||||
phys_start: CFG_PCI1_MEM_PHYS, |
||||
size: CFG_PCI1_MEM_SIZE, |
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
||||
}, |
||||
{ |
||||
bus_start: CFG_PCI1_MMIO_BASE, |
||||
phys_start: CFG_PCI1_MMIO_PHYS, |
||||
size: CFG_PCI1_MMIO_SIZE, |
||||
flags: PCI_REGION_MEM |
||||
}, |
||||
{ |
||||
bus_start: CFG_PCI1_IO_BASE, |
||||
phys_start: CFG_PCI1_IO_PHYS, |
||||
size: CFG_PCI1_IO_SIZE, |
||||
flags: PCI_REGION_IO |
||||
} |
||||
}; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
char *s; |
||||
int i; |
||||
int warmboot; |
||||
int load_fpga; |
||||
volatile immap_t *immr; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile gpio83xx_t *gpio; |
||||
volatile clk83xx_t *clk; |
||||
volatile law83xx_t *pci_law; |
||||
struct pci_region *reg[] = { pci_regions }; |
||||
|
||||
load_fpga = 1; |
||||
immr = (immap_t *) CFG_IMMR; |
||||
clk = (clk83xx_t *) &immr->clk; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
gpio = (volatile gpio83xx_t *)&immr->gpio[0]; |
||||
|
||||
s = getenv("skip_fpga"); |
||||
if (s) { |
||||
printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); |
||||
load_fpga = 0; |
||||
} |
||||
|
||||
gpio->dat = MV_GPIO_DAT; |
||||
gpio->odr = MV_GPIO_ODE; |
||||
if (load_fpga) |
||||
gpio->dir = MV_GPIO_OUT; |
||||
else |
||||
gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); |
||||
|
||||
printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, |
||||
immr->sysconf.sicrl); |
||||
|
||||
mvblm7_init_fpga(); |
||||
if (load_fpga) |
||||
mvblm7_load_fpga(); |
||||
|
||||
/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ |
||||
clk->occr = 0xc0000000; |
||||
|
||||
pci_ctrl[0].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
|
||||
for (i = 0; i < 1000; ++i) |
||||
udelay(1000); |
||||
|
||||
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; |
||||
|
||||
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
||||
|
||||
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; |
||||
|
||||
mpc83xx_pci_init(1, reg, warmboot); |
||||
} |
Loading…
Reference in new issue