Enough time has passed since this board was moved to Orphan. Remove. - Remove board/nx823/* - Remove include/configs/NX823.h - Clean-up ifdef(CONFIG_NX823) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = nx823.o flash.o
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@ -1,449 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Protection Flags: |
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*/ |
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#define FLAG_PROTECT_SET 0x01 |
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#define FLAG_PROTECT_CLEAR 0x02 |
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/* Board support for 1 or 2 flash devices */ |
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#undef FLASH_PORT_WIDTH32 |
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#define FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (FPW *addr, flash_info_t *info); |
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static int write_data (flash_info_t *info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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unsigned long size_b0; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Remap FLASH according to real size */ |
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); |
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; |
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/* Re-do sizing to get full correct info */ |
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size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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/* monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_FLASH_BASE, |
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CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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flash_info[0].size = size_b0; |
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return (size_b0); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00020000); |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: printf ("INTEL "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F320J3A: |
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printf ("28F320J3A\n"); break; |
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case FLASH_28F640J3A: |
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printf ("28F640J3A\n"); break; |
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case FLASH_28F128J3A: |
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printf ("28F128J3A\n"); break; |
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default: printf ("Unknown Chip Type\n"); break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW *addr, flash_info_t *info) |
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{ |
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FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW)0x00AA00AA; |
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addr[0x2AAA] = (FPW)0x00550055; |
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addr[0x5555] = (FPW)0x00900090; |
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value = addr[0]; |
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switch (value) { |
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case (FPW)INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW)0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW)INTEL_ID_28F320J3A: |
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info->flash_id += FLASH_28F320J3A; |
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info->sector_count = 32; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case (FPW)INTEL_ID_28F640J3A: |
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info->flash_id += FLASH_28F640J3A; |
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info->sector_count = 64; |
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info->size = 0x00800000; |
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break; /* => 8 MB */ |
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case (FPW)INTEL_ID_28F128J3A: |
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info->flash_id += FLASH_28F128J3A; |
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info->sector_count = 128; |
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info->size = 0x01000000; |
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break; /* => 16 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); |
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW)0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type, start, now, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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start = get_timer (0); |
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last = start; |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *)(info->start[sect]); |
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FPW status; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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*addr = (FPW)0x00500050; /* clear status register */ |
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*addr = (FPW)0x00200020; /* erase setup */ |
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*addr = (FPW)0x00D000D0; /* erase confirm */ |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { |
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if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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*addr = (FPW)0x00B000B0; /* suspend erase */ |
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*addr = (FPW)0x00FF00FF; /* reset to read mode */ |
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rcode = 1; |
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break; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc ('.'); |
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last = now; |
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} |
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} |
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*addr = (FPW)0x00FF00FF; /* reset to read mode */ |
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printf (" done\n"); |
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} |
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} |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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FPW data; |
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int count, i, l, rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return 4; |
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} |
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/* get lower word aligned address */ |
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#ifdef FLASH_PORT_WIDTH16 |
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wp = (addr & ~1); |
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port_width = 2; |
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#else |
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wp = (addr & ~3); |
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port_width = 4; |
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#endif |
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/* save sernum if needed */ |
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if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE) |
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{ |
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u_long dest = CONFIG_SYS_FLASH_SN_BASE; |
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u_short *sn = (u_short *)gd->bd->bi_sernum; |
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printf("(saving sernum)"); |
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for (i=0; i<4; i++) |
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{ |
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if ((rc = write_data(info, dest, sn[i])) != 0) { |
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return (rc); |
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} |
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dest += port_width; |
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} |
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} |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i=0, cp=wp; i<l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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for (; i<port_width && cnt>0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt==0 && i<port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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if ((rc = write_data(info, wp, data)) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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} |
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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while (cnt >= port_width) { |
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data = 0; |
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for (i=0; i<port_width; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_data(info, wp, data)) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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cnt -= port_width; |
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if (count++ > 0x800) |
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{ |
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putc('.'); |
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count = 0; |
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} |
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} |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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for (; i<port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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return (write_data(info, wp, data)); |
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} |
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/*-----------------------------------------------------------------------
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* Write a word or halfword to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_data (flash_info_t *info, ulong dest, FPW data) |
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{ |
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FPWV *addr = (FPWV *)dest; |
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ulong status; |
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ulong start; |
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int flag; |
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/* Check if Flash is (sufficiently) erased */ |
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if ((*addr & data) != data) { |
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printf("not erased at %08lx (%x)\n",(ulong)addr,*addr); |
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return (2); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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*addr = (FPW)0x00400040; /* write setup */ |
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*addr = data; |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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start = get_timer (0); |
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while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { |
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
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*addr = (FPW)0x00FF00FF; /* restore read mode */ |
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return (1); |
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} |
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} |
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*addr = (FPW)0x00FF00FF; /* restore read mode */ |
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return (0); |
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} |
@ -1,374 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <mpc8xx.h> |
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#include <net.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static long int dram_size (long int, long int *, long int); |
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#define _NOT_USED_ 0xFFFFFFFF |
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const uint sdram_table[] = { |
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#if (MPC8XX_SPEED <= 50000000L) |
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/*
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* Single Read. (Offset 0 in UPMA RAM) |
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*/ |
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0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07, |
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0xFFFFFFFF, |
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM) |
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* |
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* This is no UPM entry point. The following definition uses |
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* the remaining space to establish an initialization |
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* sequence, which is executed by a RUN command. |
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* |
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*/ |
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0x1FE7F434, 0xEFABE834, 0x1FA7D435, |
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|
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/*
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* Burst Read. (Offset 8 in UPMA RAM) |
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*/ |
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0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00, |
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0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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/*
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* Single Write. (Offset 18 in UPMA RAM) |
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*/ |
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0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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|
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/*
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* Burst Write. (Offset 20 in UPMA RAM) |
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*/ |
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0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00, |
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0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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/*
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* Refresh (Offset 30 in UPMA RAM) |
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*/ |
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0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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/*
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* Exception. (Offset 3c in UPMA RAM) |
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*/ |
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0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF |
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#else |
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/*
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* Single Read. (Offset 0 in UPMA RAM) |
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*/ |
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0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800, |
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0x1FF7F447, |
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|
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM) |
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* |
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* This is no UPM entry point. The following definition uses |
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* the remaining space to establish an initialization |
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* sequence, which is executed by a RUN command. |
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* |
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*/ |
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0x1FF7F434, 0xEFEBE834, 0x1FB7D435, |
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/*
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* Burst Read. (Offset 8 in UPMA RAM) |
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*/ |
||||
0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM) |
||||
*/ |
||||
0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC84, 0xFFFFFC07, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM) |
||||
*/ |
||||
0x7FFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
#endif |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
*/ |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
printf ("Board: Nexus NX823"); |
||||
return (0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
phys_size_t initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size_b0, size_b1, size8, size9; |
||||
|
||||
upmconfig (UPMA, (uint *) sdram_table, |
||||
sizeof (sdram_table) / sizeof (uint)); |
||||
|
||||
/*
|
||||
* Up to 2 Banks of 64Mbit x 2 devices |
||||
* Initial builds only have 1 |
||||
*/ |
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; |
||||
memctl->memc_mar = 0x00000088; |
||||
|
||||
/*
|
||||
* Map controller SDRAM bank 0 |
||||
*/ |
||||
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; |
||||
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; |
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ |
||||
udelay (200); |
||||
|
||||
/*
|
||||
* Map controller SDRAM bank 1 |
||||
*/ |
||||
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; |
||||
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; |
||||
|
||||
/*
|
||||
* Perform SDRAM initializsation sequence |
||||
*/ |
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh (depends on number of |
||||
* banks): This value is selected for four cycles every 62.4 us |
||||
* with two SDRAM banks or four cycles every 31.2 us with one |
||||
* bank. It will be adjusted after memory sizing. |
||||
*/ |
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; |
||||
|
||||
memctl->memc_mar = 0x00000088; |
||||
|
||||
|
||||
/*
|
||||
* Check Bank 0 Memory Size for re-configuration |
||||
* |
||||
* try 8 column mode |
||||
*/ |
||||
size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, |
||||
SDRAM_MAX_SIZE); |
||||
|
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* try 9 column mode |
||||
*/ |
||||
size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, |
||||
SDRAM_MAX_SIZE); |
||||
|
||||
if (size8 < size9) { /* leave configuration at 9 columns */ |
||||
size_b0 = size9; |
||||
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ |
||||
} else { /* back to 8 columns */ |
||||
size_b0 = size8; |
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; |
||||
udelay (500); |
||||
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ |
||||
} |
||||
|
||||
/*
|
||||
* Check Bank 1 Memory Size |
||||
* use current column settings |
||||
* [9 column SDRAM may also be used in 8 column mode, |
||||
* but then only half the real size will be used.] |
||||
*/ |
||||
size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, |
||||
SDRAM_MAX_SIZE); |
||||
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ |
||||
|
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* Adjust refresh rate depending on SDRAM type, both banks |
||||
* For types > 128 MBit leave it at the current (fast) rate |
||||
*/ |
||||
if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { |
||||
/* reduce to 15.6 us (62.4 us / quad) */ |
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; |
||||
udelay (1000); |
||||
} |
||||
|
||||
/*
|
||||
* Final mapping: map bigger bank first |
||||
*/ |
||||
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ |
||||
|
||||
memctl->memc_or2 = |
||||
((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
||||
memctl->memc_br2 = |
||||
(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; |
||||
|
||||
if (size_b0 > 0) { |
||||
/*
|
||||
* Position Bank 0 immediately above Bank 1 |
||||
*/ |
||||
memctl->memc_or1 = |
||||
((-size_b0) & 0xFFFF0000) | |
||||
CONFIG_SYS_OR_TIMING_SDRAM; |
||||
memctl->memc_br1 = |
||||
((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | |
||||
BR_V) |
||||
+ size_b1; |
||||
} else { |
||||
unsigned long reg; |
||||
|
||||
/*
|
||||
* No bank 0 |
||||
* |
||||
* invalidate bank |
||||
*/ |
||||
memctl->memc_br1 = 0; |
||||
|
||||
/* adjust refresh rate depending on SDRAM type, one bank */ |
||||
reg = memctl->memc_mptpr; |
||||
reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ |
||||
memctl->memc_mptpr = reg; |
||||
} |
||||
|
||||
} else { /* SDRAM Bank 0 is bigger - map first */ |
||||
|
||||
memctl->memc_or1 = |
||||
((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
||||
memctl->memc_br1 = |
||||
(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; |
||||
|
||||
if (size_b1 > 0) { |
||||
/*
|
||||
* Position Bank 1 immediately above Bank 0 |
||||
*/ |
||||
memctl->memc_or2 = |
||||
((-size_b1) & 0xFFFF0000) | |
||||
CONFIG_SYS_OR_TIMING_SDRAM; |
||||
memctl->memc_br2 = |
||||
((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | |
||||
BR_V) |
||||
+ size_b0; |
||||
} else { |
||||
unsigned long reg; |
||||
|
||||
/*
|
||||
* No bank 1 |
||||
* |
||||
* invalidate bank |
||||
*/ |
||||
memctl->memc_br2 = 0; |
||||
|
||||
/* adjust refresh rate depending on SDRAM type, one bank */ |
||||
reg = memctl->memc_mptpr; |
||||
reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ |
||||
memctl->memc_mptpr = reg; |
||||
} |
||||
} |
||||
|
||||
udelay (10000); |
||||
|
||||
return (size_b0 + size_b1); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines |
||||
* the actually available RAM size between addresses `base' and |
||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
||||
* - short between address lines |
||||
* - short between data lines |
||||
*/ |
||||
|
||||
static long int dram_size (long int mamr_value, long int *base, |
||||
long int maxsize) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
memctl->memc_mamr = mamr_value; |
||||
|
||||
return (get_ram_size (base, maxsize)); |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
int i; |
||||
char tmp[50]; |
||||
uchar ethaddr[6]; |
||||
bd_t *bd = gd->bd; |
||||
ulong *my_sernum = (unsigned long *)&bd->bi_sernum; |
||||
|
||||
/* load unique serial number */ |
||||
for (i = 0; i < 8; ++i) |
||||
bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); |
||||
|
||||
/* save env variables according to sernum */ |
||||
sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); |
||||
setenv ("serial#", tmp); |
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", ethaddr)) { |
||||
ethaddr[0] = 0x10; |
||||
ethaddr[1] = 0x20; |
||||
ethaddr[2] = 0x30; |
||||
ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; |
||||
ethaddr[4] = bd->bi_sernum[5]; |
||||
ethaddr[5] = bd->bi_sernum[6]; |
||||
} |
||||
|
||||
return 0; |
||||
} |
@ -1,82 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2001-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,121 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,344 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
/*#define CONFIG_VIDEO 1 */ |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED |
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ |
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
||||
#define CONFIG_BOOTARGS "ramdisk_size=8000 "\ |
||||
"root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
|
||||
"nfsaddrs=10.77.77.20:10.77.77.250" |
||||
#define CONFIG_BOOTCOMMAND "bootm 400e0000" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ |
||||
#define CONFIG_SOURCE |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_SOURCE |
||||
|
||||
|
||||
/* call various generic functions */ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define xEMBED |
||||
#ifdef EMBED |
||||
#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ |
||||
#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE |
||||
#else |
||||
#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */ |
||||
#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ |
||||
#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ |
||||
#define CONFIG_SYS_FLASH_SN_BYTES 8 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 12-30 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 12-16 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 12-18 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 12-23 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
*/ |
||||
#define MPC8XX_SPEED 66666666L |
||||
#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ |
||||
#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) |
||||
#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |
||||
#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 5-3 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0 and OR0 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ |
||||
OR_SCY_8_CLK ) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
/*
|
||||
* BR1/2 and OR1/2 (SDRAM) |
||||
*/ |
||||
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) |
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/* IO and memory mapped stuff */ |
||||
#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ |
||||
#define NX823_IO_BASE 0xFF000000 /* start of IO */ |
||||
#define GPOUT_OFFSET (3<<16) |
||||
#define QUART_OFFSET (4<<16) |
||||
#define VIDAC_OFFSET (5<<16) |
||||
#define CPLD_OFFSET (6<<16) |
||||
#define SED1386_OFFSET (7<<16) |
||||
|
||||
/*
|
||||
* BR3 and OR3 (general purpose output latches) |
||||
*/ |
||||
#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) |
||||
#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) |
||||
#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) |
||||
#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V) |
||||
|
||||
/*
|
||||
* BR4 and OR4 (QUART) |
||||
*/ |
||||
#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) |
||||
#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) |
||||
#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) |
||||
#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) |
||||
|
||||
/*
|
||||
* BR5 and OR5 (Video DAC) |
||||
*/ |
||||
#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) |
||||
#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) |
||||
#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) |
||||
#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) |
||||
|
||||
/*
|
||||
* BR6 and OR6 (CPLD) |
||||
* FIXME timing not verified for CPLD |
||||
*/ |
||||
#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) |
||||
#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) |
||||
#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) |
||||
#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR7 and OR7 (SED1386) |
||||
* FIXME timing not verified for SED controller |
||||
*/ |
||||
#define SED1386_BASE 0xF7000000 |
||||
#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) |
||||
#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ |
||||
#define CONFIG_ETHADDR 00:10:20:30:40:50 |
||||
#define CONFIG_IPADDR 10.77.77.20 |
||||
#define CONFIG_SERVERIP 10.77.77.250 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue