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@ -16,7 +16,7 @@ |
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#if defined(CONFIG_FSL_CORENET) |
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#if defined(CONFIG_FSL_CORENET) |
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 |
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 |
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#elif defined(CONFIG_BSC9132QDS) |
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#elif defined(CONFIG_TARGET_BSC9132QDS) |
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 |
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 |
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#elif defined(CONFIG_C29XPCIE) |
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#elif defined(CONFIG_C29XPCIE) |
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#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 |
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#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 |
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@ -138,7 +138,7 @@ |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 |
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#elif defined(CONFIG_FSL_CORENET) |
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#elif defined(CONFIG_FSL_CORENET) |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 |
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#elif defined(CONFIG_BSC9132QDS) |
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#elif defined(CONFIG_TARGET_BSC9132QDS) |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 |
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#elif defined(CONFIG_C29XPCIE) |
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#elif defined(CONFIG_C29XPCIE) |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 |
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 |
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