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@ -305,7 +305,7 @@ struct uart_port { |
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# define SCIF2_RFDC_MASK 0x001f |
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# define SCIF2_RFDC_MASK 0x001f |
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# define SCIF2_TXROOM_MAX 16 |
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# define SCIF2_TXROOM_MAX 16 |
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ |
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ |
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defined(CONFIG_R8A7793) |
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defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) |
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
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# define SCIF_RFDC_MASK 0x003f |
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# define SCIF_RFDC_MASK 0x003f |
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#else |
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#else |
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@ -736,7 +736,7 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk) |
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#elif defined(__H8300H__) || defined(__H8300S__) |
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#elif defined(__H8300H__) || defined(__H8300S__) |
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#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
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#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ |
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ |
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defined(CONFIG_R8A7793) |
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defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) |
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#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ |
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#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ |
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ |
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ |
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#else /* Generic SH */ |
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#else /* Generic SH */ |
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