Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>master
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/*
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* (C) Copyright 2000-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
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* Scott McNutt <smcnutt@psyent.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/nios2.h> |
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#include <asm/types.h> |
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#include <asm/io.h> |
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struct nios_timer { |
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u32 status; /* Timer status reg */ |
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u32 control; /* Timer control reg */ |
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u32 periodl; /* Timeout period low */ |
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u32 periodh; /* Timeout period high */ |
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u32 snapl; /* Snapshot low */ |
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u32 snaph; /* Snapshot high */ |
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}; |
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/* status register */ |
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#define NIOS_TIMER_TO (1 << 0) /* Timeout */ |
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#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ |
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/* control register */ |
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#define NIOS_TIMER_ITO (1 << 0) /* Timeout interrupt enable */ |
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#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ |
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#define NIOS_TIMER_START (1 << 2) /* Start timer */ |
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#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ |
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/*************************************************************************/ |
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unsigned long notrace timer_read_counter(void) |
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{ |
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struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE; |
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u32 val; |
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/* Trigger update */ |
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writel(0x0, &tmr->snapl); |
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/* Read timer value */ |
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val = readl(&tmr->snapl) & 0xffff; |
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val |= (readl(&tmr->snaph) & 0xffff) << 16; |
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return ~val; |
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} |
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int timer_init(void) |
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{ |
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struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE; |
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writel(0, &tmr->status); |
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writel(0, &tmr->control); |
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writel(NIOS_TIMER_STOP, &tmr->control); |
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writel(0xffff, &tmr->periodl); |
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writel(0xffff, &tmr->periodh); |
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writel(NIOS_TIMER_CONT | NIOS_TIMER_START, &tmr->control); |
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return 0; |
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} |
@ -0,0 +1,19 @@ |
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Altera Timer |
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Required properties: |
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- compatible : should be "altr,timer-1.0" |
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- reg : Specifies base physical address and size of the registers. |
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- interrupt-parent: phandle of the interrupt controller |
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- interrupts : Should contain the timer interrupt number |
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- clock-frequency : The frequency of the clock that drives the counter, in Hz. |
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Example: |
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timer { |
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compatible = "altr,timer-1.0"; |
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reg = <0x00400000 0x00000020>; |
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interrupt-parent = <&cpu>; |
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interrupts = <11>; |
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clock-frequency = <125000000>; |
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}; |
@ -0,0 +1,104 @@ |
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/*
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* (C) Copyright 2000-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
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* Scott McNutt <smcnutt@psyent.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <timer.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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struct altera_timer_regs { |
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u32 status; /* Timer status reg */ |
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u32 control; /* Timer control reg */ |
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u32 periodl; /* Timeout period low */ |
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u32 periodh; /* Timeout period high */ |
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u32 snapl; /* Snapshot low */ |
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u32 snaph; /* Snapshot high */ |
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}; |
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struct altera_timer_platdata { |
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struct altera_timer_regs *regs; |
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unsigned long clock_rate; |
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}; |
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/* control register */ |
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#define ALTERA_TIMER_CONT (1 << 1) /* Continuous mode */ |
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#define ALTERA_TIMER_START (1 << 2) /* Start timer */ |
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#define ALTERA_TIMER_STOP (1 << 3) /* Stop timer */ |
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static int altera_timer_get_count(struct udevice *dev, unsigned long *count) |
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{ |
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struct altera_timer_platdata *plat = dev->platdata; |
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struct altera_timer_regs *const regs = plat->regs; |
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u32 val; |
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/* Trigger update */ |
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writel(0x0, ®s->snapl); |
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/* Read timer value */ |
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val = readl(®s->snapl) & 0xffff; |
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val |= (readl(®s->snaph) & 0xffff) << 16; |
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*count = ~val; |
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return 0; |
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} |
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static int altera_timer_probe(struct udevice *dev) |
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{ |
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
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struct altera_timer_platdata *plat = dev->platdata; |
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struct altera_timer_regs *const regs = plat->regs; |
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uc_priv->clock_rate = plat->clock_rate; |
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writel(0, ®s->status); |
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writel(0, ®s->control); |
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writel(ALTERA_TIMER_STOP, ®s->control); |
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writel(0xffff, ®s->periodl); |
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writel(0xffff, ®s->periodh); |
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writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control); |
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return 0; |
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} |
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static int altera_timer_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct altera_timer_platdata *plat = dev_get_platdata(dev); |
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plat->regs = ioremap(dev_get_addr(dev), |
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sizeof(struct altera_timer_regs)); |
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plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
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"clock-frequency", 0); |
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return 0; |
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} |
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static const struct timer_ops altera_timer_ops = { |
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.get_count = altera_timer_get_count, |
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}; |
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static const struct udevice_id altera_timer_ids[] = { |
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{ .compatible = "altr,timer-1.0", }, |
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{ } |
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}; |
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U_BOOT_DRIVER(altera_timer) = { |
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.name = "altera_timer", |
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.id = UCLASS_TIMER, |
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.of_match = altera_timer_ids, |
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.ofdata_to_platdata = altera_timer_ofdata_to_platdata, |
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.platdata_auto_alloc_size = sizeof(struct altera_timer_platdata), |
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.probe = altera_timer_probe, |
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.ops = &altera_timer_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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