Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>master
Jagan Teki
8 years ago
committed by
Stefano Babic
parent
b8ad70f706
commit
a5b9f8c8f0
@ -0,0 +1,119 @@ |
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/* |
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* Copyright (C) 2016 Amarula Solutions B.V. |
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* Copyright (C) 2016 Engicam S.r.l. |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* version 2 as published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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|
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include "imx6ul.dtsi" |
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|
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/ { |
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model = "Engicam GEAM6UL"; |
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compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; |
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|
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memory { |
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reg = <0x80000000 0x08000000>; |
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}; |
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chosen { |
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stdout-path = &uart1; |
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}; |
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}; |
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|
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&uart1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1>; |
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status = "okay"; |
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}; |
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|
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&usdhc1 { |
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pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
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pinctrl-0 = <&pinctrl_usdhc1>; |
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
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bus-width = <4>; |
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; |
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no-1-8-v; |
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status = "okay"; |
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}; |
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|
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&iomuxc { |
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pinctrl_uart1: uart1grp { |
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fsl,pins = < |
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
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>; |
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}; |
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|
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pinctrl_usdhc1: usdhc1grp { |
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fsl,pins = < |
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 |
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
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>; |
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}; |
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|
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
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fsl,pins = < |
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 |
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 |
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
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>; |
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}; |
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|
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
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fsl,pins = < |
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 |
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 |
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 |
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 |
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 |
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 |
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>; |
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}; |
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}; |
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@ -0,0 +1,12 @@ |
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if TARGET_MX6UL_GEAM |
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|
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config SYS_BOARD |
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default "geam6ul" |
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|
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config SYS_VENDOR |
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default "engicam" |
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config SYS_CONFIG_NAME |
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default "imx6ul_geam" |
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endif |
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@ -0,0 +1,6 @@ |
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GEAM6UL BOARD |
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M: Jagan Teki <jagan@amarulasolutions.com> |
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S: Maintained |
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F: board/engicam/geam6ul |
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F: include/configs/imx6ul_geam.h |
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F: configs/imx6ul_geam_mmc_defconfig |
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@ -0,0 +1,6 @@ |
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# Copyright (C) 2016 Amarula Solutions B.V.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := geam6ul.o
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@ -0,0 +1,28 @@ |
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How to use U-Boot on Engicam GEAM6UL Starter Kit: |
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------------------------------------------------- |
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|
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- Configure U-Boot for Engicam GEAM6UL: |
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|
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$ make mrproper |
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$ make imx6ul_geam_mmc_defconfig |
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$ make |
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|
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This will generate the SPL image called SPL and the u-boot-dtb.img. |
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|
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- Flash the SPL image into the micro SD card: |
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sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync |
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|
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- Flash the u-boot-dtb.img image into the micro SD card: |
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sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync |
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|
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- Jumper settings: |
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MMC Boot: JM3 Closed |
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|
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- Connect the Serial cable between the Starter Kit and the PC for the console. |
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(J28 is the Linux Serial console connector) |
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|
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- Insert the micro SD card in the board, power it up and U-Boot messages should |
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come up. |
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@ -0,0 +1,246 @@ |
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/*
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* Copyright (C) 2016 Amarula Solutions B.V. |
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* Copyright (C) 2016 Engicam S.r.l. |
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* Author: Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include <linux/sizes.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/imx-common/iomux-v3.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const uart1_pads[] = { |
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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int board_early_init_f(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* Address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = imx_ddr_size(); |
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return 0; |
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} |
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#ifdef CONFIG_SPL_BUILD |
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#include <libfdt.h> |
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#include <spl.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/mx6-ddr.h> |
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/* MMC board initialization is needed till adding DM support in SPL */ |
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#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const usdhc1_pads[] = { |
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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|
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/* VSELECT */ |
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MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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/* CD */ |
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MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* RST_B */ |
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MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) |
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struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC1_BASE_ADDR, 0, 4}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret = 0; |
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switch (cfg->esdhc_base) { |
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case USDHC1_BASE_ADDR: |
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ret = !gpio_get_value(USDHC1_CD_GPIO); |
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break; |
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} |
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return ret; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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int i, ret; |
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/*
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* According to the board_mmc_init() the following map is done: |
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* (U-boot device node) (Physical Port) |
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* mmc0 USDHC1 |
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*/ |
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
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switch (i) { |
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case 0: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
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gpio_direction_input(USDHC1_CD_GPIO); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
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break; |
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default: |
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printf("Warning - USDHC%d controller not supporting\n", |
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i + 1); |
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return 0; |
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} |
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
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if (ret) { |
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printf("Warning: failed to initialize mmc dev %d\n", i); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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#endif /* CONFIG_FSL_ESDHC */ |
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
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.grp_addds = 0x00000030, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_b0ds = 0x00000030, |
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.grp_ctlds = 0x00000030, |
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.grp_b1ds = 0x00000030, |
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.grp_ddrpke = 0x00000000, |
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.grp_ddrmode = 0x00020000, |
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.grp_ddr_type = 0x000c0000, |
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}; |
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { |
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.dram_dqm0 = 0x00000030, |
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.dram_dqm1 = 0x00000030, |
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.dram_ras = 0x00000030, |
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.dram_cas = 0x00000030, |
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.dram_odt0 = 0x00000030, |
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.dram_odt1 = 0x00000030, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdclk_0 = 0x00000008, |
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.dram_sdqs0 = 0x00000038, |
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.dram_sdqs1 = 0x00000030, |
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.dram_reset = 0x00000030, |
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}; |
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static struct mx6_mmdc_calibration mx6_mmcd_calib = { |
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.p0_mpwldectrl0 = 0x00070007, |
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.p0_mpdgctrl0 = 0x41490145, |
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.p0_mprddlctl = 0x40404546, |
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.p0_mpwrdlctl = 0x4040524D, |
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}; |
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struct mx6_ddr_sysinfo ddr_sysinfo = { |
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.dsize = 0, |
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.cs_density = 20, |
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.ncs = 1, |
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.cs1_mirror = 0, |
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.rtt_wr = 2, |
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */ |
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.walat = 1, /* Write additional latency */ |
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.ralat = 5, /* Read additional latency */ |
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.mif3_mode = 3, /* Command prediction working mode */ |
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.bi_on = 1, /* Bank interleaving enabled */ |
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
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.ddr_type = DDR_TYPE_DDR3, |
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}; |
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static struct mx6_ddr3_cfg mem_ddr = { |
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.mem_speed = 800, |
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.density = 4, |
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.width = 16, |
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.banks = 8, |
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.rowaddr = 13, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1375, |
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.trcmin = 4875, |
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.trasmin = 3500, |
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}; |
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static void ccgr_init(void) |
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{ |
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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writel(0xFFFFFFFF, &ccm->CCGR0); |
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writel(0xFFFFFFFF, &ccm->CCGR1); |
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writel(0xFFFFFFFF, &ccm->CCGR2); |
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writel(0xFFFFFFFF, &ccm->CCGR3); |
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writel(0xFFFFFFFF, &ccm->CCGR4); |
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writel(0xFFFFFFFF, &ccm->CCGR5); |
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writel(0xFFFFFFFF, &ccm->CCGR6); |
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writel(0xFFFFFFFF, &ccm->CCGR7); |
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} |
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static void spl_dram_init(void) |
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{ |
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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/* setup AIPS and disable watchdog */ |
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arch_cpu_init(); |
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ccgr_init(); |
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/* iomux and setup of i2c */ |
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board_early_init_f(); |
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/* setup GP timer */ |
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timer_init(); |
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/* UART clocks enabled and gd valid - init serial console */ |
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preloader_console_init(); |
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/* DDR initialization */ |
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spl_dram_init(); |
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|
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/* Clear the BSS. */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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|
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/* load/boot image from boot device */ |
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board_init_r(NULL, 0); |
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} |
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#endif /* CONFIG_SPL_BUILD */ |
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@ -0,0 +1,39 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_MX6=y |
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CONFIG_TARGET_MX6UL_GEAM=y |
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" |
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CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb" |
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CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit" |
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CONFIG_SYS_PROMPT="geam6ul> " |
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CONFIG_SPL=y |
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CONFIG_BOOTDELAY=3 |
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CONFIG_BOARD_EARLY_INIT_F=y |
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CONFIG_DISPLAY_CPUINFO=y |
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CONFIG_HUSH_PARSER=y |
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CONFIG_AUTO_COMPLETE=y |
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CONFIG_SYS_MAXARGS=32 |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_BLK is not set |
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# CONFIG_DM_MMC_OPS is not set |
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CONFIG_CMD_BOOTZ=y |
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CONFIG_CMD_GPIO=y |
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CONFIG_CMD_MEMTEST=y |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_CACHE=y |
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CONFIG_CMD_EXT2=y |
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CONFIG_CMD_EXT4=y |
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CONFIG_CMD_EXT4_WRITE=y |
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CONFIG_CMD_FAT=y |
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CONFIG_CMD_FS_GENERIC=y |
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CONFIG_OF_LIBFDT=y |
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CONFIG_MXC_UART=y |
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CONFIG_IMX_THERMAL=y |
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CONFIG_PINCTRL=y |
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CONFIG_PINCTRL_IMX6=y |
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CONFIG_SPL_LIBDISK_SUPPORT=y |
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CONFIG_SPL_LIBCOMMON_SUPPORT=y |
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CONFIG_SPL_LIBGENERIC_SUPPORT=y |
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CONFIG_SPL_SERIAL_SUPPORT=y |
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CONFIG_SPL_GPIO_SUPPORT=y |
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CONFIG_SPL_WATCHDOG_SUPPORT=y |
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CONFIG_SPL_EXT_SUPPORT=y |
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@ -0,0 +1,125 @@ |
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/*
|
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* Copyright (C) 2016 Amarula Solutions B.V. |
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* Copyright (C) 2016 Engicam S.r.l. |
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* |
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* Configuration settings for the Engicam GEAM6UL Starter Kits. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __IMX6UL_GEAM_CONFIG_H |
||||
#define __IMX6UL_GEAM_CONFIG_H |
||||
|
||||
#include <linux/sizes.h> |
||||
#include "mx6_common.h" |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) |
||||
|
||||
/* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE SZ_128K |
||||
|
||||
/* Allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* Environment */ |
||||
#ifndef CONFIG_ENV_IS_NOWHERE |
||||
/* Environment in MMC */ |
||||
# if defined(CONFIG_ENV_IS_IN_MMC) |
||||
# define CONFIG_ENV_OFFSET 0x100000 |
||||
# endif |
||||
#endif |
||||
|
||||
/* Default environment */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x87800000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* UART */ |
||||
#ifdef CONFIG_MXC_UART |
||||
# define CONFIG_MXC_UART_BASE UART1_BASE |
||||
#endif |
||||
|
||||
/* MMC */ |
||||
#ifdef CONFIG_FSL_USDHC |
||||
# define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
# define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
||||
#endif |
||||
|
||||
/* SPL */ |
||||
#ifdef CONFIG_SPL |
||||
# define CONFIG_SPL_MMC_SUPPORT |
||||
|
||||
# include "imx6_spl.h" |
||||
# ifdef CONFIG_SPL_BUILD |
||||
# undef CONFIG_DM_GPIO |
||||
# undef CONFIG_DM_MMC |
||||
# endif |
||||
#endif |
||||
|
||||
#endif /* __IMX6UL_GEAM_CONFIG_H */ |
||||
Loading…
Reference in new issue