Forward port OLIMEX LIME2 Gbit ethernet patch
Required for ethernet to work on some LIME2 revisions.
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aaa9a82581
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a7944dcc11
5 changed files with 73 additions and 5 deletions
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@ -24,8 +24,6 @@ void eth_init_board(void)
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#ifdef CONFIG_RGMII
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#ifdef CONFIG_RGMII
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
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CCM_GMAC_CTRL_GPIT_RGMII);
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CCM_GMAC_CTRL_GPIT_RGMII);
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setbits_le32(&ccm->gmac_clk_cfg,
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CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
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#else
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#else
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
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CCM_GMAC_CTRL_GPIT_MII);
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CCM_GMAC_CTRL_GPIT_MII);
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@ -13,6 +13,8 @@
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#include <errno.h>
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#include <errno.h>
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#include <micrel.h>
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#include <micrel.h>
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#include <phy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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/*
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/*
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* KSZ9021 - KSZ9031 common
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* KSZ9021 - KSZ9031 common
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@ -98,7 +100,7 @@ static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
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};
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};
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static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
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static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
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{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
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{ "rxc-skew-ps", 5, 0, 0x7 }, { "txc-skew-ps", 5, 5, 0x17 }
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};
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};
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static int ksz90x1_of_config_group(struct phy_device *phydev,
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static int ksz90x1_of_config_group(struct phy_device *phydev,
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@ -329,6 +331,13 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
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static int ksz9031_config(struct phy_device *phydev)
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static int ksz9031_config(struct phy_device *phydev)
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{
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{
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int ret;
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int ret;
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#ifdef CONFIG_RGMII
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setbits_le32(&ccm->gmac_clk_cfg,
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CCM_GMAC_CTRL_TX_CLK_DELAY(4));
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#endif
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ret = ksz9031_of_config(phydev);
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ret = ksz9031_of_config(phydev);
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if (ret)
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if (ret)
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@ -9,6 +9,8 @@
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#include <common.h>
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/bitops.h>
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#include <phy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#define PHY_RTL8211x_FORCE_MASTER BIT(1)
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#define PHY_RTL8211x_FORCE_MASTER BIT(1)
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#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
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#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
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@ -78,6 +80,9 @@ static int rtl8211e_probe(struct phy_device *phydev)
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/* RealTek RTL8211x */
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/* RealTek RTL8211x */
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static int rtl8211x_config(struct phy_device *phydev)
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static int rtl8211x_config(struct phy_device *phydev)
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{
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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/* mask interrupt at init; if the interrupt is
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/* mask interrupt at init; if the interrupt is
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@ -86,6 +91,27 @@ static int rtl8211x_config(struct phy_device *phydev)
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
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MIIM_RTL8211x_PHY_INTR_DIS);
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MIIM_RTL8211x_PHY_INTR_DIS);
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/* Check if device is RTL8211CL or RTL8211E */
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if(phydev->drv->uid == 0x1cc912) {
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/* On RTL8211E TX delay must be 0 and
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* phy must be forced to be master
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*/
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(0));
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unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
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/* force manual master/slave configuration */
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reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
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/* force master mode */
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reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
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} else {
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if(phydev->drv->uid == 0x1cc915) {
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/* On RTL8211E make GMAC_TX_CLK_DELAY 2 */
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(2));
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}
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}
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if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
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if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
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unsigned int reg;
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unsigned int reg;
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@ -112,6 +138,7 @@ static int rtl8211x_config(struct phy_device *phydev)
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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0);
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0);
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}
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}
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/* read interrupt status just to clear it */
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/* read interrupt status just to clear it */
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phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
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phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
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@ -11,6 +11,8 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <miiphy.h>
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#include <miiphy.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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/* This code does not check the partner abilities. */
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/* This code does not check the partner abilities. */
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static int smsc_parse_status(struct phy_device *phydev)
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static int smsc_parse_status(struct phy_device *phydev)
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@ -43,6 +45,30 @@ static int smsc_startup(struct phy_device *phydev)
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return smsc_parse_status(phydev);
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return smsc_parse_status(phydev);
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}
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}
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#if 1
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static int olinuxino_smsc_startup(struct phy_device *phydev)
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{
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int ret;
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ret = gpio_request(SUNXI_GPA(17), "lan8710-txerr");
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if(ret)
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return ret;
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gpio_direction_output(SUNXI_GPA(17), 0);
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return genphy_parse_link(phydev);
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}
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static int olinuxino_smsc_shutdown(struct phy_device *phydev)
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{
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sunxi_gpio_set_cfgpin(SUNXI_GPA(17), SUNXI_GPIO_INPUT);
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return 0;
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}
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#endif
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static struct phy_driver lan8700_driver = {
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static struct phy_driver lan8700_driver = {
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.name = "SMSC LAN8700",
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.name = "SMSC LAN8700",
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.uid = 0x0007c0c0,
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.uid = 0x0007c0c0,
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@ -69,8 +95,13 @@ static struct phy_driver lan8710_driver = {
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.mask = 0xffff0,
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.mask = 0xffff0,
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.features = PHY_BASIC_FEATURES,
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.features = PHY_BASIC_FEATURES,
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.config = &genphy_config_aneg,
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.config = &genphy_config_aneg,
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#if 1
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.startup = &olinuxino_smsc_startup,
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.shutdown = &olinuxino_smsc_shutdown,
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#else
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.startup = &genphy_startup,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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.shutdown = &genphy_shutdown,
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#endif
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};
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};
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static struct phy_driver lan8740_driver = {
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static struct phy_driver lan8740_driver = {
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@ -291,6 +291,9 @@ extern int soft_i2c_gpio_scl;
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#ifdef CONFIG_SUN7I_GMAC
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#ifdef CONFIG_SUN7I_GMAC
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#define CONFIG_PHY_REALTEK
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#define CONFIG_PHY_REALTEK
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#define CONFIG_PHY_MICREL
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#define CONFIG_PHY_MICREL_KSZ9031
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#define CONFIG_PHY_SMSC
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#endif
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#endif
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#ifdef CONFIG_USB_EHCI_HCD
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#ifdef CONFIG_USB_EHCI_HCD
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