Enough time has passed since these boards were moved to Orphan. Remove.
- Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h}
- Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS),
defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD)
- Remove the entries from boards.cfg
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
b8a49bdaaa
commit
aa6e1e45cf
@ -1,60 +0,0 @@ |
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/*
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* A collection of structures, addresses, and values associated with |
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* the Motorola 860 ADS board. Copied from the MBX stuff. |
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* Magnus Damm added defines for 8xxrom and extended bd_info. |
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* Helmut Buchsbaum added bitvalues for BCSRx |
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* |
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
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* |
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* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com |
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* |
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* Values common to all FADS family boards are in board/fads/fads.h |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/* Board type */ |
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#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ |
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/* Processor type */ |
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#define CONFIG_MPC860 1 |
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#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#undef CONFIG_8xx_CONS_SMC2 |
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#undef CONFIG_8xx_CONS_NONE |
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#define CONFIG_BAUDRATE 38400 /* Console baudrate */ |
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#if 0 |
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#define CONFIG_SYS_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */ |
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#else |
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#define CONFIG_SYS_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ |
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#endif |
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#define CONFIG_SYS_PLPRCR (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
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#define CONFIG_DRAM_50MHZ 1 |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_IMMAP |
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#define CONFIG_CMD_PCMCIA |
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#define CONFIG_CMD_PING |
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/* This is picked up again in fads.h */ |
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#define FADS_COMMANDS_ALREADY_DEFINED |
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#include "../../board/fads/fads.h" |
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#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ |
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#endif /* __CONFIG_H */ |
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@ -1,472 +0,0 @@ |
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/*
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* A collection of structures, addresses, and values associated with |
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* the Motorola 860T FADS board. Copied from the MBX stuff. |
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* Magnus Damm added defines for 8xxrom and extended bd_info. |
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* Helmut Buchsbaum added bitvalues for BCSRx |
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* |
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
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*/ |
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/*
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* 1999-nov-26: The FADS is using the following physical memorymap: |
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* |
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* ff020000 -> ff02ffff : pcmcia io remapping |
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* ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot |
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* ff000000 -> ff00ffff : IMAP internal in the cpu |
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* e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia |
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* fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot |
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* 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot |
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*/ |
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#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 |
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#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 |
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#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 |
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#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 |
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#define CONFIG_SYS_IMMR 0xFF000000 |
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#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_BASE 0x02800000 |
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#define BCSR_ADDR ((uint) 0xff010000) |
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#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ |
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/* ------------------------------------------------------------------------- */ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
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#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ |
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#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ |
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#define CONFIG_VIDEO 1 /* To enable video controller support */ |
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#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ |
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CONFIG_SYS_I2C_SLAVE 0x7F |
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/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ |
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/* Video related */ |
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#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ |
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#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ |
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#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */ |
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#define CONFIG_VIDEO_SIZE (2*1024*1024) |
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/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */ |
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/* Wireless 56Khz 4PPM keyboard on SMCx */ |
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/*#define CONFIG_KEYBOARD 1 */ |
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#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */ |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC823 1 |
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#define CONFIG_MPC823FADS 1 |
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#define CONFIG_FADS 1 |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#undef CONFIG_8xx_CONS_SMC2 |
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#undef CONFIG_8xx_CONS_NONE |
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#define CONFIG_BAUDRATE 115200 |
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/* Set the CPU speed to 50Mhz on the FADS */ |
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#if 0 |
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#define MPC8XX_FACT 10 /* Multiply by 10 */ |
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#define MPC8XX_XIN 5000000 /* 5 MHz in */ |
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#else |
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#define MPC8XX_FACT 10 /* Multiply by 10 */ |
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#define MPC8XX_XIN 5000000 /* 5 MHz in */ |
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#define CONFIG_SYS_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */ |
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#endif |
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#if 1 |
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#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
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#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ |
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#define CONFIG_BOOTARGS "" |
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#define CONFIG_BOOTCOMMAND \ |
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"bootp ;" \
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"setenv bootargs console=tty0 console=ttyS0 " \
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"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
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"bootm" |
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#else |
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#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ |
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#endif |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_NISDOMAIN |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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#define CONFIG_BOOTP_NTPSERVER |
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#define CONFIG_BOOTP_TIMEOFFSET |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ |
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
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* Also NOTE that it doesn't mean SDRAM - it means MEMORY. |
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*/ |
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#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
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#if 0 |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
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#else |
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#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
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#endif |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
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#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ |
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#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9 |
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* SYPCR can only be written once after reset! |
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*----------------------------------------------------------------------- |
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
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*/ |
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#if defined(CONFIG_WATCHDOG) |
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
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#else |
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
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#endif |
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6 |
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*----------------------------------------------------------------------- |
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* PCMCIA config., multi-function pin tri-state |
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*/ |
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26 |
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*----------------------------------------------------------------------- |
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* Clear Reference Interrupt Status, Timebase freezing enabled |
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*/ |
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31 |
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*----------------------------------------------------------------------- |
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
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*/ |
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
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*----------------------------------------------------------------------- |
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* Reset PLL lock status sticky bit, timer expired status bit and timer * |
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* interrupt status bit - leave PLL multiplication factor unchanged ! |
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*/ |
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#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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*----------------------------------------------------------------------- |
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* Set clock output, timebase and RTC source and divider, |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00) |
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/*-----------------------------------------------------------------------
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* |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CONFIG_SYS_DER 0 |
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller |
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* differently. Normally, you write the option register |
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* first, and then enable the chip select by writing the |
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* base register. For CS0, you must write the base register |
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* first, followed by the option register. |
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*/ |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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/* the other CS:s are determined by looking at parameters in BCSRx */ |
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#define BCSR_SIZE ((uint)(64 * 1024)) |
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#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ |
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
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#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ |
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
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#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
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/* BCSRx - Board Control and Status Registers */ |
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#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
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#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ |
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#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) |
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/*
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* Memory Periodic Timer Prescaler |
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*/ |
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/* periodic timer for refresh */ |
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#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
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#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
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#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
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#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
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#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
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/*
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* MAMR settings for SDRAM |
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*/ |
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/* 8 column SDRAM */ |
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#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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/* 9 column SDRAM */ |
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#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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#define CONFIG_SYS_MAMR 0x13a01114 |
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/* values according to the manual */ |
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#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
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#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
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#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
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/* FADS bitvalues by Helmut Buchsbaum
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* see MPC8xxADS User's Manual for a proper description |
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* of the following structures |
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*/ |
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#define BCSR0_ERB ((uint)0x80000000) |
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#define BCSR0_IP ((uint)0x40000000) |
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#define BCSR0_BDIS ((uint)0x10000000) |
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#define BCSR0_BPS_MASK ((uint)0x0C000000) |
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#define BCSR0_ISB_MASK ((uint)0x01800000) |
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#define BCSR0_DBGC_MASK ((uint)0x00600000) |
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#define BCSR0_DBPC_MASK ((uint)0x00180000) |
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#define BCSR0_EBDF_MASK ((uint)0x00060000) |
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#define BCSR1_FLASH_EN ((uint)0x80000000) |
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#define BCSR1_DRAM_EN ((uint)0x40000000) |
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#define BCSR1_ETHEN ((uint)0x20000000) |
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#define BCSR1_IRDEN ((uint)0x10000000) |
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#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
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#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
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#define BCSR1_BCSR_EN ((uint)0x02000000) |
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#define BCSR1_RS232EN_1 ((uint)0x01000000) |
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#define BCSR1_PCCEN ((uint)0x00800000) |
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#define BCSR1_PCCVCC0 ((uint)0x00400000) |
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#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
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#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
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#define BCSR1_RS232EN_2 ((uint)0x00040000) |
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#define BCSR1_SDRAM_EN ((uint)0x00020000) |
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#define BCSR1_PCCVCC1 ((uint)0x00010000) |
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#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
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#define BCSR2_FLASH_PD_SHIFT 28 |
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
||||
#define BCSR2_DRAM_PD_SHIFT 23 |
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800) |
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
||||
#define BCSR3_BREVNR0 ((ushort)0x0080) |
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
||||
#define BCSR3_BREVN1 ((ushort)0x0008) |
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000) |
||||
#define BCSR4_TFPLDL ((uint)0x40000000) |
||||
#define BCSR4_TPSQEL ((uint)0x20000000) |
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860SAR |
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860SAR */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETH_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_SPEED ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG0 ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VCCO ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHFDE ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG1 ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHRST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC850 |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
#endif /* CONFIG_MPC850 */ |
||||
|
||||
#define CONFIG_DRAM_50MHZ 1 |
||||
#define CONFIG_SDRAM_50MHZ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
/*
|
||||
* MPC8xx CPM Options |
||||
*/ |
||||
#define CONFIG_SCC_ENET 1 |
||||
#define CONFIG_SCC2_ENET 1 |
||||
#undef CONFIG_FEC_ENET |
||||
#undef CONFIG_CPM_IIC |
||||
#undef CONFIG_UCODE_PATCH |
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
|
||||
/* PCMCIA configuration */ |
||||
|
||||
#define PCMCIA_MAX_SLOTS 1 |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_DAUGHTERBOARD |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,415 +0,0 @@ |
||||
/*
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T FADS board. Copied from the MBX stuff. |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
*/ |
||||
|
||||
/*
|
||||
* 1999-nov-26: The FADS is using the following physical memorymap: |
||||
* |
||||
* ff020000 -> ff02ffff : pcmcia |
||||
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom |
||||
* ff000000 -> ff00ffff : IMAP internal in the cpu |
||||
* fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom |
||||
* 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MPC850 1 |
||||
#define CONFIG_MPC850SAR 1 |
||||
#define CONFIG_FADS 1 |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#if 0 |
||||
#define MPC8XX_FACT 10 /* Multiply by 10 */ |
||||
#define MPC8XX_XIN 50000000 /* 50 MHz in */ |
||||
#else |
||||
#define MPC8XX_FACT 12 /* Multiply by 12 */ |
||||
#define MPC8XX_XIN 4000000 /* 4 MHz in */ |
||||
#endif |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS " " |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#undef CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFF000000 |
||||
#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
* Also NOTE that it doesn't mean SDRAM - it means MEMORY. |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ |
||||
#define CONFIG_SYS_FLASH_BASE 0x02800000 |
||||
#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
||||
#if 0 |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
||||
#endif |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ |
||||
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer * |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << 20) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
/* the other CS:s are determined by looking at parameters in BCSRx */ |
||||
|
||||
|
||||
#define BCSR_ADDR ((uint) 0x02100000) |
||||
#define BCSR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ |
||||
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/* BCSRx - Board Control and Status Registers */ |
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ |
||||
#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_SYS_MAMR 0x13a01114 |
||||
|
||||
/* values according to the manual */ |
||||
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description |
||||
* of the following structures |
||||
*/ |
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000) |
||||
#define BCSR0_IP ((uint)0x40000000) |
||||
#define BCSR0_BDIS ((uint)0x10000000) |
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000) |
||||
#define BCSR0_ISB_MASK ((uint)0x01800000) |
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000) |
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000) |
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000) |
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000) |
||||
#define BCSR1_DRAM_EN ((uint)0x40000000) |
||||
#define BCSR1_ETHEN ((uint)0x20000000) |
||||
#define BCSR1_IRDEN ((uint)0x10000000) |
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
||||
#define BCSR1_BCSR_EN ((uint)0x02000000) |
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000) |
||||
#define BCSR1_PCCEN ((uint)0x00800000) |
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000) |
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000) |
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000) |
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000) |
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
||||
#define BCSR2_FLASH_PD_SHIFT 28 |
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
||||
#define BCSR2_DRAM_PD_SHIFT 23 |
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800) |
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
||||
#define BCSR3_BREVNR0 ((ushort)0x0080) |
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
||||
#define BCSR3_BREVN1 ((ushort)0x0008) |
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000) |
||||
#define BCSR4_TFPLDL ((uint)0x40000000) |
||||
#define BCSR4_TPSQEL ((uint)0x20000000) |
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860SAR |
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860SAR */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETH_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_SPEED ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG0 ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VCCO ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHFDE ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG1 ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHRST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
|
||||
#define CONFIG_DRAM_50MHZ 1 |
||||
#define CONFIG_SDRAM_50MHZ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
|
||||
|
||||
/* PCMCIA configuration */ |
||||
|
||||
#define PCMCIA_MAX_SLOTS 2 |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_DAUGHTERBOARD |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,58 +0,0 @@ |
||||
/*
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T FADS board. Copied from the MBX stuff. |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
* |
||||
* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com |
||||
* |
||||
* Values common to all FADS family boards are in board/fads/fads.h |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* board type */ |
||||
#define CONFIG_FADS 1 /* old/new FADS + new ADS */ |
||||
|
||||
/* processor type */ |
||||
#define CONFIG_MPC860T 1 /* 860T */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 38400 |
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
|
||||
#if 0 /* old FADS */
|
||||
# define CONFIG_SYS_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ |
||||
#else /* new FADS */ |
||||
# define CONFIG_SYS_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_PLPRCR (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
#define CONFIG_DRAM_50MHZ 1 |
||||
#define CONFIG_SDRAM_50MHZ 1 |
||||
|
||||
#include "../../board/fads/fads.h" |
||||
|
||||
#ifdef USE_REAL_FLASH_VALUES |
||||
/*
|
||||
* These values fit our FADS860T ... |
||||
* The "default" behaviour with 1Mbyte initial doesn't work for us! |
||||
*/ |
||||
#undef CONFIG_SYS_OR0_PRELIM |
||||
#undef CONFIG_SYS_BR0_PRELIM |
||||
#define CONFIG_SYS_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ |
||||
#define CONFIG_SYS_BR0_PRELIM 0x02800001 /* Real values for the board */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_DAUGHTERBOARD /* FADS has processor-specific daughterboard */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue