Coding style cleanup, update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,49 @@
+commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Fri Jul 27 14:43:59 2007 +0200
+
+    [ADS5121] Support for the ADS5121 board
+
+    The following MPC5121e subsystems are supported:
+
+    - low-level CPU init
+    - NOR Boot Flash (common CFI driver)
+    - DDR SDRAM
+    - FEC
+    - I2C
+    - Watchdog
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+    Signed-off-by: Jan Wrobel <wrr@semihalf.com>
+
+commit 1863cfb7b100ba0ee3401799457a01dc058745f8
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Fri Jul 27 14:22:04 2007 +0200
+
+    [PPC] Remove unused MSR_USER definition
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit cc3023b9f95d7ac959a764471a65001062aecf41
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Thu Jul 19 17:12:28 2007 +0200
+
+    Fix breakage of 8xx boards from recent commit.
+
+    This patch fixes the negative consequences for 8xx of the recent
+    "ppc4xx: Clean up 440 exceptions handling" commit.
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 3a6cab844cf74f76639d795e0be8717e02c86af7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Jul 14 22:51:02 2007 +0200
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 011595307731a7a67a7445d107c279d031e8ab97
 Author: Heiko Schocher <hs@pollux.denx.de>
 Date:	Sat Jul 14 01:06:58 2007 +0200

include/configs/ads5121.h

@@ -65,48 +65,49 @@
 #define CFG_SDRAM_BASE		CFG_DDR_BASE
 
 /* DDR Controller Configuration
-
-SYS_CFG:
- 	[31:31]	MDDRC Soft Reset:	Diabled
-	[30:30]	DRAM CKE pin:		Enabled
-	[29:29]	DRAM CLK:		Enabled
-	[28:28]	Command Mode:		Enabled (For initialization only)    
-	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
-	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
-	[20:19]	Read Test:		DON'T USE
-	[18:18]	Self Refresh:		Enabled
-	[17:17]	16bit Mode:		Disabled
-	[16:13] Ready Delay:		2
-	[12:12]	Half DQS Delay:		Disabled
-	[11:11]	Quarter DQS Delay:	Disabled
-	[10:08]	Write Delay:		2
-	[07:07]	Early ODT:		Disabled
-	[06:06]	On DIE Termination:	Disabled
-	[05:05]	FIFO Overflow Clear:	DON'T USE here
-	[04:04]	FIFO Underflow Clear:	DON'T USE here
-	[03:03]	FIFO Overflow Pending:	DON'T USE here
-	[02:02]	FIFO Underlfow Pending:	DON'T USE here
-	[01:01]	FIFO Overlfow Enabled:	Enabled
-	[00:00]	FIFO Underflow Enabled:	Enabled
- TIME_CFG0
- 	[31:16]	DRAM Refresh Time:	0 CSB clocks	
-	[15:8]	DRAM Command Time:	0 CSB clocks
-	[07:00]	DRAM Precharge Time:	0 CSB clocks
- TIME_CFG1
- 	[31:26]	DRAM tRFC:
-	[25:21]	DRAM tWR1:
-	[20:17]	DRAM tWRT1:
-	[16:11]	DRAM tDRR:
-	[10:05]	DRAM tRC:
-	[04:00]	DRAM tRAS:
- TIME_CFG2
- 	[31:28]	DRAM tRCD:
-	[27:23]	DRAM tFAW:
-	[22:19]	DRAM tRTW1:
-	[18:15]	DRAM tCCD:
-	[14:10] DRAM tRTP:
-	[09:05]	DRAM tRP:
-	[04:00] DRAM tRPA */
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
 
 #define CFG_MDDRC_SYS_CFG	0xF8604200
 #define CFG_MDDRC_SYS_CFG_RUN	0xE8604200