@ -433,39 +433,3 @@ fiq:
bl d o _ f i q
# endif
.align 5
.globl reset_cpu
reset_cpu :
# ifdef C O N F I G _ S 3 C 2 4 0 0
bl d i s a b l e _ i n t e r r u p t s
# ifdef C O N F I G _ T R A B
bl d i s a b l e _ v f d
# endif
ldr r1 , _ r W T C O N
ldr r2 , _ r W T C N T
/* Disable watchdog */
mov r3 , #0x0000
str r3 , [ r1 ]
/* Initialize watchdog timer count register */
mov r3 , #0x0001
str r3 , [ r2 ]
/* Enable watchdog timer; assert reset at timer timeout */
mov r3 , #0x0021
str r3 , [ r1 ]
_loop_forever :
b _ l o o p _ f o r e v e r
_rWTCON :
.word 0x15300000
_rWTCNT :
.word 0x15300008
# else / * ! C O N F I G _ S 3 C 2 4 0 0 * /
mov i p , #0
mcr p15 , 0 , i p , c7 , c7 , 0 @ invalidate cache
mcr p15 , 0 , i p , c8 , c7 , 0 @ flush TLB (v4)
mrc p15 , 0 , i p , c1 , c0 , 0 @ get ctrl register
bic i p , i p , #0x000f @ ............wcam
bic i p , i p , #0x2100 @ ..v....s........
mcr p15 , 0 , i p , c1 , c0 , 0 @ ctrl register
mov p c , r0
# endif / * C O N F I G _ S 3 C 2 4 0 0 * /