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* Patch by Robert Schwebel, 10 Jun 2004:

Browse Source 
Add support for Intel K3 strata flash.

* Some cleanup

* Patch by Thomas Brand, 10 Jun 2004:
  Fix "loads" command on DK1S10 board
master
wdenk 20 years ago
parent 681334540d
commit b54d32b40d
9 changed files with 43 additions and 33 deletions
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  1. 6
      CHANGELOG
  2. 2
      board/ispan/ispan.c
  3. 32
      board/mx1ads/syncflash.c
  4. 2
      common/cmd_jffs2.c
  5. 2
      include/bmp_logo.h
  6. 1
      include/configs/DK1S10.h
  7. 3
      include/configs/FADS823.h
  8. 3
      include/configs/FADS850SAR.h
  9. 25
      include/flash.h

6
CHANGELOG
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@ -2,6 +2,12 @@
Changes since U-Boot 1.1.1: Changes since U-Boot 1.1.1:
====================================================================== ======================================================================
* Patch by Robert Schwebel, 10 Jun 2004:
Add support for Intel K3 strata flash.
* Patch by Thomas Brand, 10 Jun 2004:
Fix "loads" command on DK1S10 board
* Patch by Yuli Barcohen, 09 Jun 2004: * Patch by Yuli Barcohen, 09 Jun 2004:
Add support for 8MB flash SIMM and JFFS2 file system on Add support for 8MB flash SIMM and JFFS2 file system on
Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).

2
board/ispan/ispan.c
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@ -236,6 +236,7 @@ static int seeprom_read (int addr, uchar * data, int size)
* Serial EEPROM conected to the PSpan bridge. We keep it as * Serial EEPROM conected to the PSpan bridge. We keep it as
* simple as possible. * simple as possible.
*/ */
#ifdef DEBUG
static int hwc_flash_size (void) static int hwc_flash_size (void)
{ {
uchar byte; uchar byte;
@ -273,6 +274,7 @@ static int hwc_local_sdram_size (void)
} }
return -1; return -1;
} }
#endif /* DEBUG */
static int hwc_main_sdram_size (void) static int hwc_main_sdram_size (void)
{ {

32
board/mx1ads/syncflash.c
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@ -33,26 +33,26 @@ typedef unsigned long * p_u32;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Following Setting is for CSD1 */ /* Following Setting is for CSD1 */
#define SFCTL 0x00221004 #define SFCTL 0x00221004
#define reg_SFCTL __REG(SFCTL) #define reg_SFCTL __REG(SFCTL)
#define SYNCFLASH_A10 (0x00100000) #define SYNCFLASH_A10 (0x00100000)
#define CMD_NORMAL (0x81020300) /* Normal Mode */ #define CMD_NORMAL (0x81020300) /* Normal Mode */
#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ #define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ #define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ #define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ #define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) #define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ #define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
/* LCR Command */ /* LCR Command */
#define LCR_READSTATUS (0x0001C000) /* 0x70 */ #define LCR_READSTATUS (0x0001C000) /* 0x70 */
#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ #define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ #define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ #define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ #define LCR_SR_CLEAR (0x00014000) /* 0x50 */
/* Get Status register */ /* Get Status register */
@ -330,5 +330,3 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
return ERR_OK; return ERR_OK;
} }

2
common/cmd_jffs2.c
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@ -103,7 +103,7 @@ jffs2_part_info(int part_num)
memset(&part, 0, sizeof(part)); memset(&part, 0, sizeof(part));
part.offset = CONFIG_JFFS2_NAND_OFF; part.offset = (char *)CONFIG_JFFS2_NAND_OFF;
part.size = CONFIG_JFFS2_NAND_SIZE; /* the bigger size the slower jffs2 */ part.size = CONFIG_JFFS2_NAND_SIZE; /* the bigger size the slower jffs2 */
#ifndef CONFIG_JFFS2_NAND_DEV #ifndef CONFIG_JFFS2_NAND_DEV

2
include/bmp_logo.h
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@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = {
0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999,
0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3,
0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA,
0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF,
}; };
unsigned char bmp_logo_bitmap[] = { unsigned char bmp_logo_bitmap[] = {

1
include/configs/DK1S10.h
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@ -142,6 +142,7 @@
#if (CFG_NIOS_CPU_UART_NUMS != 0) #if (CFG_NIOS_CPU_UART_NUMS != 0)
#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ #define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#if (CFG_NIOS_CPU_UART0_BR != 0) #if (CFG_NIOS_CPU_UART0_BR != 0)
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */

3
include/configs/FADS823.h
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@ -366,8 +366,9 @@
#define BCSR1_PCCVCC1 ((uint)0x00010000) #define BCSR1_PCCVCC1 ((uint)0x00010000)
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
#define BCSR2_FLASH_PD_SHIFT 28
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT (23) #define BCSR2_DRAM_PD_SHIFT 23
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) #define BCSR2_DBREVNR_MASK ((uint)0x00030000)

3
include/configs/FADS850SAR.h
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@ -333,8 +333,9 @@
#define BCSR1_PCCVCC1 ((uint)0x00010000) #define BCSR1_PCCVCC1 ((uint)0x00010000)
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
#define BCSR2_FLASH_PD_SHIFT 28
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT (23) #define BCSR2_DRAM_PD_SHIFT 23
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) #define BCSR2_DBREVNR_MASK ((uint)0x00030000)

25
include/flash.h
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@ -248,9 +248,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */ #define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */ #define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */
#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ #define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */
#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ #define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
@ -330,10 +330,6 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ #define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ #define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
#define FLASH_28F320J3A 0x007C /* INTEL 28F320J3A ( 32M = 128K x 32) */
#define FLASH_28F640J3A 0x007D /* INTEL 28F640J3A ( 64M = 128K x 64) */
#define FLASH_28F128J3A 0x007E /* INTEL 28F128J3A (128M = 128K x 128) */
#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ #define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ #define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ #define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
@ -364,15 +360,20 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ #define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ #define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ #define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ #define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
#define FLASH_28F256L18T 0x00B0
#define FLASH_28F256K3 0x00A8
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ #define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
#define FLASH_AMDL163B 0x00B3 #define FLASH_AMDL163B 0x00B3
#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
#define FLASH_FUJLV650 0x00B4 /* Fujitsu MBM 29LV650UE/651UE */ #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
#define FLASH_MT28S4M16LC 0x00B5 /* Micron MT28S4M16LC */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */

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