common/lcd code is full of platform-specific code and definitions, which ideally should reside with the respective driver code. Take a step towards that goal by moving platform-specific structs from lcd.h to their own header files. The structs for the generic case (the #else for all the platform-specific cases) is retained in lcd.h as the default case. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>master
Nikita Kiryanov
9 years ago
committed by
Anatolij Gustschin
parent
7f641d53bb
commit
baaa7dd706
@ -0,0 +1,38 @@ |
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/*
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* atmel_lcd.h - Atmel LCD Controller structures |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef _ATMEL_LCD_H_ |
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#define _ATMEL_LCD_H_ |
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typedef struct vidinfo { |
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ushort vl_col; /* Number of columns (i.e. 640) */ |
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ushort vl_row; /* Number of rows (i.e. 480) */ |
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u_long vl_clk; /* pixel clock in ps */ |
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/* LCD configuration register */ |
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u_long vl_sync; /* Horizontal / vertical sync */ |
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u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ |
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u_long vl_tft; /* 0 = passive, 1 = TFT */ |
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u_long vl_cont_pol_low; /* contrast polarity is low */ |
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u_long vl_clk_pol; /* clock polarity */ |
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/* Horizontal control register. */ |
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u_long vl_hsync_len; /* Length of horizontal sync */ |
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u_long vl_left_margin; /* Time from sync to picture */ |
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u_long vl_right_margin; /* Time from picture to sync */ |
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/* Vertical control register. */ |
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u_long vl_vsync_len; /* Length of vertical sync */ |
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u_long vl_upper_margin; /* Time from sync to picture */ |
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u_long vl_lower_margin; /* Time from picture to sync */ |
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u_long mmio; /* Memory mapped registers */ |
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} vidinfo_t; |
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#endif |
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@ -0,0 +1,81 @@ |
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/*
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* exynos_lcd.h - Exynos LCD Controller structures |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _EXYNOS_LCD_H_ |
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#define _EXYNOS_LCD_H_ |
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enum { |
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FIMD_RGB_INTERFACE = 1, |
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FIMD_CPU_INTERFACE = 2, |
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}; |
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enum exynos_fb_rgb_mode_t { |
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MODE_RGB_P = 0, |
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MODE_BGR_P = 1, |
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MODE_RGB_S = 2, |
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MODE_BGR_S = 3, |
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}; |
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typedef struct vidinfo { |
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ushort vl_col; /* Number of columns (i.e. 640) */ |
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ushort vl_row; /* Number of rows (i.e. 480) */ |
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ushort vl_width; /* Width of display area in millimeters */ |
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ushort vl_height; /* Height of display area in millimeters */ |
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/* LCD configuration register */ |
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u_char vl_freq; /* Frequency */ |
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u_char vl_clkp; /* Clock polarity */ |
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u_char vl_oep; /* Output Enable polarity */ |
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u_char vl_hsp; /* Horizontal Sync polarity */ |
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u_char vl_vsp; /* Vertical Sync polarity */ |
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u_char vl_dp; /* Data polarity */ |
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u_char vl_bpix; /* Bits per pixel */ |
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/* Horizontal control register. Timing from data sheet */ |
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u_char vl_hspw; /* Horz sync pulse width */ |
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u_char vl_hfpd; /* Wait before of line */ |
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u_char vl_hbpd; /* Wait end of line */ |
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/* Vertical control register. */ |
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u_char vl_vspw; /* Vertical sync pulse width */ |
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u_char vl_vfpd; /* Wait before of frame */ |
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u_char vl_vbpd; /* Wait end of frame */ |
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u_char vl_cmd_allow_len; /* Wait end of frame */ |
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unsigned int win_id; |
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unsigned int init_delay; |
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unsigned int power_on_delay; |
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unsigned int reset_delay; |
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unsigned int interface_mode; |
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unsigned int mipi_enabled; |
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unsigned int dp_enabled; |
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unsigned int cs_setup; |
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unsigned int wr_setup; |
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unsigned int wr_act; |
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unsigned int wr_hold; |
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unsigned int logo_on; |
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unsigned int logo_width; |
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unsigned int logo_height; |
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int logo_x_offset; |
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int logo_y_offset; |
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unsigned long logo_addr; |
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unsigned int rgb_mode; |
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unsigned int resolution; |
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/* parent clock name(MPLL, EPLL or VPLL) */ |
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unsigned int pclk_name; |
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/* ratio value for source clock from parent clock. */ |
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unsigned int sclk_div; |
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unsigned int dual_lcd_enabled; |
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} vidinfo_t; |
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void init_panel_info(vidinfo_t *vid); |
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#endif |
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@ -0,0 +1,43 @@ |
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/*
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* mpc823_lcd.h - MPC823 LCD Controller structures |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _MPC823_LCD_H_ |
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#define _MPC823_LCD_H_ |
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/*
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* LCD controller stucture for MPC823 CPU |
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*/ |
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typedef struct vidinfo { |
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ushort vl_col; /* Number of columns (i.e. 640) */ |
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ushort vl_row; /* Number of rows (i.e. 480) */ |
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ushort vl_width; /* Width of display area in millimeters */ |
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ushort vl_height; /* Height of display area in millimeters */ |
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/* LCD configuration register */ |
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u_char vl_clkp; /* Clock polarity */ |
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u_char vl_oep; /* Output Enable polarity */ |
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u_char vl_hsp; /* Horizontal Sync polarity */ |
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u_char vl_vsp; /* Vertical Sync polarity */ |
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u_char vl_dp; /* Data polarity */ |
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u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ |
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u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ |
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u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ |
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u_char vl_clor; /* Color, 0 = mono, 1 = color */ |
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u_char vl_tft; /* 0 = passive, 1 = TFT */ |
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/* Horizontal control register. Timing from data sheet */ |
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ushort vl_wbl; /* Wait between lines */ |
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/* Vertical control register */ |
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u_char vl_vpw; /* Vertical sync pulse width */ |
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u_char vl_lcdac; /* LCD AC timing */ |
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u_char vl_wbf; /* Wait between frames */ |
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} vidinfo_t; |
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#endif |
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@ -0,0 +1,80 @@ |
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/*
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* pxa_lcd.h - PXA LCD Controller structures |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _PXA_LCD_H_ |
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#define _PXA_LCD_H_ |
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/*
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* PXA LCD DMA descriptor |
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*/ |
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struct pxafb_dma_descriptor { |
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u_long fdadr; /* Frame descriptor address register */ |
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u_long fsadr; /* Frame source address register */ |
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u_long fidr; /* Frame ID register */ |
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u_long ldcmd; /* Command register */ |
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}; |
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/*
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* PXA LCD info |
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*/ |
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struct pxafb_info { |
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/* Misc registers */ |
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u_long reg_lccr3; |
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u_long reg_lccr2; |
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u_long reg_lccr1; |
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u_long reg_lccr0; |
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u_long fdadr0; |
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u_long fdadr1; |
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/* DMA descriptors */ |
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struct pxafb_dma_descriptor *dmadesc_fblow; |
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struct pxafb_dma_descriptor *dmadesc_fbhigh; |
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struct pxafb_dma_descriptor *dmadesc_palette; |
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u_long screen; /* physical address of frame buffer */ |
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u_long palette; /* physical address of palette memory */ |
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u_int palette_size; |
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}; |
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/*
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* LCD controller stucture for PXA CPU |
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*/ |
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typedef struct vidinfo { |
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ushort vl_col; /* Number of columns (i.e. 640) */ |
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ushort vl_row; /* Number of rows (i.e. 480) */ |
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ushort vl_width; /* Width of display area in millimeters */ |
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ushort vl_height; /* Height of display area in millimeters */ |
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/* LCD configuration register */ |
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u_char vl_clkp; /* Clock polarity */ |
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u_char vl_oep; /* Output Enable polarity */ |
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u_char vl_hsp; /* Horizontal Sync polarity */ |
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u_char vl_vsp; /* Vertical Sync polarity */ |
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u_char vl_dp; /* Data polarity */ |
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u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ |
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u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ |
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u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ |
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u_char vl_clor; /* Color, 0 = mono, 1 = color */ |
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u_char vl_tft; /* 0 = passive, 1 = TFT */ |
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/* Horizontal control register. Timing from data sheet */ |
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ushort vl_hpw; /* Horz sync pulse width */ |
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u_char vl_blw; /* Wait before of line */ |
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u_char vl_elw; /* Wait end of line */ |
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/* Vertical control register. */ |
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u_char vl_vpw; /* Vertical sync pulse width */ |
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u_char vl_bfw; /* Wait before of frame */ |
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u_char vl_efw; /* Wait end of frame */ |
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/* PXA LCD controller params */ |
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struct pxafb_info pxa; |
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} vidinfo_t; |
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#endif |
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