This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stefano Babic <sbabic@denx.de>master
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if TARGET_VISION2 |
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config SYS_BOARD |
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default "vision2" |
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config SYS_VENDOR |
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default "ttcontrol" |
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config SYS_SOC |
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default "mx5" |
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config SYS_CONFIG_NAME |
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default "vision2" |
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endif |
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VISION2 BOARD |
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M: Stefano Babic <sbabic@denx.de> |
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S: Maintained |
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F: board/ttcontrol/vision2/ |
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F: include/configs/vision2.h |
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F: configs/vision2_defconfig |
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2009 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := vision2.o
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/* |
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* (C) Copyright 2009 |
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* Stefano Babic DENX Software Engineering sbabic@denx.de. |
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* |
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* (C) Copyright 2010 |
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* Klaus Steinhammer TTECH Control Gmbh kst@tttech.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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|
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/* |
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* Boot Device : one of |
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* spi, nand, onenand, sd |
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*/ |
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BOOT_FROM spi |
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|
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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/* |
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* ####################### |
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* ### Disable WDOG ### |
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* ####################### |
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*/ |
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DATA 2 0x73f98000 0x30 |
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/* |
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* ####################### |
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* ### SET DDR Clk ### |
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* ####################### |
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*/ |
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/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */ |
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DATA 4 0x73FD4018 0x000024C0 |
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/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */ |
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DATA 4 0x73FD4038 0x2010241 |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8600 0x00000107 |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8604 0x00000107 |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8608 0x00000187 |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa860c 0x00000187 |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8614 0x00000107 |
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/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */ |
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DATA 4 0x73fa86a8 0x00000187 |
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/* |
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* ####################### |
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* ### Settings IOMUXC ### |
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* ####################### |
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*/ |
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/* |
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* DDR IOMUX configuration |
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* Control, Data, Address pads are in their default state: HIGH DS, FAST SR. |
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS |
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*/ |
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DATA 4 0x73fa84b8 0x000000e7 |
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/* PVTC MAX (at GPC, PGR reg) */ |
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/* DATA 4 0x73FD8004 0x1fc00000 */ |
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/* DQM0 DS high slew rate slow */ |
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DATA 4 0x73fa84d4 0x000000e4 |
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/* DQM1 DS high slew rate slow */ |
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DATA 4 0x73fa84d8 0x000000e4 |
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/* DQM2 DS high slew rate slow */ |
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DATA 4 0x73fa84dc 0x000000e4 |
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/* DQM3 DS high slew rate slow */ |
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DATA 4 0x73fa84e0 0x000000e4 |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */ |
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DATA 4 0x73fa84bc 0x000000c4 |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */ |
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DATA 4 0x73fa84c0 0x000000c4 |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */ |
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DATA 4 0x73fa84c4 0x000000c4 |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */ |
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DATA 4 0x73fa84c8 0x000000c4 |
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/* DRAM_DATA B0 */ |
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DATA 4 0x73fa88a4 0x00000004 |
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/* DRAM_DATA B1 */ |
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DATA 4 0x73fa88ac 0x00000004 |
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/* DRAM_DATA B2 */ |
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DATA 4 0x73fa88b8 0x00000004 |
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/* DRAM_DATA B3 */ |
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DATA 4 0x73fa882c 0x00000004 |
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/* DRAM_DATA B0 slew rate */ |
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DATA 4 0x73fa8878 0x00000000 |
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/* DRAM_DATA B1 slew rate */ |
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DATA 4 0x73fa8880 0x00000000 |
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/* DRAM_DATA B2 slew rate */ |
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DATA 4 0x73fa888c 0x00000000 |
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/* DRAM_DATA B3 slew rate */ |
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DATA 4 0x73fa889c 0x00000000 |
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/* |
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* ####################### |
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* ### Configure SDRAM ### |
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* ####################### |
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*/ |
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/* Configure CS0 */ |
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/* ####################### */ |
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/* ESDCTL0: Enable controller */ |
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DATA 4 0x83fd9000 0x83220000 |
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/* Init DRAM on CS0 */ |
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/* ESDSCR: Precharge command */ |
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DATA 4 0x83fd9014 0x04008008 |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008010 |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008010 |
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/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ |
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DATA 4 0x83fd9014 0x00338018 |
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/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ |
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DATA 4 0x83fd9014 0x0020801a |
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/* ESDSCR */ |
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DATA 4 0x83fd9014 0x00008000 |
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/* ESDSCR: EMR with full Drive strength */ |
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/* DATA 4 0x83fd9014 0x0000801a */ |
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/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */ |
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DATA 4 0x83fd9000 0xC3220000 |
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/* |
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* ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks |
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* DATA 4 0x83fd9004 0xC33574AA |
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*/ |
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/* |
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* micron mDDR |
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* ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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* DATA 4 0x83FD9004 0x101564a8 |
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*/ |
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/* |
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* hynix mDDR |
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* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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*/ |
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DATA 4 0x83FD9004 0x704564a8 |
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/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */ |
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DATA 4 0x83fd9010 0x000a1700 |
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/* Configure CS1 */ |
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/* ####################### */ |
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/* ESDCTL1: Enable controller */ |
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DATA 4 0x83fd9008 0x83220000 |
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/* Init DRAM on CS1 */ |
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/* ESDSCR: Precharge command */ |
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DATA 4 0x83fd9014 0x0400800c |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008014 |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008014 |
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/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ |
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DATA 4 0x83fd9014 0x0033801c |
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/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ |
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DATA 4 0x83fd9014 0x0020801e |
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/* ESDSCR */ |
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DATA 4 0x83fd9014 0x00008004 |
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/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */ |
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DATA 4 0x83fd9008 0xC3220000 |
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/* |
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* ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks |
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* DATA 4 0x83fd900c 0xC33574AA |
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*/ |
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/* |
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* micron mDDR |
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* ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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* DATA 4 0x83FD900C 0x101564a8 |
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*/ |
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/* |
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* hynix mDDR |
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* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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*/ |
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DATA 4 0x83FD900C 0x704564a8 |
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/* ESDSCR (mDRAM configuration finished) */ |
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DATA 4 0x83FD9014 0x00000004 |
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/* ESDSCR - clear "configuration request" bit */ |
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DATA 4 0x83fd9014 0x00000000 |
@ -1,572 +0,0 @@ |
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/*
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* (C) Copyright 2010 |
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
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* |
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* (C) Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/iomux-mx51.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/imx-common/spi.h> |
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#include <i2c.h> |
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#include <mmc.h> |
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#include <power/pmic.h> |
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#include <fsl_esdhc.h> |
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#include <fsl_pmic.h> |
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#include <mc13892.h> |
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#include <linux/fb.h> |
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#include <ipu_pixfmt.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct fb_videomode const nec_nl6448bc26_09c = { |
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"NEC_NL6448BC26-09C", |
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60, /* Refresh */ |
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640, /* xres */ |
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480, /* yres */ |
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37650, /* pixclock = 26.56Mhz */ |
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48, /* left margin */ |
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16, /* right margin */ |
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31, /* upper margin */ |
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12, /* lower margin */ |
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96, /* hsync-len */ |
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2, /* vsync-len */ |
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0, /* sync */ |
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FB_VMODE_NONINTERLACED, /* vmode */ |
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0, /* flag */ |
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}; |
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#ifdef CONFIG_HW_WATCHDOG |
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#include <watchdog.h> |
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void hw_watchdog_reset(void) |
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{ |
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int val; |
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/* toggle watchdog trigger pin */ |
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val = gpio_get_value(IMX_GPIO_NR(3, 2)); |
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val = val ? 0 : 1; |
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gpio_set_value(IMX_GPIO_NR(3, 2), val); |
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} |
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#endif |
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static void init_drive_strength(void) |
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{ |
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static const iomux_v3_cfg_t ddr_pads[] = { |
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NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0), |
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NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0), |
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NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP), |
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NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS, |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS, |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0), |
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NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0), |
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NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0), |
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NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0), |
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NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP), |
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NEW_PAD_CTRL(MX51_GRP_INMODE1, 0), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED), |
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NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3, |
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MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL), |
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, |
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PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
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static void setup_weim(void) |
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{ |
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struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; |
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pweim->cs0gcr1 = 0x004100b9; |
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pweim->cs0gcr2 = 0x00000001; |
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pweim->cs0rcr1 = 0x0a018000; |
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pweim->cs0rcr2 = 0; |
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pweim->cs0wcr1 = 0x0704a240; |
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} |
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static void setup_uart(void) |
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{ |
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static const iomux_v3_cfg_t uart_pads[] = { |
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MX51_PAD_EIM_D25__UART3_RXD, /* console RX */ |
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MX51_PAD_EIM_D26__UART3_TXD, /* console TX */ |
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}; |
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
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} |
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#ifdef CONFIG_MXC_SPI |
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int board_spi_cs_gpio(unsigned bus, unsigned cs) |
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{ |
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return (bus == 0 && cs == 1) ? 121 : -1; |
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} |
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void spi_io_init(void) |
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{ |
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static const iomux_v3_cfg_t spi_pads[] = { |
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS | |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS | |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS | |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), |
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), |
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}; |
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); |
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} |
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static void reset_peripherals(int reset) |
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{ |
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#ifdef CONFIG_VISION2_HW_1_0 |
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static const iomux_v3_cfg_t fec_cfg_pads[] = { |
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/* RXD1 */ |
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL), |
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/* RXD2 */ |
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL), |
||||
/* RXD3 */ |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL), |
||||
/* RXER */ |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL), |
||||
/* COL */ |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL), |
||||
/* RCLK */ |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL), |
||||
/* RXD0 */ |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL), |
||||
}; |
||||
|
||||
static const iomux_v3_cfg_t fec_pads[] = { |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), |
||||
MX51_PAD_NANDF_D9__FEC_RDATA0, |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), |
||||
MX51_PAD_EIM_CS4__FEC_RX_ER, |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), |
||||
}; |
||||
#endif |
||||
|
||||
if (reset) { |
||||
|
||||
/* reset_n is on NANDF_D15 */ |
||||
gpio_direction_output(IMX_GPIO_NR(3, 25), 0); |
||||
|
||||
#ifdef CONFIG_VISION2_HW_1_0 |
||||
/*
|
||||
* set FEC Configuration lines |
||||
* set levels of FEC config lines |
||||
*/ |
||||
gpio_direction_output(IMX_GPIO_NR(3, 11), 0); |
||||
gpio_direction_output(IMX_GPIO_NR(3, 10), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(3, 31), 1); |
||||
|
||||
/* set direction of FEC config lines */ |
||||
gpio_direction_output(IMX_GPIO_NR(2, 27), 0); |
||||
gpio_direction_output(IMX_GPIO_NR(2, 28), 0); |
||||
gpio_direction_output(IMX_GPIO_NR(2, 29), 0); |
||||
gpio_direction_output(IMX_GPIO_NR(2, 23), 1); |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, |
||||
ARRAY_SIZE(fec_cfg_pads)); |
||||
#endif |
||||
|
||||
/* activate reset_n pin */ |
||||
imx_iomux_v3_setup_pad( |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25, |
||||
PAD_CTL_DSE_MAX)); |
||||
} else { |
||||
/* set FEC Control lines */ |
||||
gpio_direction_input(IMX_GPIO_NR(3, 25)); |
||||
udelay(500); |
||||
|
||||
#ifdef CONFIG_VISION2_HW_1_0 |
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, |
||||
ARRAY_SIZE(fec_pads)); |
||||
#endif |
||||
} |
||||
} |
||||
|
||||
static void power_init_mx51(void) |
||||
{ |
||||
unsigned int val; |
||||
struct pmic *p; |
||||
int ret; |
||||
|
||||
ret = pmic_init(I2C_PMIC); |
||||
if (ret) |
||||
return; |
||||
|
||||
p = pmic_get("FSL_PMIC"); |
||||
if (!p) |
||||
return; |
||||
|
||||
/* Write needed to Power Gate 2 register */ |
||||
pmic_reg_read(p, REG_POWER_MISC, &val); |
||||
|
||||
/* enable VCAM with 2.775V to enable read from PMIC */ |
||||
val = VCAMCONFIG | VCAMEN; |
||||
pmic_reg_write(p, REG_MODE_1, val); |
||||
|
||||
/*
|
||||
* Set switchers in Auto in NORMAL mode & STANDBY mode |
||||
* Setup the switcher mode for SW1 & SW2 |
||||
*/ |
||||
pmic_reg_read(p, REG_SW_4, &val); |
||||
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | |
||||
(SWMODE_MASK << SWMODE2_SHIFT))); |
||||
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | |
||||
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT); |
||||
pmic_reg_write(p, REG_SW_4, val); |
||||
|
||||
/* Setup the switcher mode for SW3 & SW4 */ |
||||
pmic_reg_read(p, REG_SW_5, &val); |
||||
val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | |
||||
(SWMODE_MASK << SWMODE3_SHIFT)); |
||||
val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | |
||||
(SWMODE_AUTO_AUTO << SWMODE3_SHIFT); |
||||
pmic_reg_write(p, REG_SW_5, val); |
||||
|
||||
|
||||
/* Set VGEN3 to 1.8V, VCAM to 3.0V */ |
||||
pmic_reg_read(p, REG_SETTING_0, &val); |
||||
val &= ~(VCAM_MASK | VGEN3_MASK); |
||||
val |= VCAM_3_0; |
||||
pmic_reg_write(p, REG_SETTING_0, val); |
||||
|
||||
/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ |
||||
pmic_reg_read(p, REG_SETTING_1, &val); |
||||
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); |
||||
val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; |
||||
pmic_reg_write(p, REG_SETTING_1, val); |
||||
|
||||
/* Configure VGEN3 and VCAM regulators to use external PNP */ |
||||
val = VGEN3CONFIG | VCAMCONFIG; |
||||
pmic_reg_write(p, REG_MODE_1, val); |
||||
udelay(200); |
||||
|
||||
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ |
||||
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | |
||||
VVIDEOEN | VAUDIOEN | VSDEN; |
||||
pmic_reg_write(p, REG_MODE_1, val); |
||||
|
||||
pmic_reg_read(p, REG_POWER_CTL2, &val); |
||||
val |= WDIRESET; |
||||
pmic_reg_write(p, REG_POWER_CTL2, val); |
||||
|
||||
udelay(2500); |
||||
|
||||
} |
||||
#endif |
||||
|
||||
static void setup_gpios(void) |
||||
{ |
||||
static const iomux_v3_cfg_t gpio_pads_1[] = { |
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* CAM_SUP_DISn */ |
||||
NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* DAB Display EN */ |
||||
NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* WDOG_TRIGGER */ |
||||
}; |
||||
|
||||
static const iomux_v3_cfg_t gpio_pads_2[] = { |
||||
NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* Display2 TxEN */ |
||||
NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* DAB Light EN */ |
||||
NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* AUDIO_MUTE */ |
||||
NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* SPARE_OUT */ |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* BEEPER_EN */ |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* POWER_OFF */ |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* FRAM_WE */ |
||||
NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE | |
||||
PAD_CTL_DSE_MED), /* EXPANSION_EN */ |
||||
MX51_PAD_GPIO1_2__PWM1_PWMO, |
||||
}; |
||||
|
||||
unsigned int i; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1)); |
||||
|
||||
/* Now we need to trigger the watchdog */ |
||||
WATCHDOG_RESET(); |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2)); |
||||
|
||||
/*
|
||||
* Set GPIO1_4 to high and output; it is used to reset |
||||
* the system on reboot |
||||
*/ |
||||
gpio_direction_output(IMX_GPIO_NR(1, 4), 1); |
||||
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 7), 0); |
||||
for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++) |
||||
gpio_direction_output(i, 0); |
||||
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 30), 0); |
||||
|
||||
/* Set POWER_OFF high */ |
||||
gpio_direction_output(IMX_GPIO_NR(3, 27), 1); |
||||
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 26), 0); |
||||
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 26), 0); |
||||
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 25), 1); |
||||
|
||||
WATCHDOG_RESET(); |
||||
} |
||||
|
||||
static void setup_fec(void) |
||||
{ |
||||
static const iomux_v3_cfg_t fec_pads[] = { |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | |
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | |
||||
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), |
||||
MX51_PAD_NANDF_CS3__FEC_MDC, |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), |
||||
NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), |
||||
MX51_PAD_NANDF_D9__FEC_RDATA0, |
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3, |
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2, |
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1, |
||||
MX51_PAD_NANDF_D8__FEC_TDATA0, |
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN, |
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER, |
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), |
||||
MX51_PAD_EIM_CS5__FEC_CRS, |
||||
MX51_PAD_EIM_CS4__FEC_RX_ER, |
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), |
||||
}; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
||||
} |
||||
|
||||
struct fsl_esdhc_cfg esdhc_cfg[1] = { |
||||
{MMC_SDHC1_BASE_ADDR}, |
||||
}; |
||||
|
||||
int get_mmc_getcd(u8 *cd, struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) |
||||
*cd = gpio_get_value(IMX_GPIO_NR(1, 0)); |
||||
else |
||||
*cd = 0; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
static const iomux_v3_cfg_t sd1_pads[] = { |
||||
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | |
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), |
||||
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | |
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), |
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | |
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), |
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | |
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), |
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | |
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), |
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | |
||||
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), |
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), |
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), |
||||
}; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); |
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
||||
} |
||||
#endif |
||||
|
||||
void lcd_enable(void) |
||||
{ |
||||
static const iomux_v3_cfg_t lcd_pads[] = { |
||||
MX51_PAD_DI1_PIN2__DI1_PIN2, |
||||
MX51_PAD_DI1_PIN3__DI1_PIN3, |
||||
}; |
||||
|
||||
int ret; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
||||
|
||||
gpio_set_value(IMX_GPIO_NR(1, 2), 1); |
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2, |
||||
NO_PAD_CTRL)); |
||||
|
||||
ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666); |
||||
if (ret) |
||||
puts("LCD cannot be configured\n"); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
|
||||
|
||||
init_drive_strength(); |
||||
|
||||
/* Setup debug led */ |
||||
gpio_direction_output(IMX_GPIO_NR(1, 6), 0); |
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, |
||||
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST)); |
||||
|
||||
/* wait a little while to give the pll time to settle */ |
||||
sdelay(100000); |
||||
|
||||
setup_weim(); |
||||
setup_uart(); |
||||
setup_fec(); |
||||
setup_gpios(); |
||||
|
||||
spi_io_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void backlight(int on) |
||||
{ |
||||
if (on) { |
||||
gpio_set_value(IMX_GPIO_NR(3, 1), 1); |
||||
udelay(10000); |
||||
gpio_set_value(IMX_GPIO_NR(3, 4), 1); |
||||
} else { |
||||
gpio_set_value(IMX_GPIO_NR(3, 1), 0); |
||||
gpio_set_value(IMX_GPIO_NR(3, 4), 0); |
||||
} |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
lcd_enable(); |
||||
|
||||
backlight(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
power_init_mx51(); |
||||
|
||||
reset_peripherals(1); |
||||
udelay(2000); |
||||
reset_peripherals(0); |
||||
udelay(2000); |
||||
|
||||
/* Early revisions require a second reset */ |
||||
#ifdef CONFIG_VISION2_HW_1_0 |
||||
reset_peripherals(1); |
||||
udelay(2000); |
||||
reset_peripherals(0); |
||||
udelay(2000); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Do not overwrite the console |
||||
* Use always serial for U-Boot console |
||||
*/ |
||||
int overwrite_console(void) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: TTControl Vision II CPU V\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int on; |
||||
|
||||
if (argc < 2) |
||||
return cmd_usage(cmdtp); |
||||
|
||||
on = (strcmp(argv[1], "on") == 0); |
||||
backlight(on); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd, |
||||
"Vision2 Backlight", |
||||
"lcdbl [on|off]\n" |
||||
); |
@ -1,7 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_VISION2=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SYS_PROMPT="Vision II U-boot > " |
@ -1,199 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> |
||||
* |
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the MX51-3Stack Freescale board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
|
||||
#define CONFIG_MX51 /* in a mx51 */ |
||||
#define CONFIG_SYS_TEXT_BASE 0x97800000 |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#ifndef MACH_TYPE_TTC_VISION2 |
||||
#define MACH_TYPE_TTC_VISION2 2775 |
||||
#endif |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART3_BASE |
||||
#define CONFIG_MXC_GPIO |
||||
#define CONFIG_MXC_SPI |
||||
#define CONFIG_HW_WATCHDOG |
||||
|
||||
/*
|
||||
* SPI Configs |
||||
* */ |
||||
#define CONFIG_FSL_SF |
||||
#define CONFIG_CMD_SF |
||||
|
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
|
||||
/*
|
||||
* Use gpio 4 pin 25 as chip select for SPI flash |
||||
* This corresponds to gpio 121 |
||||
*/ |
||||
#define CONFIG_SF_DEFAULT_CS 1 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000 |
||||
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 25000000 |
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0 |
||||
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) |
||||
#define CONFIG_ENV_SIZE (4 * 1024) |
||||
|
||||
#define CONFIG_FSL_ENV_IN_SF |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
|
||||
/* PMIC Controller */ |
||||
#define CONFIG_POWER |
||||
#define CONFIG_POWER_SPI |
||||
#define CONFIG_POWER_FSL |
||||
#define CONFIG_FSL_PMIC_BUS 0 |
||||
#define CONFIG_FSL_PMIC_CS 0 |
||||
#define CONFIG_FSL_PMIC_CLK 2500000 |
||||
#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 |
||||
#define CONFIG_FSL_PMIC_BITLEN 32 |
||||
#define CONFIG_RTC_MC13XXX |
||||
|
||||
/*
|
||||
* MMC Configs |
||||
*/ |
||||
#define CONFIG_FSL_ESDHC |
||||
#ifdef CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) |
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1 |
||||
|
||||
#define CONFIG_MMC |
||||
|
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
|
||||
/*
|
||||
* Eth Configs |
||||
*/ |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_MII |
||||
|
||||
#define CONFIG_FEC_MXC |
||||
#define IMX_FEC_BASE FEC_BASE_ADDR |
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_MII |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/***********************************************************
|
||||
* Command definition |
||||
***********************************************************/ |
||||
|
||||
#define CONFIG_CMD_SPI |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"loadaddr=0x90800000\0" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x90000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x10000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR |
||||
#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) |
||||
#define PHYS_SDRAM_2 CSD1_BASE_ADDR |
||||
#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
/* 166 MHz DDR RAM */ |
||||
#define CONFIG_SYS_DDR_CLKSEL 0 |
||||
#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 |
||||
#define CONFIG_SYS_MAIN_PWR_ON |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*
|
||||
* Framebuffer and LCD |
||||
*/ |
||||
#define CONFIG_PREBOOT |
||||
#define CONFIG_VIDEO |
||||
#define CONFIG_VIDEO_IPUV3 |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_CMD_BMP |
||||
#define CONFIG_BMP_16BPP |
||||
#define CONFIG_IPUV3_CLK 133000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
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Reference in new issue