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mxs: clock: Use 'mxs' prefix for methods

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Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
master
Otavio Salvador 12 years ago committed by Stefano Babic
parent 14e26bcfa7
commit bf48fcb61b
8 changed files with 44 additions and 44 deletions
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  1. 46
      arch/arm/cpu/arm926ejs/mxs/clock.c
  2. 6
      arch/arm/include/asm/arch-mxs/clock.h
  3. 6
      board/bluegiga/apx4devkit/apx4devkit.c
  4. 8
      board/denx/m28evk/m28evk.c
  5. 8
      board/freescale/mx28evk/mx28evk.c
  6. 8
      board/schulercontrol/sc_sps_1/sc_sps_1.c
  7. 4
      drivers/mmc/mxsmmc.c
  8. 2
      drivers/spi/mxs_spi.c

46
arch/arm/cpu/arm926ejs/mxs/clock.c
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@ -41,7 +41,7 @@
#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
static uint32_t mx28_get_pclk(void) static uint32_t mxs_get_pclk(void)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -73,7 +73,7 @@ static uint32_t mx28_get_pclk(void)
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
} }
static uint32_t mx28_get_hclk(void) static uint32_t mxs_get_hclk(void)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -88,10 +88,10 @@ static uint32_t mx28_get_hclk(void)
return 0; return 0;
div = clkctrl & CLKCTRL_HBUS_DIV_MASK; div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
return mx28_get_pclk() / div; return mxs_get_pclk() / div;
} }
static uint32_t mx28_get_emiclk(void) static uint32_t mxs_get_emiclk(void)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -116,7 +116,7 @@ static uint32_t mx28_get_emiclk(void)
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
} }
static uint32_t mx28_get_gpmiclk(void) static uint32_t mxs_get_gpmiclk(void)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -143,7 +143,7 @@ static uint32_t mx28_get_gpmiclk(void)
/* /*
* Set IO clock frequency, in kHz * Set IO clock frequency, in kHz
*/ */
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -176,7 +176,7 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
/* /*
* Get IO clock, returns IO clock in kHz * Get IO clock, returns IO clock in kHz
*/ */
static uint32_t mx28_get_ioclk(enum mxs_ioclock io) static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -197,7 +197,7 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
/* /*
* Configure SSP clock frequency, in kHz * Configure SSP clock frequency, in kHz
*/ */
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -216,7 +216,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
if (xtal) if (xtal)
clk = XTAL_FREQ_KHZ; clk = XTAL_FREQ_KHZ;
else else
clk = mx28_get_ioclk(ssp >> 1); clk = mxs_get_ioclk(ssp >> 1);
if (freq > clk) if (freq > clk)
return; return;
@ -241,7 +241,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
/* /*
* Return SSP frequency, in kHz * Return SSP frequency, in kHz
*/ */
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
{ {
struct mxs_clkctrl_regs *clkctrl_regs = struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -263,7 +263,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
if (tmp == 0) if (tmp == 0)
return 0; return 0;
clk = mx28_get_ioclk(ssp >> 1); clk = mxs_get_ioclk(ssp >> 1);
return clk / tmp; return clk / tmp;
} }
@ -271,10 +271,10 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
/* /*
* Set SSP/MMC bus frequency, in kHz) * Set SSP/MMC bus frequency, in kHz)
*/ */
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq) void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{ {
struct mxs_ssp_regs *ssp_regs; struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus); const uint32_t sspclk = mxs_get_sspclk(bus);
uint32_t reg; uint32_t reg;
uint32_t divide, rate, tgtclk; uint32_t divide, rate, tgtclk;
@ -313,26 +313,26 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
{ {
switch (clk) { switch (clk) {
case MXC_ARM_CLK: case MXC_ARM_CLK:
return mx28_get_pclk() * 1000000; return mxs_get_pclk() * 1000000;
case MXC_GPMI_CLK: case MXC_GPMI_CLK:
return mx28_get_gpmiclk() * 1000000; return mxs_get_gpmiclk() * 1000000;
case MXC_AHB_CLK: case MXC_AHB_CLK:
case MXC_IPG_CLK: case MXC_IPG_CLK:
return mx28_get_hclk() * 1000000; return mxs_get_hclk() * 1000000;
case MXC_EMI_CLK: case MXC_EMI_CLK:
return mx28_get_emiclk(); return mxs_get_emiclk();
case MXC_IO0_CLK: case MXC_IO0_CLK:
return mx28_get_ioclk(MXC_IOCLK0); return mxs_get_ioclk(MXC_IOCLK0);
case MXC_IO1_CLK: case MXC_IO1_CLK:
return mx28_get_ioclk(MXC_IOCLK1); return mxs_get_ioclk(MXC_IOCLK1);
case MXC_SSP0_CLK: case MXC_SSP0_CLK:
return mx28_get_sspclk(MXC_SSPCLK0); return mxs_get_sspclk(MXC_SSPCLK0);
case MXC_SSP1_CLK: case MXC_SSP1_CLK:
return mx28_get_sspclk(MXC_SSPCLK1); return mxs_get_sspclk(MXC_SSPCLK1);
case MXC_SSP2_CLK: case MXC_SSP2_CLK:
return mx28_get_sspclk(MXC_SSPCLK2); return mxs_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK: case MXC_SSP3_CLK:
return mx28_get_sspclk(MXC_SSPCLK3); return mxs_get_sspclk(MXC_SSPCLK3);
case MXC_XTAL_CLK: case MXC_XTAL_CLK:
return XTAL_FREQ_KHZ * 1000; return XTAL_FREQ_KHZ * 1000;
} }

6
arch/arm/include/asm/arch-mxs/clock.h
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@ -52,9 +52,9 @@ enum mxs_sspclock {
uint32_t mxc_get_clock(enum mxc_clock clk); uint32_t mxc_get_clock(enum mxc_clock clk);
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq); void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq); void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
/* Compatibility with the FEC Ethernet driver */ /* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) #define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)

6
board/bluegiga/apx4devkit/apx4devkit.c
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@ -43,12 +43,12 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void) int board_early_init_f(void)
{ {
/* IO0 clock at 480MHz */ /* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000); mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */ /* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000); mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */ /* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
return 0; return 0;
} }

8
board/denx/m28evk/m28evk.c
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@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void) int board_early_init_f(void)
{ {
/* IO0 clock at 480MHz */ /* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000); mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */ /* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000); mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */ /* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 160MHz */ /* SSP2 clock at 160MHz */
mx28_set_sspclk(MXC_SSPCLK2, 160000, 0); mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);

8
board/freescale/mx28evk/mx28evk.c
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@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void) int board_early_init_f(void)
{ {
/* IO0 clock at 480MHz */ /* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000); mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */ /* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000); mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */ /* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 160MHz */ /* SSP2 clock at 160MHz */
mx28_set_sspclk(MXC_SSPCLK2, 160000, 0); mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);

8
board/schulercontrol/sc_sps_1/sc_sps_1.c
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@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void) int board_early_init_f(void)
{ {
/* IO0 clock at 480MHz */ /* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000); mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */ /* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000); mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */ /* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 96MHz */ /* SSP2 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);

4
drivers/mmc/mxsmmc.c
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@ -304,7 +304,7 @@ static void mxsmmc_set_ios(struct mmc *mmc)
/* Set the clock speed */ /* Set the clock speed */
if (mmc->clock) if (mmc->clock)
mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
switch (mmc->bus_width) { switch (mmc->bus_width) {
case 1: case 1:
@ -341,7 +341,7 @@ static int mxsmmc_init(struct mmc *mmc)
SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
/* Set initial bit clock 400 KHz */ /* Set initial bit clock 400 KHz */
mx28_set_ssp_busclock(priv->id, 400); mxs_set_ssp_busclock(priv->id, 400);
/* Send initial 74 clock cycles (185 us @ 400 KHz)*/ /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);

2
drivers/spi/mxs_spi.c
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@ -137,7 +137,7 @@ int spi_claim_bus(struct spi_slave *slave)
writel(0, &ssp_regs->hw_ssp_cmd0); writel(0, &ssp_regs->hw_ssp_cmd0);
mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz); mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
return 0; return 0;
} }

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