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@ -208,7 +208,7 @@ in_flash: |
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bl enable_addr_trans |
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bl enable_addr_trans |
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sync |
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sync |
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/* enable and invalidate the data cache */ |
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/* enable the data cache */ |
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bl dcache_enable |
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bl dcache_enable |
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sync |
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sync |
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#ifdef CFG_INIT_RAM_LOCK |
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#ifdef CFG_INIT_RAM_LOCK |
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@ -483,17 +483,29 @@ init_e300_core: /* time t 10 */ |
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1: |
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1: |
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#endif /* CONFIG_WATCHDOG */ |
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#endif /* CONFIG_WATCHDOG */ |
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#if defined(CONFIG_MASK_AER_AO) |
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/* Write the Arbiter Event Enable to mask Address Only traps. */ |
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/* This prevents the dcbz instruction from being trapped when */ |
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/* HID0_ABE Address Broadcast Enable is set and the MEMORY */ |
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/* COHERENCY bit is set in the WIMG bits, which is often */ |
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/* needed for PCI operation. */ |
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lwz r4, 0x0808(r3) |
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rlwinm r0, r4, 0, ~AER_AO |
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stw r0, 0x0808(r3) |
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#endif /* CONFIG_MASK_AER_AO */ |
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/* Initialize the Hardware Implementation-dependent Registers */ |
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/* Initialize the Hardware Implementation-dependent Registers */ |
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/* HID0 also contains cache control */ |
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/* HID0 also contains cache control */ |
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/* - force invalidation of data and instruction caches */ |
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/*------------------------------------------------------*/ |
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/*------------------------------------------------------*/ |
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lis r3, CFG_HID0_INIT@h
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lis r3, CFG_HID0_INIT@h
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ori r3, r3, CFG_HID0_INIT@l
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ori r3, r3, (CFG_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
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SYNC |
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SYNC |
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mtspr HID0, r3 |
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mtspr HID0, r3 |
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lis r3, CFG_HID0_FINAL@h
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lis r3, CFG_HID0_FINAL@h
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ori r3, r3, CFG_HID0_FINAL@l
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ori r3, r3, (CFG_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
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SYNC |
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SYNC |
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mtspr HID0, r3 |
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mtspr HID0, r3 |
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@ -703,8 +715,7 @@ disable_addr_trans: |
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icache_enable: |
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icache_enable: |
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mfspr r3, HID0 |
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mfspr r3, HID0 |
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ori r3, r3, HID0_ICE |
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ori r3, r3, HID0_ICE |
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lis r4, 0 |
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li r4, HID0_ICFI|HID0_ILOCK |
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ori r4, r4, HID0_ILOCK |
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andc r3, r3, r4 |
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andc r3, r3, r4 |
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ori r4, r3, HID0_ICFI |
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ori r4, r3, HID0_ICFI |
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isync |
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isync |
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@ -717,13 +728,10 @@ icache_enable: |
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icache_disable: |
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icache_disable: |
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mfspr r3, HID0 |
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mfspr r3, HID0 |
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lis r4, 0 |
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lis r4, 0 |
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ori r4, r4, HID0_ICE|HID0_ILOCK |
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ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK |
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andc r3, r3, r4 |
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andc r3, r3, r4 |
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ori r4, r3, HID0_ICFI |
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isync |
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isync |
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mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ |
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mtspr HID0, r3 /* clears invalidate, enable and lock */ |
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isync |
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mtspr HID0, r3 /* clears invalidate */ |
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blr |
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blr |
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.globl icache_status
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.globl icache_status
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@ -737,25 +745,24 @@ dcache_enable: |
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mfspr r3, HID0 |
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mfspr r3, HID0 |
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li r5, HID0_DCFI|HID0_DLOCK |
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li r5, HID0_DCFI|HID0_DLOCK |
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andc r3, r3, r5 |
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andc r3, r3, r5 |
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mtspr HID0, r3 /* no invalidate, unlock */ |
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ori r3, r3, HID0_DCE |
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ori r3, r3, HID0_DCE |
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ori r5, r3, HID0_DCFI |
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mtspr HID0, r5 /* enable + invalidate */ |
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mtspr HID0, r3 /* enable */ |
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sync |
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sync |
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mtspr HID0, r3 /* enable, no invalidate */ |
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blr |
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blr |
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.globl dcache_disable
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.globl dcache_disable
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dcache_disable: |
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dcache_disable: |
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mflr r4 |
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bl flush_dcache /* uses r3 and r5 */ |
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mfspr r3, HID0 |
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mfspr r3, HID0 |
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lis r4, 0 |
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li r5, HID0_DCE|HID0_DLOCK |
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ori r4, r4, HID0_DCE|HID0_DLOCK |
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andc r3, r3, r5 |
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andc r3, r3, r4 |
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ori r5, r3, HID0_DCFI |
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ori r4, r3, HID0_DCI |
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sync |
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sync |
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mtspr HID0, r4 /* sets invalidate, clears enable and lock */ |
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mtspr HID0, r5 /* sets invalidate, clears enable and lock */ |
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sync |
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sync |
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mtspr HID0, r3 /* clears invalidate */ |
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mtspr HID0, r3 /* clears invalidate */ |
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mtlr r4 |
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blr |
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blr |
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.globl dcache_status
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.globl dcache_status
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@ -764,6 +771,18 @@ dcache_status: |
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rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 |
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rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 |
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blr |
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blr |
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.globl flush_dcache
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flush_dcache: |
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lis r3, 0 |
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lis r5, CFG_CACHELINE_SIZE |
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1: cmp 0, 1, r3, r5 |
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bge 2f |
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lwz r5, 0(r3) |
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lis r5, CFG_CACHELINE_SIZE |
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addi r3, r3, 0x4 |
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b 1b |
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2: blr |
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.globl get_pvr
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.globl get_pvr
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get_pvr: |
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get_pvr: |
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mfspr r3, PVR |
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mfspr r3, PVR |
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@ -1060,9 +1079,9 @@ lock_ram_in_cache: |
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*/ |
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*/ |
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lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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li r2, ((CFG_INIT_RAM_END & ~31) + \ |
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li r4, ((CFG_INIT_RAM_END & ~31) + \ |
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(CFG_INIT_RAM_ADDR & 31) + 31) / 32 |
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(CFG_INIT_RAM_ADDR & 31) + 31) / 32 |
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mtctr r2 |
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mtctr r4 |
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1: |
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1: |
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dcbz r0, r3 |
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dcbz r0, r3 |
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addi r3, r3, 32 |
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addi r3, r3, 32 |
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@ -1070,7 +1089,7 @@ lock_ram_in_cache: |
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/* Lock the data cache */ |
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/* Lock the data cache */ |
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mfspr r0, HID0 |
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mfspr r0, HID0 |
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ori r0, r0, 0x1000 |
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ori r0, r0, HID0_DLOCK |
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sync |
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sync |
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mtspr HID0, r0 |
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mtspr HID0, r0 |
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sync |
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sync |
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@ -1082,8 +1101,9 @@ unlock_ram_in_cache: |
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/* invalidate the INIT_RAM section */ |
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/* invalidate the INIT_RAM section */ |
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lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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li r2,512 |
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li r4, ((CFG_INIT_RAM_END & ~31) + \ |
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mtctr r2 |
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(CFG_INIT_RAM_ADDR & 31) + 31) / 32 |
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mtctr r4 |
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1: icbi r0, r3 |
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1: icbi r0, r3 |
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dcbi r0, r3 |
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dcbi r0, r3 |
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addi r3, r3, 32 |
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addi r3, r3, 32 |
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@ -1096,9 +1116,10 @@ unlock_ram_in_cache: |
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li r5, HID0_DLOCK|HID0_DCFI |
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li r5, HID0_DLOCK|HID0_DCFI |
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andc r3, r3, r5 /* no invalidate, unlock */ |
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andc r3, r3, r5 /* no invalidate, unlock */ |
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ori r5, r3, HID0_DCFI /* invalidate, unlock */ |
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ori r5, r3, HID0_DCFI /* invalidate, unlock */ |
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sync |
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mtspr HID0, r5 /* invalidate, unlock */ |
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mtspr HID0, r5 /* invalidate, unlock */ |
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mtspr HID0, r3 /* no invalidate, unlock */ |
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sync |
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sync |
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mtspr HID0, r3 /* no invalidate, unlock */ |
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blr |
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blr |
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#endif /* !CONFIG_NAND_SPL */ |
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#endif /* !CONFIG_NAND_SPL */ |
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#endif /* CFG_INIT_RAM_LOCK */ |
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#endif /* CFG_INIT_RAM_LOCK */ |
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