Tom Rini
9 years ago
commit
d81572c272
@ -1,17 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Marek Vasut <marex@denx.de> |
||||
* |
||||
* This file contains stub implementation of |
||||
* invalidate_dcache_range() |
||||
* flush_dcache_range() |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
@ -1,15 +0,0 @@ |
||||
/*
|
||||
* This file contains stub implementation of |
||||
* invalidate_dcache_range() |
||||
* flush_dcache_range() |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
@ -1,17 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Marek Vasut <marex@denx.de> |
||||
* |
||||
* This file contains stub implementation of |
||||
* invalidate_dcache_range() |
||||
* flush_dcache_range() |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
@ -1,17 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Marek Vasut <marex@denx.de> |
||||
* |
||||
* This file contains stub implementation of |
||||
* invalidate_dcache_range() |
||||
* flush_dcache_range() |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop) |
||||
{ |
||||
} |
||||
@ -0,0 +1,44 @@ |
||||
if TARGET_UCP1020 |
||||
|
||||
config SYS_BOARD |
||||
string |
||||
default "ucp1020" |
||||
|
||||
config SYS_VENDOR |
||||
string |
||||
default "Arcturus" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
string |
||||
default "UCP1020" |
||||
|
||||
config SPI_FLASH |
||||
bool |
||||
default y |
||||
|
||||
config SPI_PCI |
||||
bool |
||||
default y |
||||
|
||||
choice |
||||
prompt "Target image select" |
||||
|
||||
config TARGET_UCP1020_NOR |
||||
bool "NOR flash u-boot image" |
||||
|
||||
config TARGET_UCP1020_SPIFLASH |
||||
bool "SPI flash u-boot image" |
||||
|
||||
endchoice |
||||
|
||||
if TARGET_UCP1020_SPIFLASH |
||||
config UCBOOT |
||||
bool |
||||
default y |
||||
|
||||
config SPIFLASH |
||||
bool |
||||
default y |
||||
endif |
||||
|
||||
endif |
||||
@ -0,0 +1,7 @@ |
||||
UCP1020 BOARD |
||||
M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com> |
||||
S: Maintained |
||||
F: board/Arcturus/ucp1020/ |
||||
F: include/configs/UCP1020.h |
||||
F: configs/UCP1020_defconfig |
||||
F: configs/UCP1020_SPIFLASH_defconfig |
||||
@ -0,0 +1,33 @@ |
||||
#
|
||||
# Copyright 2013-2015 Arcturus Networks, Inc.
|
||||
# based on board/freescale/p1_p2_rdb_pc/Makefile
|
||||
# original copyright follows:
|
||||
# Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
MINIMAL=
|
||||
|
||||
ifdef CONFIG_SPL_BUILD |
||||
ifdef CONFIG_SPL_INIT_MINIMAL |
||||
MINIMAL=y
|
||||
endif |
||||
endif |
||||
|
||||
ifdef MINIMAL |
||||
|
||||
obj-y += spl_minimal.o tlb.o law.o
|
||||
|
||||
else |
||||
ifdef CONFIG_SPL_BUILD |
||||
obj-y += spl.o
|
||||
endif |
||||
|
||||
obj-y += ucp1020.o
|
||||
obj-y += ddr.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
||||
obj-y += cmd_arc.o
|
||||
|
||||
endif |
||||
@ -0,0 +1,54 @@ |
||||
The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules |
||||
product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs, |
||||
DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash. |
||||
|
||||
Information on the generic product family can be found here: |
||||
http://www.arcturusnetworks.com/products/ucp1020 |
||||
|
||||
The UCP1020 several configurable options |
||||
======================================== |
||||
|
||||
- the selection of populated phy(s): |
||||
KSZ9031 (current default for eTSEC 1 and 3) |
||||
|
||||
- the selection of boot location: |
||||
SPI Flash or NOR flash |
||||
|
||||
The UCP1020 includes 2 default configurations |
||||
============================================= |
||||
NOR boot image: |
||||
configs/UCP1020_defconfig |
||||
SPI boot image: |
||||
configs/UCP1020_SPIFLASH_defconfig |
||||
|
||||
The UCP1020 adds an additional command in cmd_arc.c to access and program |
||||
SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet |
||||
HW Addresses. |
||||
|
||||
|
||||
Build example |
||||
============= |
||||
|
||||
make distclean |
||||
make UCP1020_defconfig |
||||
make |
||||
|
||||
Default Scripts |
||||
=============== |
||||
A default upgrade scripts is included in the default environment variable example: |
||||
|
||||
B$ run tftpflash |
||||
|
||||
Dual Environment |
||||
================ |
||||
|
||||
This build enables dual / failover environment environment. |
||||
|
||||
NOR Flash Partition declarations and scripts |
||||
============================================ |
||||
Several scripts are available to allow TFTP of images and programming directly |
||||
into defined NOR flash partitions. Examples: |
||||
|
||||
B$ run program0 |
||||
B$ run program1 |
||||
B$ run program2 |
||||
@ -0,0 +1,231 @@ |
||||
/*
|
||||
* Command for accessing Arcturus factory environment. |
||||
* |
||||
* Copyright 2013-2015 Arcturus Networks Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* by Oleksandr G Zhadan et al. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <div64.h> |
||||
#include <malloc.h> |
||||
#include <spi_flash.h> |
||||
|
||||
#include <asm/io.h> |
||||
|
||||
#ifndef CONFIG_SF_DEFAULT_SPEED |
||||
# define CONFIG_SF_DEFAULT_SPEED 1000000 |
||||
#endif |
||||
#ifndef CONFIG_SF_DEFAULT_MODE |
||||
# define CONFIG_SF_DEFAULT_MODE SPI_MODE0 |
||||
#endif |
||||
#ifndef CONFIG_SF_DEFAULT_CS |
||||
# define CONFIG_SF_DEFAULT_CS 0 |
||||
#endif |
||||
#ifndef CONFIG_SF_DEFAULT_BUS |
||||
# define CONFIG_SF_DEFAULT_BUS 0 |
||||
#endif |
||||
|
||||
#define MAX_SERIAL_SIZE 15 |
||||
#define MAX_HWADDR_SIZE 17 |
||||
|
||||
#define FIRM_ADDR1 (0x200 - sizeof(smac)) |
||||
#define FIRM_ADDR2 (0x400 - sizeof(smac)) |
||||
#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) |
||||
#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) |
||||
|
||||
static struct spi_flash *flash; |
||||
char smac[4][18]; |
||||
|
||||
static int ishwaddr(char *hwaddr) |
||||
{ |
||||
if (strlen(hwaddr) == MAX_HWADDR_SIZE) |
||||
if (hwaddr[2] == ':' && |
||||
hwaddr[5] == ':' && |
||||
hwaddr[8] == ':' && |
||||
hwaddr[11] == ':' && |
||||
hwaddr[14] == ':') |
||||
return 0; |
||||
return -1; |
||||
} |
||||
|
||||
static int set_arc_product(int argc, char *const argv[]) |
||||
{ |
||||
int err = 0; |
||||
char *mystrerr = "ERROR: Failed to save factory info in spi location"; |
||||
|
||||
if (argc != 5) |
||||
return -1; |
||||
|
||||
/* Check serial number */ |
||||
if (strlen(argv[1]) != MAX_SERIAL_SIZE) |
||||
return -1; |
||||
|
||||
/* Check HWaddrs */ |
||||
if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) |
||||
return -1; |
||||
|
||||
strcpy(smac[3], argv[1]); |
||||
strcpy(smac[2], argv[2]); |
||||
strcpy(smac[1], argv[3]); |
||||
strcpy(smac[0], argv[4]); |
||||
|
||||
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, |
||||
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); |
||||
|
||||
/*
|
||||
* Save factory defaults |
||||
*/ |
||||
|
||||
if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) { |
||||
printf("%s: %s [1]\n", __func__, mystrerr); |
||||
err++; |
||||
} |
||||
if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) { |
||||
printf("%s: %s [2]\n", __func__, mystrerr); |
||||
err++; |
||||
} |
||||
|
||||
if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) { |
||||
printf("%s: %s [3]\n", __func__, mystrerr); |
||||
err++; |
||||
} |
||||
|
||||
if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) { |
||||
printf("%s: %s [4]\n", __func__, mystrerr); |
||||
err++; |
||||
} |
||||
|
||||
if (err == 4) { |
||||
printf("%s: %s [ALL]\n", __func__, mystrerr); |
||||
return -2; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int get_arc_info(void) |
||||
{ |
||||
int location = 1; |
||||
char *myerr = "ERROR: Failed to read all 4 factory info spi locations"; |
||||
|
||||
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, |
||||
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); |
||||
|
||||
if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) { |
||||
location++; |
||||
if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) { |
||||
location++; |
||||
if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac), |
||||
smac)) { |
||||
location++; |
||||
if (spi_flash_read(flash, FIRM_ADDR4, |
||||
sizeof(smac), smac)) { |
||||
printf("%s: %s\n", __func__, myerr); |
||||
return -2; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
if (smac[3][0] != 0) { |
||||
if (location > 1) |
||||
printf("Using region %d\n", location); |
||||
printf("SERIAL: "); |
||||
if (smac[3][0] == 0xFF) { |
||||
printf("\t<not found>\n"); |
||||
} else { |
||||
printf("\t%s\n", smac[3]); |
||||
setenv("SERIAL", smac[3]); |
||||
} |
||||
} |
||||
|
||||
if (strcmp(smac[2], "00:00:00:00:00:00") == 0) |
||||
return 0; |
||||
|
||||
printf("HWADDR0:"); |
||||
if (smac[2][0] == 0xFF) { |
||||
printf("\t<not found>\n"); |
||||
} else { |
||||
char *ret = getenv("ethaddr"); |
||||
|
||||
if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { |
||||
setenv("ethaddr", smac[2]); |
||||
printf("\t%s (factory)\n", smac[2]); |
||||
} else { |
||||
printf("\t%s\n", ret); |
||||
} |
||||
} |
||||
|
||||
if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { |
||||
setenv("eth1addr", smac[2]); |
||||
setenv("eth2addr", smac[2]); |
||||
return 0; |
||||
} |
||||
|
||||
printf("HWADDR1:"); |
||||
if (smac[1][0] == 0xFF) { |
||||
printf("\t<not found>\n"); |
||||
} else { |
||||
char *ret = getenv("eth1addr"); |
||||
|
||||
if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { |
||||
setenv("eth1addr", smac[1]); |
||||
printf("\t%s (factory)\n", smac[1]); |
||||
} else { |
||||
printf("\t%s\n", ret); |
||||
} |
||||
} |
||||
|
||||
if (strcmp(smac[0], "00:00:00:00:00:00") == 0) { |
||||
setenv("eth2addr", smac[1]); |
||||
return 0; |
||||
} |
||||
|
||||
printf("HWADDR2:"); |
||||
if (smac[0][0] == 0xFF) { |
||||
printf("\t<not found>\n"); |
||||
} else { |
||||
char *ret = getenv("eth2addr"); |
||||
|
||||
if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { |
||||
setenv("eth2addr", smac[0]); |
||||
printf("\t%s (factory)\n", smac[0]); |
||||
} else { |
||||
printf("\t%s\n", ret); |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) |
||||
{ |
||||
const char *cmd; |
||||
int ret = -1; |
||||
|
||||
cmd = argv[1]; |
||||
--argc; |
||||
++argv; |
||||
|
||||
if (strcmp(cmd, "product") == 0) { |
||||
ret = set_arc_product(argc, argv); |
||||
goto done; |
||||
} |
||||
if (strcmp(cmd, "info") == 0) { |
||||
ret = get_arc_info(); |
||||
goto done; |
||||
} |
||||
done: |
||||
if (ret == -1) |
||||
return CMD_RET_USAGE; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
U_BOOT_CMD(arc, 6, 1, do_arc_cmd, |
||||
"Arcturus product command sub-system", |
||||
"product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n" |
||||
"info - show Arcturus factory env\n\n"); |
||||
@ -0,0 +1,161 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c |
||||
* original copyright follows: |
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/processor.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#include <asm/io.h> |
||||
#include <asm/fsl_law.h> |
||||
|
||||
#ifdef CONFIG_SYS_DDR_RAW_TIMING |
||||
#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1) |
||||
/*
|
||||
* Micron MT41J128M16HA-15E |
||||
* */ |
||||
dimm_params_t ddr_raw_timing = { |
||||
.n_ranks = 1, |
||||
.rank_density = 536870912u, |
||||
.capacity = 536870912u, |
||||
.primary_sdram_width = 32, |
||||
.ec_sdram_width = 8, |
||||
.registered_dimm = 0, |
||||
.mirrored_dimm = 0, |
||||
.n_row_addr = 14, |
||||
.n_col_addr = 10, |
||||
.n_banks_per_sdram_device = 8, |
||||
.edc_config = 2, |
||||
.burst_lengths_bitmask = 0x0c, |
||||
|
||||
.tckmin_x_ps = 1650, |
||||
.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ |
||||
.taa_ps = 14050, |
||||
.twr_ps = 15000, |
||||
.trcd_ps = 13500, |
||||
.trrd_ps = 75000, |
||||
.trp_ps = 13500, |
||||
.tras_ps = 40000, |
||||
.trc_ps = 49500, |
||||
.trfc_ps = 160000, |
||||
.twtr_ps = 75000, |
||||
.trtp_ps = 75000, |
||||
.refresh_rate_ps = 7800000, |
||||
.tfaw_ps = 30000, |
||||
}; |
||||
|
||||
#else |
||||
#error Missing raw timing data for this board |
||||
#endif |
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, |
||||
unsigned int controller_number, |
||||
unsigned int dimm_number) |
||||
{ |
||||
const char dimm_model[] = "Fixed DDR on board"; |
||||
|
||||
if ((controller_number == 0) && (dimm_number == 0)) { |
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); |
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); |
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_SYS_DDR_RAW_TIMING */ |
||||
|
||||
#ifdef CONFIG_SYS_DDR_CS0_BNDS |
||||
/* Fixed sdram init -- doesn't use serial presence detect. */ |
||||
phys_size_t fixed_sdram(void) |
||||
{ |
||||
sys_info_t sysinfo; |
||||
char buf[32]; |
||||
size_t ddr_size; |
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs = { |
||||
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
||||
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
||||
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
||||
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 |
||||
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, |
||||
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, |
||||
.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, |
||||
#endif |
||||
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, |
||||
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, |
||||
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, |
||||
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, |
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, |
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, |
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, |
||||
.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, |
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, |
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, |
||||
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
||||
}; |
||||
|
||||
get_sys_info(&sysinfo); |
||||
printf("Configuring DDR for %s MT/s data rate\n", |
||||
strmhz(buf, sysinfo.freq_ddrbus)); |
||||
|
||||
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
||||
|
||||
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); |
||||
|
||||
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, |
||||
ddr_size, LAW_TRGT_IF_DDR_1) < 0) { |
||||
printf("ERROR setting Local Access Windows for DDR\n"); |
||||
return 0; |
||||
}; |
||||
|
||||
return ddr_size; |
||||
} |
||||
#endif |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
int i; |
||||
|
||||
popts->clk_adjust = 6; |
||||
popts->cpo_override = 0x1f; |
||||
popts->write_data_delay = 2; |
||||
popts->half_strength_driver_enable = 1; |
||||
/* Write leveling override */ |
||||
popts->wrlvl_en = 1; |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
popts->wrlvl_start = 0x8; |
||||
popts->trwt_override = 1; |
||||
popts->trwt = 0; |
||||
|
||||
if (pdimm->primary_sdram_width == 64) |
||||
popts->data_bus_width = 0; |
||||
else if (pdimm->primary_sdram_width == 32) |
||||
popts->data_bus_width = 1; |
||||
else |
||||
printf("Error in DDR bus width configuration!\n"); |
||||
|
||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
||||
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; |
||||
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; |
||||
} |
||||
} |
||||
@ -0,0 +1,25 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c |
||||
* original copyright follows: |
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifdef CONFIG_VSC7385_ENET |
||||
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), |
||||
#endif |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), |
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,126 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c |
||||
* original copyright follows: |
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ns16550.h> |
||||
#include <malloc.h> |
||||
#include <mmc.h> |
||||
#include <nand.h> |
||||
#include <i2c.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <spi_flash.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static const u32 sysclk_tbl[] = { |
||||
66666000, 7499900, 83332500, 8999900, |
||||
99999000, 11111000, 12499800, 13333200 |
||||
}; |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
return CONFIG_SYS_L2_SIZE; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio, bus_clk; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
console_init_f(); |
||||
|
||||
/* Set pmuxcr to allow both i2c1 and i2c2 */ |
||||
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); |
||||
setbits_be32(&gur->pmuxcr, |
||||
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); |
||||
|
||||
/* Read back the register to synchronize the write. */ |
||||
in_be32(&gur->pmuxcr); |
||||
|
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); |
||||
#endif |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
||||
plat_ratio >>= 1; |
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
||||
gd->bus_clk = bus_clk; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
bus_clk / 16 / CONFIG_BAUDRATE); |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
puts("\nSD boot...\n"); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
puts("\nSPI Flash boot...\n"); |
||||
#endif |
||||
|
||||
/* copy code to RAM and jump to it - this should not return */ |
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read. |
||||
*/ |
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
/* Pointer is writable since we allocated a register for it */ |
||||
gd = (gd_t *)CONFIG_SPL_GD_ADDR; |
||||
bd_t *bd; |
||||
|
||||
memset(gd, 0, sizeof(gd_t)); |
||||
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); |
||||
memset(bd, 0, sizeof(bd_t)); |
||||
gd->bd = bd; |
||||
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; |
||||
bd->bi_memsize = CONFIG_SYS_L2_SIZE; |
||||
|
||||
probecpu(); |
||||
get_clocks(); |
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
||||
CONFIG_SPL_RELOC_MALLOC_SIZE); |
||||
|
||||
#ifndef CONFIG_SPL_NAND_BOOT |
||||
env_init(); |
||||
#endif |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_initialize(bd); |
||||
#endif |
||||
/* relocate environment function pointers etc. */ |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
||||
gd->env_valid = 1; |
||||
#else |
||||
env_relocate(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SYS_I2C |
||||
i2c_init_all(); |
||||
#else |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
#endif |
||||
|
||||
gd->ram_size = initdram(0); |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
puts("Tertiary program loader running in sram..."); |
||||
#else |
||||
puts("Second program loader running in sram...\n"); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_boot(); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
spi_boot(); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
nand_boot(); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,67 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl_minimal.c |
||||
* original copyright follows: |
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ns16550.h> |
||||
#include <asm/io.h> |
||||
#include <nand.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <asm/global_data.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) |
||||
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); |
||||
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); |
||||
#endif |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
||||
plat_ratio >>= 1; |
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE); |
||||
|
||||
puts("\nNAND boot... "); |
||||
|
||||
/* copy code to RAM and jump to it - this should not return */ |
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read. |
||||
*/ |
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
puts("\nSecond program loader running in sram..."); |
||||
nand_boot(); |
||||
} |
||||
|
||||
void putc(char c) |
||||
{ |
||||
if (c == '\n') |
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); |
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); |
||||
} |
||||
|
||||
void puts(const char *str) |
||||
{ |
||||
while (*str) |
||||
putc(*str++); |
||||
} |
||||
@ -0,0 +1,101 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/tlb.c |
||||
* original copyright follows: |
||||
* Copyright 2010-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
/* W**G* - Flash/promjet, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* *I*G* - PCI memory 1.5G */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI I/O effective: 192K */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256K, 1), |
||||
#endif |
||||
|
||||
#ifdef CONFIG_VSC7385_ENET |
||||
/* *I*G - VSC7385 Switch */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_1M, 1), |
||||
#endif |
||||
#endif /* not SPL */ |
||||
|
||||
#ifdef CONFIG_SYS_NAND_BASE |
||||
/* *I*G - NAND */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_1M, 1), |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || \ |
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) |
||||
/* *I*G - eSDHC/eSPI/NAND boot */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 8, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
#endif /* RAMBOOT/SPL */ |
||||
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR |
||||
/* *I*G - L2SRAM */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, |
||||
0, 11, BOOKE_PAGESZ_256K, 1), |
||||
#if CONFIG_SYS_L2_SIZE >= (256 << 10) |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, |
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 12, BOOKE_PAGESZ_256K, 1) |
||||
#endif |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -0,0 +1,363 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* by Oleksandr G Zhadan et al. |
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c |
||||
* original copyright follows: |
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <hwconfig.h> |
||||
#include <pci.h> |
||||
#include <i2c.h> |
||||
#include <miiphy.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <fsl_mdio.h> |
||||
#include <tsec.h> |
||||
#include <ioports.h> |
||||
#include <netdev.h> |
||||
#include <micrel.h> |
||||
#include <spi_flash.h> |
||||
#include <mmc.h> |
||||
#include <linux/ctype.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <asm/io.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_lbc.h> |
||||
#include <asm/mp.h> |
||||
#include "ucp1020.h" |
||||
|
||||
void spi_set_speed(struct spi_slave *slave, uint hz) |
||||
{ |
||||
/* TO DO: It's actially have to be in spi/ */ |
||||
} |
||||
|
||||
/*
|
||||
* To be compatible with cmd_gpio |
||||
*/ |
||||
int name_to_gpio(const char *name) |
||||
{ |
||||
int gpio = 31 - simple_strtoul(name, NULL, 10); |
||||
|
||||
if (gpio < 16) |
||||
gpio = -1; |
||||
|
||||
return gpio; |
||||
} |
||||
|
||||
void board_gpio_init(void) |
||||
{ |
||||
int i; |
||||
char envname[8], *val; |
||||
|
||||
for (i = 0; i < GPIO_MAX_NUM; i++) { |
||||
sprintf(envname, "GPIO%d", i); |
||||
val = getenv(envname); |
||||
if (val) { |
||||
char direction = toupper(val[0]); |
||||
char level = toupper(val[1]); |
||||
|
||||
if (direction == 'I') { |
||||
gpio_direction_input(i); |
||||
} else { |
||||
if (direction == 'O') { |
||||
if (level == '1') |
||||
gpio_direction_output(i, 1); |
||||
else |
||||
gpio_direction_output(i, 0); |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
val = getenv("PCIE_OFF"); |
||||
if (val) { |
||||
gpio_direction_input(GPIO_PCIE1_EN); |
||||
gpio_direction_input(GPIO_PCIE2_EN); |
||||
} else { |
||||
gpio_direction_output(GPIO_PCIE1_EN, 1); |
||||
gpio_direction_output(GPIO_PCIE2_EN, 1); |
||||
} |
||||
|
||||
val = getenv("SDHC_CDWP_OFF"); |
||||
if (!val) { |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
|
||||
setbits_be32(&gur->pmuxcr, |
||||
(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); |
||||
} |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
return 0; /* Just in case. Could be disable in config file */ |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); |
||||
board_gpio_init(); |
||||
printf("SD/MMC: 4-bit Mode\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_PCI |
||||
void pci_init_board(void) |
||||
{ |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||
|
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
/* invalidate existing TLB entry for flash */ |
||||
disable_tlb(flash_esel); |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */ |
||||
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_phy_config(struct phy_device *phydev) |
||||
{ |
||||
#if defined(CONFIG_PHY_MICREL_KSZ9021) |
||||
int regval; |
||||
static int cnt; |
||||
|
||||
if (cnt++ == 0) |
||||
printf("PHYs address ["); |
||||
|
||||
if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) { |
||||
regval = |
||||
ksz9021_phy_extended_read(phydev, |
||||
MII_KSZ9021_EXT_STRAP_STATUS); |
||||
/*
|
||||
* min rx data delay |
||||
*/ |
||||
ksz9021_phy_extended_write(phydev, |
||||
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, |
||||
0x6666); |
||||
/*
|
||||
* max rx/tx clock delay, min rx/tx control |
||||
*/ |
||||
ksz9021_phy_extended_write(phydev, |
||||
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, |
||||
0xf6f6); |
||||
printf("0x%x", (regval & 0x1f)); |
||||
} else { |
||||
printf("0x%x", (TSEC2_PHY_ADDR & 0x1f)); |
||||
} |
||||
if (cnt == 3) |
||||
printf("] "); |
||||
else |
||||
printf(","); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG) |
||||
regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000); |
||||
if (regval >= 0) |
||||
printf(" (ADDR 0x%x) ", regval & 0x1f); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
static char newkernelargs[256]; |
||||
static u8 id1[16]; |
||||
static u8 id2; |
||||
struct mmc *mmc; |
||||
char *sval, *kval; |
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { |
||||
printf("Error reading i2c IDT6V49205B information!\n"); |
||||
} else { |
||||
printf("IDT6V49205B(0x%02x): ready\n", id1[1]); |
||||
i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); |
||||
if (!(id1[1] & 0x02)) { |
||||
id1[1] |= 0x02; |
||||
i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); |
||||
asm("nop; nop"); |
||||
} |
||||
} |
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0) |
||||
printf("Error reading i2c NCT72 information!\n"); |
||||
else |
||||
printf("NCT72(0x%x): ready\n", id2); |
||||
|
||||
kval = getenv("kernelargs"); |
||||
|
||||
mmc = find_mmc_device(0); |
||||
if (mmc) |
||||
if (!mmc_init(mmc)) { |
||||
printf("MMC/SD card detected\n"); |
||||
if (kval) { |
||||
int n = strlen(defkargs); |
||||
char *tmp = strstr(kval, defkargs); |
||||
|
||||
*tmp = 0; |
||||
strcpy(newkernelargs, kval); |
||||
strcat(newkernelargs, " "); |
||||
strcat(newkernelargs, mmckargs); |
||||
strcat(newkernelargs, " "); |
||||
strcat(newkernelargs, &tmp[n]); |
||||
setenv("kernelargs", newkernelargs); |
||||
} else { |
||||
setenv("kernelargs", mmckargs); |
||||
} |
||||
} |
||||
get_arc_info(); |
||||
|
||||
if (kval) { |
||||
sval = getenv("SERIAL"); |
||||
if (sval) { |
||||
strcpy(newkernelargs, "SN="); |
||||
strcat(newkernelargs, sval); |
||||
strcat(newkernelargs, " "); |
||||
strcat(newkernelargs, kval); |
||||
setenv("kernelargs", newkernelargs); |
||||
} |
||||
} else { |
||||
printf("Error reading kernelargs env variable!\n"); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
struct fsl_pq_mdio_info mdio_info; |
||||
struct tsec_info_struct tsec_info[4]; |
||||
#ifdef CONFIG_TSEC2 |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
#endif |
||||
int num = 0; |
||||
|
||||
#ifdef CONFIG_TSEC1 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 1); |
||||
num++; |
||||
#endif |
||||
#ifdef CONFIG_TSEC2 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 2); |
||||
if (is_serdes_configured(SGMII_TSEC2)) { |
||||
if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) { |
||||
puts("eTSEC2 is in sgmii mode.\n"); |
||||
tsec_info[num].flags |= TSEC_SGMII; |
||||
tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; |
||||
} |
||||
} |
||||
num++; |
||||
#endif |
||||
#ifdef CONFIG_TSEC3 |
||||
SET_STD_TSEC_INFO(tsec_info[num], 3); |
||||
num++; |
||||
#endif |
||||
|
||||
if (!num) { |
||||
printf("No TSECs initialized\n"); |
||||
return 0; |
||||
} |
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; |
||||
mdio_info.name = DEFAULT_MII_NAME; |
||||
|
||||
fsl_pq_mdio_init(bis, &mdio_info); |
||||
|
||||
tsec_eth_init(bis, tsec_info, num); |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
const char *soc_usb_compat = "fsl-usb2-dr"; |
||||
int err, usb1_off, usb2_off; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
FT_FSL_PCI_SETUP; |
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB) |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
||||
/* Delete eLBC node as it is muxed with USB2 controller */ |
||||
if (hwconfig("usb2")) { |
||||
const char *soc_elbc_compat = "fsl,p1020-elbc"; |
||||
int off = fdt_node_offset_by_compatible(blob, -1, |
||||
soc_elbc_compat); |
||||
if (off < 0) { |
||||
printf |
||||
("WARNING: could not find compatible node %s: %s\n", |
||||
soc_elbc_compat, fdt_strerror(off)); |
||||
return off; |
||||
} |
||||
err = fdt_del_node(blob, off); |
||||
if (err < 0) { |
||||
printf("WARNING: could not remove %s: %s\n", |
||||
soc_elbc_compat, fdt_strerror(err)); |
||||
} |
||||
return err; |
||||
} |
||||
#endif |
||||
|
||||
/* Delete USB2 node as it is muxed with eLBC */ |
||||
usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); |
||||
if (usb1_off < 0) { |
||||
printf("WARNING: could not find compatible node %s: %s.\n", |
||||
soc_usb_compat, fdt_strerror(usb1_off)); |
||||
return usb1_off; |
||||
} |
||||
usb2_off = |
||||
fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); |
||||
if (usb2_off < 0) { |
||||
printf("WARNING: could not find compatible node %s: %s.\n", |
||||
soc_usb_compat, fdt_strerror(usb2_off)); |
||||
return usb2_off; |
||||
} |
||||
err = fdt_del_node(blob, usb2_off); |
||||
if (err < 0) { |
||||
printf("WARNING: could not remove %s: %s.\n", |
||||
soc_usb_compat, fdt_strerror(err)); |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc. |
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* by Oleksandr G Zhadan et al. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __UCP1020_H__ |
||||
#define __UCP1020_H__ |
||||
|
||||
#define GPIO0 31 |
||||
#define GPIO1 30 |
||||
#define GPIO2 29 |
||||
#define GPIO3 28 |
||||
#define GPIO4 27 |
||||
#define GPIO5 26 |
||||
#define GPIO6 25 |
||||
#define GPIO7 24 |
||||
#define GPIO8 23 |
||||
#define GPIO9 22 |
||||
#define GPIO10 21 |
||||
#define GPIO11 20 |
||||
#define GPIO12 19 |
||||
#define GPIO13 18 |
||||
#define GPIO14 17 |
||||
#define GPIO15 16 |
||||
#define GPIO_MAX_NUM 16 |
||||
|
||||
#define GPIO_SDHC_CD GPIO8 |
||||
#define GPIO_SDHC_WP GPIO9 |
||||
#define GPIO_USB_PCTL0 GPIO10 |
||||
#define GPIO_PCIE1_EN GPIO11 |
||||
#define GPIO_PCIE2_EN GPIO10 |
||||
#define GPIO_USB_PCTL1 GPIO11 |
||||
|
||||
#define GPIO_WD GPIO15 |
||||
|
||||
static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro"; |
||||
static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw"; |
||||
|
||||
int get_arc_info(void); |
||||
|
||||
#endif |
||||
@ -0,0 +1,8 @@ |
||||
#PBL preamble and RCW header for T1023RDB |
||||
aa55aa55 010e0100 |
||||
#SerDes Protocol: 0x77 |
||||
#Core/DDR: 1400Mhz/1600MT/s with single source clock |
||||
0810000e 00000000 00000000 00000000 |
||||
3b800003 00000012 e8104000 21000000 |
||||
00000000 00000000 00000000 00020800 |
||||
00000130 04020200 00000000 00000006 |
||||
@ -1,7 +1,7 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 010e0100 |
||||
#serdes protocol 1_27_5_11 |
||||
16070019 18101916 00000000 00000000 |
||||
1607001b 18101b16 00000000 00000000 |
||||
04362858 30548c00 ec020000 f5000000 |
||||
00000000 ee0000ee 00000000 000307fc |
||||
00000000 00000000 00000000 00000028 |
||||
|
||||
@ -0,0 +1,95 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* Author: Chunhe Lan <Chunhe.Lan@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/spl.h> |
||||
#include <malloc.h> |
||||
#include <ns16550.h> |
||||
#include <nand.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <i2c.h> |
||||
|
||||
#include "t4rdb.h" |
||||
|
||||
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
return CONFIG_SYS_L3_SIZE; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
return CONFIG_SYS_CLK_FREQ; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
return CONFIG_DDR_CLK_FREQ; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio, sys_clk, ccb_clk; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ |
||||
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); |
||||
|
||||
/* Update GD pointer */ |
||||
gd = (gd_t *)(CONFIG_SPL_GD_ADDR); |
||||
|
||||
/* compiler optimization barrier needed for GCC >= 3.4 */ |
||||
__asm__ __volatile__("" : : : "memory"); |
||||
|
||||
console_init_f(); |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
sys_clk = get_board_sys_clk(); |
||||
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; |
||||
ccb_clk = sys_clk * plat_ratio / 2; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
ccb_clk / 16 / CONFIG_BAUDRATE); |
||||
|
||||
puts("\nSD boot...\n"); |
||||
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
bd_t *bd; |
||||
|
||||
bd = (bd_t *)(gd + sizeof(gd_t)); |
||||
memset(bd, 0, sizeof(bd_t)); |
||||
gd->bd = bd; |
||||
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; |
||||
bd->bi_memsize = CONFIG_SYS_L3_SIZE; |
||||
|
||||
probecpu(); |
||||
get_clocks(); |
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
||||
CONFIG_SPL_RELOC_MALLOC_SIZE); |
||||
|
||||
mmc_initialize(bd); |
||||
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
||||
gd->env_valid = 1; |
||||
|
||||
i2c_init_all(); |
||||
|
||||
gd->ram_size = initdram(0); |
||||
|
||||
mmc_boot(); |
||||
} |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -1,5 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
|
||||
@ -1,5 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
|
||||
@ -1,4 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
|
||||
@ -1,5 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
|
||||
@ -1,4 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
|
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T4240QDS=y |
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T4240EMU=y |
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T4240QDS=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T4240RDB=y |
||||
@ -0,0 +1,6 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_UCP1020=y |
||||
CONFIG_TARGET_UCP1020_SPIFLASH=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_UCP1020=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_UCP1020=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_UCP1020=y |
||||
@ -1,6 +1,24 @@ |
||||
CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. |
||||
CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. |
||||
CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. |
||||
Freescale esdhc-specific options |
||||
|
||||
Accessing ESDHC registers can be determined by ESDHC IP's endian |
||||
mode or processor's endian mode. |
||||
- CONFIG_FSL_ESDHC_ADAPTER_IDENT |
||||
Support Freescale adapter card type identification. This is implemented by |
||||
operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC |
||||
Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot. |
||||
|
||||
SDHC Card ID[0:2] Adapter Card Type |
||||
0b000 reserved |
||||
0b001 eMMC Card Rev4.5 |
||||
0b010 SD/MMC Legacy Card |
||||
0b011 eMMC Card Rev4.4 |
||||
0b100 reserved |
||||
0b101 MMC Card |
||||
0b110 SD Card Rev2.0/3.0 |
||||
0b111 No card is present |
||||
- CONFIG_SYS_FSL_ESDHC_LE |
||||
ESDHC IP is in little-endian mode. Accessing ESDHC registers can be |
||||
determined by ESDHC IP's endian mode or processor's endian mode. |
||||
- CONFIG_SYS_FSL_ESDHC_BE |
||||
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined |
||||
by ESDHC IP's endian mode or processor's endian mode. |
||||
|
||||
- CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. |
||||
|
||||
@ -1,181 +0,0 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* T4240 EMU board configuration file |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_T4240EMU |
||||
#define CONFIG_PHYS_64BIT |
||||
|
||||
#define CONFIG_SYS_NO_FLASH 1 |
||||
#define CONFIG_SYS_FSL_DDR_EMU 1 |
||||
#define CONFIG_SYS_FSL_NO_QIXIS 1 |
||||
#define CONFIG_SYS_FSL_NO_SERDES 1 |
||||
|
||||
#include "t4qds.h" |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_CACHE_FLUSH |
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000 |
||||
#define CONFIG_DDR_CLK_FREQ 133333333 |
||||
#define CONFIG_FSL_TBCLK_EXTRA_DIV 100 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_SPD_BUS_NUM 1 |
||||
#define SPD_EEPROM_ADDRESS1 0x51 |
||||
#define SPD_EEPROM_ADDRESS2 0x52 |
||||
#define SPD_EEPROM_ADDRESS3 0x53 |
||||
#define SPD_EEPROM_ADDRESS4 0x54 |
||||
#define SPD_EEPROM_ADDRESS5 0x55 |
||||
#define SPD_EEPROM_ADDRESS6 0x56 |
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
||||
|
||||
/*
|
||||
* IFC Definitions |
||||
*/ |
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||
/* NOR Flash Timing Params */ |
||||
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
||||
+ 0x8000000) | \
|
||||
CSPR_PORT_SIZE_32 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) |
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
||||
FTIM0_NOR_TEADC(0x1) | \
|
||||
FTIM0_NOR_TEAHC(0x1)) |
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ |
||||
FTIM1_NOR_TRAD_NOR(0x1)) |
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ |
||||
FTIM2_NOR_TCH(0x0) | \
|
||||
FTIM2_NOR_TWP(0x1)) |
||||
#define CONFIG_SYS_NOR_FTIM3 0x04000000 |
||||
#define CONFIG_SYS_IFC_CCR 0x01000000 |
||||
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */ |
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 4000000 |
||||
|
||||
/* Qman/Bman */ |
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 50 |
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE |
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ |
||||
CONFIG_SYS_BMAN_CENA_SIZE) |
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE |
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ |
||||
CONFIG_SYS_QMAN_CENA_SIZE) |
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_SYS_DPAA_PME |
||||
#define CONFIG_SYS_PMAN |
||||
#define CONFIG_SYS_DPAA_DCE |
||||
#define CONFIG_SYS_DPAA_RMAN |
||||
#define CONFIG_SYS_INTERLAKEN |
||||
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
||||
|
||||
#define CONFIG_BOOTDELAY 0 |
||||
|
||||
/*
|
||||
* T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be |
||||
* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way |
||||
* interleaving. It can be cacheline, page, bank, superbank. |
||||
* See doc/README.fsl-ddr for details. |
||||
*/ |
||||
#ifdef CONFIG_PPC_T4240 |
||||
#define CTRL_INTLV_PREFERED 3way_4KB |
||||
#else |
||||
#define CTRL_INTLV_PREFERED cacheline |
||||
#endif |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:" \
|
||||
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
|
||||
"bank_intlv=auto;" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t4240emu/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=t4240emu/t4240emu.dtb\0" \
|
||||
"bdev=sda3\0" |
||||
|
||||
/*
|
||||
* For emulation this causes u-boot to jump to the start of the proof point |
||||
* app code automatically |
||||
*/ |
||||
#define CONFIG_PROOF_POINTS \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"cpu 1 release 0x29000000 - - -;" \
|
||||
"cpu 2 release 0x29000000 - - -;" \
|
||||
"cpu 3 release 0x29000000 - - -;" \
|
||||
"cpu 4 release 0x29000000 - - -;" \
|
||||
"cpu 5 release 0x29000000 - - -;" \
|
||||
"cpu 6 release 0x29000000 - - -;" \
|
||||
"cpu 7 release 0x29000000 - - -;" \
|
||||
"go 0x29000000" |
||||
|
||||
#define CONFIG_HVBOOT \ |
||||
"setenv bootargs config-addr=0x60000000; " \
|
||||
"bootm 0x01000000 - 0x00f00000" |
||||
|
||||
#define CONFIG_LINUX \ |
||||
"errata;" \
|
||||
"setenv othbootargs ignore_loglevel;" \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in new issue