* 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Wire up SPI driver spi: microblaze: Adds driver for Xilinx SPI controller microblaze: intc: Clear interrupt code microblaze: Call serial multi initialization microblaze: Move __udelay implementation microblaze: Remove extern from board.c microblaze: Wire up dts configuration fdt: Add board specific dts inclusion microblaze: Move individual board linker scripts to common script in cpu tree. microblaze: Add gpio.h microblaze: Add missing undefs for UBI and UBIFS microblaze: Expand and correct configuration comments microblaze: Enable ubi support microblaze: Avoid compile error on systems without cfi flash microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>master
Wolfgang Denk
13 years ago
commit
d978780b2e
@ -0,0 +1,41 @@ |
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#ifndef _ASM_MICROBLAZE_GPIO_H_ |
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#define _ASM_MICROBLAZE_GPIO_H_ |
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#include <asm/io.h> |
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static inline int gpio_request(unsigned gpio, const char *label) |
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{ |
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return 0; |
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} |
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static inline int gpio_free(unsigned gpio) |
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{ |
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return 0; |
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} |
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static inline int gpio_direction_input(unsigned gpio) |
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{ |
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return 0; |
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} |
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static inline int gpio_direction_output(unsigned gpio, int value) |
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{ |
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return 0; |
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} |
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static inline int gpio_get_value(unsigned gpio) |
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{ |
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return 0; |
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} |
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static inline int gpio_set_value(unsigned gpio, int value) |
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{ |
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return 0; |
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} |
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static inline int gpio_is_valid(int number) |
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{ |
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return 0; |
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} |
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#endif |
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@ -1,42 +0,0 @@ |
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/*
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* (C) Copyright 2007 Michal Simek |
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* (C) Copyright 2004 Atmark Techno, Inc. |
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* |
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* Michal SIMEK <monstr@monstr.eu> |
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* Yasushi SHOJI <yashi@atmark-techno.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#ifdef CONFIG_SYS_TIMER_0 |
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void __udelay (unsigned long usec) |
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{ |
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int i; |
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i = get_timer (0); |
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while ((get_timer (0) - i) < (usec / 1000)) ; |
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} |
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#else |
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void __udelay (unsigned long usec) |
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{ |
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unsigned int i; |
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for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++); |
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} |
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#endif |
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@ -0,0 +1 @@ |
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/include/ BOARD_DTS |
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@ -0,0 +1,7 @@ |
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/dts-v1/; |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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aliases { |
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} ; |
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} ; |
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@ -0,0 +1,214 @@ |
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/*
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* Xilinx SPI driver |
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* |
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* supports 8 bit SPI transfers only, with or w/o FIFO |
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* |
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* based on bfin_spi.c, by way of altera_spi.c |
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* Copyright (c) 2005-2008 Analog Devices Inc. |
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw> |
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca> |
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net> |
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* |
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* Licensed under the GPL-2 or later. |
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* |
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* [0]: http://www.xilinx.com/support/documentation
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* |
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* [S]: [0]/ip_documentation/xps_spi.pdf |
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* [0]/ip_documentation/axi_spi_ds742.pdf |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <malloc.h> |
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#include <spi.h> |
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#include "xilinx_spi.h" |
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#ifndef CONFIG_SYS_XILINX_SPI_LIST |
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#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } |
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#endif |
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#ifndef CONFIG_XILINX_SPI_IDLE_VAL |
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#define CONFIG_XILINX_SPI_IDLE_VAL 0xff |
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#endif |
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#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \ |
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SPICR_MASTER_MODE | \
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SPICR_SPE) |
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \ |
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SPICR_MANUAL_SS) |
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#define XILSPI_MAX_XFER_BITS 8 |
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static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST; |
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__attribute__((weak)) |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; |
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} |
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__attribute__((weak)) |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); |
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writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr); |
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} |
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__attribute__((weak)) |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); |
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writel(SPISSR_OFF, &xilspi->regs->spissr); |
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} |
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void spi_init(void) |
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{ |
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/* do nothing */ |
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} |
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void spi_set_speed(struct spi_slave *slave, uint hz) |
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{ |
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/* xilinx spi core does not support programmable speed */ |
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} |
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
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unsigned int max_hz, unsigned int mode) |
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{ |
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struct xilinx_spi_slave *xilspi; |
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struct xilinx_spi_reg *regs; |
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if (!spi_cs_is_valid(bus, cs)) { |
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printf("XILSPI error: %s: unsupported bus %d / cs %d\n", |
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__func__, bus, cs); |
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return NULL; |
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} |
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xilspi = malloc(sizeof(*xilspi)); |
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if (!xilspi) { |
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printf("XILSPI error: %s: malloc of SPI structure failed\n", |
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__func__); |
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return NULL; |
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} |
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xilspi->slave.bus = bus; |
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xilspi->slave.cs = cs; |
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xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus]; |
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xilspi->freq = max_hz; |
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xilspi->mode = mode; |
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debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__, |
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bus, cs, xilspi->regs, xilspi->mode, xilspi->freq); |
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return &xilspi->slave; |
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} |
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void spi_free_slave(struct spi_slave *slave) |
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{ |
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); |
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free(xilspi); |
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} |
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int spi_claim_bus(struct spi_slave *slave) |
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{ |
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); |
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u32 spicr; |
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); |
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writel(SPISSR_OFF, &xilspi->regs->spissr); |
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spicr = XILSPI_SPICR_DFLT_ON; |
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if (xilspi->mode & SPI_LSB_FIRST) |
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spicr |= SPICR_LSB_FIRST; |
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if (xilspi->mode & SPI_CPHA) |
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spicr |= SPICR_CPHA; |
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if (xilspi->mode & SPI_CPOL) |
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spicr |= SPICR_CPOL; |
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if (xilspi->mode & SPI_LOOP) |
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spicr |= SPICR_LOOP; |
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writel(spicr, &xilspi->regs->spicr); |
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return 0; |
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} |
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void spi_release_bus(struct spi_slave *slave) |
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{ |
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); |
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); |
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writel(SPISSR_OFF, &xilspi->regs->spissr); |
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writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr); |
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} |
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
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void *din, unsigned long flags) |
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{ |
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); |
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/* assume spi core configured to do 8 bit transfers */ |
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unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS; |
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const unsigned char *txp = dout; |
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unsigned char *rxp = din; |
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unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ |
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debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, |
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slave->bus, slave->cs, bitlen, bytes, flags); |
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if (bitlen == 0) |
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goto done; |
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if (bitlen % XILSPI_MAX_XFER_BITS) { |
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printf("XILSPI warning: %s: Not a multiple of %d bits\n", |
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__func__, XILSPI_MAX_XFER_BITS); |
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flags |= SPI_XFER_END; |
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goto done; |
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} |
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/* empty read buffer */ |
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while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) { |
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readl(&xilspi->regs->spidrr); |
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rxecount--; |
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} |
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if (!rxecount) { |
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printf("XILSPI error: %s: Rx buffer not empty\n", __func__); |
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return -1; |
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} |
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if (flags & SPI_XFER_BEGIN) |
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spi_cs_activate(slave); |
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while (bytes--) { |
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unsigned timeout = /* at least 1usec or greater, leftover 1 */ |
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xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : |
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(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; |
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/* get Tx element from data out buffer and count up */ |
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unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; |
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debug("%s: tx:%x ", __func__, d); |
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/* write out and wait for processing (receive data) */ |
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writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr); |
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while (timeout && readl(&xilspi->regs->spisr) |
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& SPISR_RX_EMPTY) { |
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timeout--; |
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udelay(1); |
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} |
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if (!timeout) { |
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printf("XILSPI error: %s: Xfer timeout\n", __func__); |
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return -1; |
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} |
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/* read Rx element and push into data in buffer */ |
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d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK; |
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if (rxp) |
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*rxp++ = d; |
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debug("rx:%x\n", d); |
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} |
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done: |
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if (flags & SPI_XFER_END) |
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spi_cs_deactivate(slave); |
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return 0; |
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} |
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@ -0,0 +1,135 @@ |
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/*
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* Xilinx SPI driver |
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* |
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* XPS/AXI bus interface |
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* |
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* based on bfin_spi.c, by way of altera_spi.c |
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* Copyright (c) 2005-2008 Analog Devices Inc. |
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw> |
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca> |
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net> |
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* |
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* Licensed under the GPL-2 or later. |
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* |
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* [0]: http://www.xilinx.com/support/documentation
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* |
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* [S]: [0]/ip_documentation/xps_spi.pdf |
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* [0]/ip_documentation/axi_spi_ds742.pdf |
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*/ |
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#ifndef _XILINX_SPI_ |
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#define _XILINX_SPI_ |
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#include <asm/types.h> |
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#include <asm/io.h> |
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/*
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* Xilinx SPI Register Definition |
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* |
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* [1]: [0]/ip_documentation/xps_spi.pdf |
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* page 8, Register Descriptions |
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* [2]: [0]/ip_documentation/axi_spi_ds742.pdf |
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* page 7, Register Overview Table |
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*/ |
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struct xilinx_spi_reg { |
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u32 __space0__[7]; |
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ |
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */ |
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u32 __space1__; |
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u32 ipier; /* IP Interrupt Enable Register (IPIER) */ |
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u32 __space2__[5]; |
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u32 srr; /* Softare Reset Register (SRR) */ |
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u32 __space3__[7]; |
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u32 spicr; /* SPI Control Register (SPICR) */ |
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u32 spisr; /* SPI Status Register (SPISR) */ |
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u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ |
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u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ |
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u32 spissr; /* SPI Slave Select Register (SPISSR) */ |
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u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ |
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ |
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}; |
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/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */ |
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#define DGIER_GIE (1 << 31) |
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/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */ |
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#define IPISR_DRR_NOT_EMPTY (1 << 8) |
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#define IPISR_SLAVE_SELECT (1 << 7) |
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#define IPISR_TXF_HALF_EMPTY (1 << 6) |
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#define IPISR_DRR_OVERRUN (1 << 5) |
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#define IPISR_DRR_FULL (1 << 4) |
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#define IPISR_DTR_UNDERRUN (1 << 3) |
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#define IPISR_DTR_EMPTY (1 << 2) |
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#define IPISR_SLAVE_MODF (1 << 1) |
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#define IPISR_MODF (1 << 0) |
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|
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/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */ |
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#define IPIER_DRR_NOT_EMPTY (1 << 8) |
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#define IPIER_SLAVE_SELECT (1 << 7) |
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#define IPIER_TXF_HALF_EMPTY (1 << 6) |
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#define IPIER_DRR_OVERRUN (1 << 5) |
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#define IPIER_DRR_FULL (1 << 4) |
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#define IPIER_DTR_UNDERRUN (1 << 3) |
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#define IPIER_DTR_EMPTY (1 << 2) |
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#define IPIER_SLAVE_MODF (1 << 1) |
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#define IPIER_MODF (1 << 0) |
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|
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|
/* Softare Reset Register (srr), [1] p9, [2] p8 */ |
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|
#define SRR_RESET_CODE 0x0000000A |
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|
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|
/* SPI Control Register (spicr), [1] p9, [2] p8 */ |
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|
#define SPICR_LSB_FIRST (1 << 9) |
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#define SPICR_MASTER_INHIBIT (1 << 8) |
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|
#define SPICR_MANUAL_SS (1 << 7) |
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|
#define SPICR_RXFIFO_RESEST (1 << 6) |
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#define SPICR_TXFIFO_RESEST (1 << 5) |
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#define SPICR_CPHA (1 << 4) |
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#define SPICR_CPOL (1 << 3) |
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#define SPICR_MASTER_MODE (1 << 2) |
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#define SPICR_SPE (1 << 1) |
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#define SPICR_LOOP (1 << 0) |
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/* SPI Status Register (spisr), [1] p11, [2] p10 */ |
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#define SPISR_SLAVE_MODE_SELECT (1 << 5) |
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#define SPISR_MODF (1 << 4) |
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#define SPISR_TX_FULL (1 << 3) |
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#define SPISR_TX_EMPTY (1 << 2) |
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#define SPISR_RX_FULL (1 << 1) |
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#define SPISR_RX_EMPTY (1 << 0) |
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/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ |
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#define SPIDTR_8BIT_MASK (0xff << 0) |
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#define SPIDTR_16BIT_MASK (0xffff << 0) |
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#define SPIDTR_32BIT_MASK (0xffffffff << 0) |
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/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ |
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#define SPIDRR_8BIT_MASK (0xff << 0) |
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#define SPIDRR_16BIT_MASK (0xffff << 0) |
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#define SPIDRR_32BIT_MASK (0xffffffff << 0) |
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/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ |
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#define SPISSR_MASK(cs) (1 << (cs)) |
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#define SPISSR_ACT(cs) ~SPISSR_MASK(cs) |
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#define SPISSR_OFF ~0UL |
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/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */ |
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#define SPITFOR_OCYVAL_POS 0 |
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#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS) |
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|
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/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */ |
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#define SPIRFOR_OCYVAL_POS 0 |
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#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS) |
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|
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struct xilinx_spi_slave { |
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struct spi_slave slave; |
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struct xilinx_spi_reg *regs; |
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unsigned int freq; |
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unsigned int mode; |
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}; |
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|
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static inline struct xilinx_spi_slave *to_xilinx_spi_slave( |
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|
struct spi_slave *slave) |
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|
{ |
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|
return container_of(slave, struct xilinx_spi_slave, slave); |
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|
} |
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|
|
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|
#endif /* _XILINX_SPI_ */ |
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Loading…
Reference in new issue