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@ -55,6 +55,7 @@ |
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#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) |
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#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) |
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#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE |
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#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE |
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) |
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) |
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#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) |
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#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) |
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#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) |
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#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) |
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#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) |
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) |
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) |
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