These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
49f9337956
commit
dab0f7626e
@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = qs850.o flash.o
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@ -1,600 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* MuLogic B.V. |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/ppc4xx.h> |
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#include <asm/u-boot.h> |
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#include <asm/processor.h> |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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#define FLASH_WORD_SIZE unsigned long |
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#define FLASH_ID_MASK 0xFFFFFFFF |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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/* stolen from esteem192e/flash.c */ |
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ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0, size_b1; |
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int i; |
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uint pbcr; |
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unsigned long base_b0, base_b1; |
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volatile FLASH_WORD_SIZE* flash_base; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here */ |
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/* Test for 8M Flash first */ |
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debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_8M_PRELIM); |
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flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_8M_PRELIM); |
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size_b0 = flash_get_size(flash_base, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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return 0; |
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} |
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if (size_b0 < 8*1024*1024) { |
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/* Not quite 8M, try 4M Flash base address */ |
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debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_4M_PRELIM); |
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flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_4M_PRELIM); |
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size_b0 = flash_get_size(flash_base, &flash_info[0]); |
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} |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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return 0; |
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} |
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/* Only one bank */ |
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if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { |
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/* Setup offsets */ |
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flash_get_offsets ((ulong)flash_base, &flash_info[0]); |
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); |
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size_b1 = 0 ; |
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flash_info[0].size = size_b0; |
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return(size_b0); |
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} |
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/* We have 2 banks */ |
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size_b1 = flash_get_size(flash_base, &flash_info[1]); |
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/* Re-do sizing to get full correct info */ |
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if (size_b1) { |
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mtdcr(EBC0_CFGADDR, PB0CR); |
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pbcr = mfdcr(EBC0_CFGDATA); |
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mtdcr(EBC0_CFGADDR, PB0CR); |
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base_b1 = -size_b1; |
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pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); |
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mtdcr(EBC0_CFGDATA, pbcr); |
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} |
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if (size_b0) { |
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mtdcr(EBC0_CFGADDR, PB1CR); |
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pbcr = mfdcr(EBC0_CFGDATA); |
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mtdcr(EBC0_CFGADDR, PB1CR); |
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base_b0 = base_b1 - size_b0; |
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); |
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mtdcr(EBC0_CFGDATA, pbcr); |
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} |
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size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); |
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flash_get_offsets (base_b0, &flash_info[0]); |
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/* monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); |
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if (size_b1) { |
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/* Re-do sizing to get full correct info */ |
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size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]); |
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flash_get_offsets (base_b1, &flash_info[1]); |
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/* monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CONFIG_SYS_MONITOR_LEN, |
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base_b1+size_b1-1, &flash_info[1]); |
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/* monitor protection OFF by default (one is enough) */ |
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(void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CONFIG_SYS_MONITOR_LEN, |
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base_b0+size_b0-1, &flash_info[0]); |
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} else { |
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flash_info[1].flash_id = FLASH_UNKNOWN; |
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flash_info[1].sector_count = -1; |
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} |
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flash_info[0].size = size_b0; |
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flash_info[1].size = size_b1; |
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return (size_b0 + size_b1); |
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} |
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/*-----------------------------------------------------------------------
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This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823. |
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t *info) |
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{ |
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int i; |
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long large_sect_size; |
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long small_sect_size; |
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/* set up sector start adress table */ |
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large_sect_size = info->size / (info->sector_count - 8 + 1); |
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small_sect_size = large_sect_size / 8; |
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if (info->flash_id & FLASH_BTYPE) { |
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/* set sector offsets for bottom boot block type */ |
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for (i = 0; i < 7; i++) { |
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info->start[i] = base; |
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base += small_sect_size; |
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} |
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for (; i < info->sector_count; i++) { |
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info->start[i] = base; |
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base += large_sect_size; |
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} |
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} |
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else |
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{ |
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/* set sector offsets for top boot block type */ |
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for (i = 0; i < (info->sector_count - 8); i++) { |
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info->start[i] = base; |
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base += large_sect_size; |
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} |
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for (; i < info->sector_count; i++) { |
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info->start[i] = base; |
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base += small_sect_size; |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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uchar *boottype; |
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uchar botboot[]=", bottom boot sect)\n"; |
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uchar topboot[]=", top boot sector)\n"; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: |
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printf ("AMD "); |
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break; |
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case FLASH_MAN_FUJ: |
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printf ("FUJITSU "); |
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break; |
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case FLASH_MAN_SST: |
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printf ("SST "); |
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break; |
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case FLASH_MAN_STM: |
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printf ("STM "); |
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break; |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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if (info->flash_id & 0x0001 ) { |
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boottype = botboot; |
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} else { |
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boottype = topboot; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AM160B: |
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printf ("AM29LV160B (16 Mbit%s",boottype); |
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break; |
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case FLASH_AM160T: |
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printf ("AM29LV160T (16 Mbit%s",boottype); |
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break; |
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case FLASH_AMDL163T: |
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printf ("AM29DL163T (16 Mbit%s",boottype); |
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break; |
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case FLASH_AMDL163B: |
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printf ("AM29DL163B (16 Mbit%s",boottype); |
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break; |
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case FLASH_AM320B: |
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printf ("AM29LV320B (32 Mbit%s",boottype); |
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break; |
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case FLASH_AM320T: |
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printf ("AM29LV320T (32 Mbit%s",boottype); |
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break; |
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case FLASH_AMDL323T: |
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printf ("AM29DL323T (32 Mbit%s",boottype); |
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break; |
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case FLASH_AMDL323B: |
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printf ("AM29DL323B (32 Mbit%s",boottype); |
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break; |
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case FLASH_AMDL322T: |
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printf ("AM29DL322T (32 Mbit%s",boottype); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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* The following code cannot be run from FLASH! |
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*/ |
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ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong base = (ulong)addr; |
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FLASH_WORD_SIZE value; |
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/* Write auto select command: read Manufacturer ID */ |
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/*
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* Note: if it is an AMD flash and the word at addr[0000] |
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* is 0x00890089 this routine will think it is an Intel |
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* flash device and may(most likely) cause trouble. |
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*/ |
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addr[0x0000] = 0x00900090; |
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if(addr[0x0000] != 0x00890089){ |
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addr[0x0555] = 0x00AA00AA; |
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addr[0x02AA] = 0x00550055; |
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addr[0x0555] = 0x00900090; |
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} |
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value = addr[0]; |
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switch (value) { |
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case (AMD_MANUFACT & FLASH_ID_MASK): |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case (FUJ_MANUFACT & FLASH_ID_MASK): |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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case (STM_MANUFACT & FLASH_ID_MASK): |
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info->flash_id = FLASH_MAN_STM; |
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break; |
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case (SST_MANUFACT & FLASH_ID_MASK): |
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info->flash_id = FLASH_MAN_SST; |
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break; |
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case (INTEL_MANUFACT & FLASH_ID_MASK): |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (AMD_ID_LV160T & FLASH_ID_MASK): |
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info->flash_id += FLASH_AM160T; |
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info->sector_count = 35; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case (AMD_ID_LV160B & FLASH_ID_MASK): |
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info->flash_id += FLASH_AM160B; |
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info->sector_count = 35; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case (AMD_ID_DL163T & FLASH_ID_MASK): |
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info->flash_id += FLASH_AMDL163T; |
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info->sector_count = 39; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case (AMD_ID_DL163B & FLASH_ID_MASK): |
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info->flash_id += FLASH_AMDL163B; |
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info->sector_count = 39; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case (AMD_ID_DL323T & FLASH_ID_MASK): |
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info->flash_id += FLASH_AMDL323T; |
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info->sector_count = 71; |
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info->size = 0x00800000; |
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break; /* => 8 MB */ |
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case (AMD_ID_DL323B & FLASH_ID_MASK): |
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info->flash_id += FLASH_AMDL323B; |
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info->sector_count = 71; |
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info->size = 0x00800000; |
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break; /* => 8 MB */ |
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case (AMD_ID_DL322T & FLASH_ID_MASK): |
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info->flash_id += FLASH_AMDL322T; |
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info->sector_count = 71; |
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info->size = 0x00800000; |
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break; /* => 8 MB */ |
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default: |
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/* FIXME*/ |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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flash_get_offsets(base, info); |
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
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/* D0 = 1 if protected */ |
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addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); |
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info->protect[i] = addr[2] & 1; |
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} |
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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addr = (volatile FLASH_WORD_SIZE *)info->start[0]; |
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*addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ |
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} |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); |
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int flag, prot, sect, l_sect; |
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ulong start, now, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
|
||||||
printf ("- no sectors to erase\n"); |
|
||||||
} |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
if ((info->flash_id == FLASH_UNKNOWN) || |
|
||||||
(info->flash_id > FLASH_AMD_COMP) ) { |
|
||||||
printf ("Can't erase unknown flash type - aborted\n"); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
prot = 0; |
|
||||||
for (sect=s_first; sect<=s_last; ++sect) { |
|
||||||
if (info->protect[sect]) { |
|
||||||
prot++; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
if (prot) { |
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
|
||||||
prot); |
|
||||||
} else { |
|
||||||
printf ("\n"); |
|
||||||
} |
|
||||||
|
|
||||||
l_sect = -1; |
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts(); |
|
||||||
addr[0x0555] = 0x00AA00AA; |
|
||||||
addr[0x02AA] = 0x00550055; |
|
||||||
addr[0x0555] = 0x00800080; |
|
||||||
addr[0x0555] = 0x00AA00AA; |
|
||||||
addr[0x02AA] = 0x00550055; |
|
||||||
/* Start erase on unprotected sectors */ |
|
||||||
for (sect = s_first; sect<=s_last; sect++) { |
|
||||||
if (info->protect[sect] == 0) { /* not protected */ |
|
||||||
addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); |
|
||||||
addr[0] = (0x00300030 & FLASH_ID_MASK); |
|
||||||
l_sect = sect; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */ |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
/* wait at least 80us - let's wait 1 ms */ |
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
/*
|
|
||||||
* We wait for the last triggered sector |
|
||||||
*/ |
|
||||||
if (l_sect < 0) |
|
||||||
goto DONE; |
|
||||||
|
|
||||||
start = get_timer (0); |
|
||||||
last = start; |
|
||||||
addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); |
|
||||||
while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != |
|
||||||
(0x00800080&FLASH_ID_MASK) ) |
|
||||||
{ |
|
||||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
|
||||||
printf ("Timeout\n"); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
/* show that we're waiting */ |
|
||||||
if ((now - last) > 1000) { /* every second */ |
|
||||||
serial_putc ('.'); |
|
||||||
last = now; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
DONE: |
|
||||||
/* reset to read mode */ |
|
||||||
addr = (volatile FLASH_WORD_SIZE *)info->start[0]; |
|
||||||
addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ |
|
||||||
|
|
||||||
printf (" done\n"); |
|
||||||
return rcode; |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
*/ |
|
||||||
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
|
||||||
{ |
|
||||||
ulong cp, wp, data; |
|
||||||
int l; |
|
||||||
int i, rc; |
|
||||||
|
|
||||||
wp = (addr & ~3); /* get lower word aligned address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned start bytes |
|
||||||
*/ |
|
||||||
if ((l = addr - wp) != 0) { |
|
||||||
data = 0; |
|
||||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
for (; i<4 && cnt>0; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
++cp; |
|
||||||
} |
|
||||||
for (; cnt==0 && i<4; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
|
|
||||||
if ((rc = write_word(info, wp, data)) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += 4; |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle word aligned part |
|
||||||
*/ |
|
||||||
while (cnt >= 4) { |
|
||||||
data = 0; |
|
||||||
for (i=0; i<4; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
} |
|
||||||
if ((rc = write_word(info, wp, data)) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += 4; |
|
||||||
cnt -= 4; |
|
||||||
} |
|
||||||
|
|
||||||
if (cnt == 0) { |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes |
|
||||||
*/ |
|
||||||
data = 0; |
|
||||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
} |
|
||||||
for (; i<4; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
|
|
||||||
return (write_word(info, wp, data)); |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word to Flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
*/ |
|
||||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
|
||||||
{ |
|
||||||
vu_long *addr = (vu_long*)(info->start[0]); |
|
||||||
ulong start; |
|
||||||
int flag; |
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */ |
|
||||||
if ((*((vu_long *)dest) & data) != data) { |
|
||||||
return (2); |
|
||||||
} |
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts(); |
|
||||||
|
|
||||||
/* AMD stuff */ |
|
||||||
addr[0x0555] = 0x00AA00AA; |
|
||||||
addr[0x02AA] = 0x00550055; |
|
||||||
addr[0x0555] = 0x00A000A0; |
|
||||||
|
|
||||||
*((vu_long *)dest) = data; |
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */ |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
/* data polling for D7 */ |
|
||||||
start = get_timer(0); |
|
||||||
|
|
||||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { |
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
|
||||||
return (1); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
@ -1,214 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* MuLogic B.V. |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* Simple Network Magic Corporation, dnevil@snmc.com |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <asm/u-boot.h> |
|
||||||
#include <commproc.h> |
|
||||||
#include "mpc8xx.h" |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
static long int dram_size (long int, long int *, long int); |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
const uint sdram_table[] = |
|
||||||
{ |
|
||||||
/*
|
|
||||||
* Single Read. (Offset 0 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04, |
|
||||||
0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, |
|
||||||
/*
|
|
||||||
* Burst Read. (Offset 8 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00, |
|
||||||
0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05, |
|
||||||
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, |
|
||||||
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, |
|
||||||
/*
|
|
||||||
* Single Write. (Offset 18 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07, |
|
||||||
0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, |
|
||||||
/*
|
|
||||||
* Burst Write. (Offset 20 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00, |
|
||||||
0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04, |
|
||||||
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, |
|
||||||
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, |
|
||||||
/*
|
|
||||||
* Refresh (Offset 30 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04, |
|
||||||
0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04, |
|
||||||
0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04, |
|
||||||
/*
|
|
||||||
* Exception. (Offset 3c in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37 |
|
||||||
}; |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check Board Identity: |
|
||||||
* |
|
||||||
* Test ID string (QS850, QS823, ...) |
|
||||||
* |
|
||||||
* Always return 1 |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_QS850) |
|
||||||
#define BOARD_IDENTITY "QS850" |
|
||||||
#elif defined(CONFIG_QS823) |
|
||||||
#define BOARD_IDENTITY "QS823" |
|
||||||
#else |
|
||||||
#define BOARD_IDENTITY "QS???" |
|
||||||
#endif |
|
||||||
|
|
||||||
int checkboard (void) |
|
||||||
{ |
|
||||||
char *s, *e; |
|
||||||
char buf[64]; |
|
||||||
int i; |
|
||||||
|
|
||||||
i = getenv_f("serial#", buf, sizeof(buf)); |
|
||||||
s = (i>0) ? buf : NULL; |
|
||||||
|
|
||||||
if (!s || strncmp(s, BOARD_IDENTITY, 5)) { |
|
||||||
puts ("### No HW ID - assuming " BOARD_IDENTITY); |
|
||||||
} else { |
|
||||||
for (e=s; *e; ++e) { |
|
||||||
if (*e == ' ') |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
for ( ; s<e; ++s) { |
|
||||||
putc (*s); |
|
||||||
} |
|
||||||
} |
|
||||||
putc ('\n'); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
/* SDRAM Mode Register Definitions */ |
|
||||||
|
|
||||||
/* Set SDRAM Burst Length to 4 (010) */ |
|
||||||
/* See Motorola MPC850 User Manual, Page 13-14 */ |
|
||||||
#define SDRAM_BURST_LENGTH (2) |
|
||||||
|
|
||||||
/* Set Wrap Type to Sequential (0) */ |
|
||||||
/* See Motorola MPC850 User Manual, Page 13-14 */ |
|
||||||
#define SDRAM_WRAP_TYPE (0 << 3) |
|
||||||
|
|
||||||
/* Set /CAS Latentcy to 2 clocks */ |
|
||||||
#define SDRAM_CAS_LATENTCY (2 << 4) |
|
||||||
|
|
||||||
/* The Mode Register value must be shifted left by 2, since it is */ |
|
||||||
/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */ |
|
||||||
#define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2) |
|
||||||
|
|
||||||
#define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index) |
|
||||||
|
|
||||||
/* Please note a value of zero = 16 loops */ |
|
||||||
#define REFRESH_INIT_LOOPS (0) |
|
||||||
|
|
||||||
|
|
||||||
phys_size_t initdram (int board_type) |
|
||||||
{ |
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
long int size; |
|
||||||
|
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Prescaler for refresh |
|
||||||
*/ |
|
||||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Map controller bank 1 to the SDRAM address |
|
||||||
*/ |
|
||||||
memctl->memc_or1 = CONFIG_SYS_OR1; |
|
||||||
memctl->memc_br1 = CONFIG_SYS_BR1; |
|
||||||
udelay(1000); |
|
||||||
|
|
||||||
/* perform SDRAM initialization sequence */ |
|
||||||
memctl->memc_mamr = CONFIG_SYS_16M_MAMR; |
|
||||||
udelay(100); |
|
||||||
|
|
||||||
/* Program the SDRAM's Mode Register */ |
|
||||||
memctl->memc_mar = SDRAM_MODE_REG; |
|
||||||
|
|
||||||
/* Run the Prechard Pattern at 0x3C */ |
|
||||||
memctl->memc_mcr = UPMA_RUN(1,0x3c); |
|
||||||
udelay(1); |
|
||||||
|
|
||||||
/* Run the Refresh program residing at MAD index 0x30 */ |
|
||||||
/* This contains the CBR Refresh command with a loop */ |
|
||||||
/* The SDRAM must be refreshed at least 2 times */ |
|
||||||
/* Please note a value of zero = 16 loops */ |
|
||||||
memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); |
|
||||||
udelay(1); |
|
||||||
|
|
||||||
/* Run the Exception program residing at MAD index 0x3E */ |
|
||||||
/* This contains the Write Mode Register command */ |
|
||||||
/* The Write Mode Register command uses the value written to MAR */ |
|
||||||
memctl->memc_mcr = UPMA_RUN(1,0x3e); |
|
||||||
|
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check for 32M SDRAM Memory Size |
|
||||||
*/ |
|
||||||
size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE, |
|
||||||
(long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); |
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check for 16M SDRAM Memory Size |
|
||||||
*/ |
|
||||||
if (size != SDRAM_32M_MAX_SIZE) { |
|
||||||
size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE, |
|
||||||
(long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); |
|
||||||
udelay (1000); |
|
||||||
} |
|
||||||
|
|
||||||
udelay(10000); |
|
||||||
return (size); |
|
||||||
} |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check memory range for valid RAM. A simple memory test determines |
|
||||||
* the actually available RAM size between addresses `base' and |
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
|
||||||
* - short between address lines |
|
||||||
* - short between data lines |
|
||||||
*/ |
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize) |
|
||||||
{ |
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value; |
|
||||||
|
|
||||||
return (get_ram_size(base, maxsize)); |
|
||||||
} |
|
||||||
@ -1,85 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000-2010 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
|
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.text : |
|
||||||
{ |
|
||||||
/* WARNING - the following is hand-optimized to fit within */ |
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
|
||||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
|
||||||
|
|
||||||
*(.text*) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
|
||||||
} |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
KEEP(*(.got2)) |
|
||||||
KEEP(*(.got)) |
|
||||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
KEEP(*(.fixup)) |
|
||||||
} |
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data*) |
|
||||||
*(.sdata*) |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
. = .; |
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
. = .; |
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(256); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(256); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss (NOLOAD) : |
|
||||||
{ |
|
||||||
*(.bss*) |
|
||||||
*(.sbss*) |
|
||||||
*(COMMON) |
|
||||||
. = ALIGN(4); |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,8 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2000-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = qs860t.o flash.o
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,220 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* MuLogic B.V. |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* Simple Network Magic Corporation, dnevil@snmc.com |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <asm/u-boot.h> |
|
||||||
#include <commproc.h> |
|
||||||
#include "mpc8xx.h" |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
static long int dram_size (long int, long int *, long int); |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
const uint sdram_table[] = |
|
||||||
{ |
|
||||||
/*
|
|
||||||
* Single Read. (Offset 0 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
|
||||||
0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, |
|
||||||
/*
|
|
||||||
* Burst Read. (Offset 8 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
|
||||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, |
|
||||||
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
/*
|
|
||||||
* Single Write. (Offset 18 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, |
|
||||||
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
/*
|
|
||||||
* Burst Write. (Offset 20 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
|
||||||
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04, |
|
||||||
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
/*
|
|
||||||
* Refresh (Offset 30 in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
|
||||||
0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, |
|
||||||
/*
|
|
||||||
* Exception. (Offset 3c in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04 |
|
||||||
}; |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check Board Identity: |
|
||||||
* |
|
||||||
* Test ID string (QS860T...) |
|
||||||
* |
|
||||||
* Always return 1 |
|
||||||
*/ |
|
||||||
|
|
||||||
int checkboard (void) |
|
||||||
{ |
|
||||||
char *s, *e; |
|
||||||
char buf[64]; |
|
||||||
int i; |
|
||||||
|
|
||||||
i = getenv_f("serial#", buf, sizeof(buf)); |
|
||||||
s = (i>0) ? buf : NULL; |
|
||||||
|
|
||||||
if (!s || strncmp(s, "QS860T", 6)) { |
|
||||||
puts ("### No HW ID - assuming QS860T"); |
|
||||||
} else { |
|
||||||
for (e=s; *e; ++e) { |
|
||||||
if (*e == ' ') |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
for ( ; s<e; ++s) { |
|
||||||
putc (*s); |
|
||||||
} |
|
||||||
} |
|
||||||
putc ('\n'); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
phys_size_t initdram (int board_type) |
|
||||||
{ |
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
long int size; |
|
||||||
|
|
||||||
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Prescaler for refresh |
|
||||||
*/ |
|
||||||
memctl->memc_mptpr = 0x0400; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Map controller bank 2 to the SDRAM address |
|
||||||
*/ |
|
||||||
memctl->memc_or2 = CONFIG_SYS_OR2; |
|
||||||
memctl->memc_br2 = CONFIG_SYS_BR2; |
|
||||||
udelay(200); |
|
||||||
|
|
||||||
/* perform SDRAM initialization sequence */ |
|
||||||
memctl->memc_mbmr = CONFIG_SYS_16M_MBMR; |
|
||||||
udelay(100); |
|
||||||
|
|
||||||
memctl->memc_mar = 0x00000088; |
|
||||||
memctl->memc_mcr = 0x80804105; /* run precharge pattern */ |
|
||||||
udelay(1); |
|
||||||
|
|
||||||
/* Run two refresh cycles on SDRAM */ |
|
||||||
memctl->memc_mbmr = 0x18802118; |
|
||||||
memctl->memc_mcr = 0x80804130; |
|
||||||
memctl->memc_mbmr = 0x18802114; |
|
||||||
memctl->memc_mcr = 0x80804106; |
|
||||||
|
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
#if 0 |
|
||||||
/*
|
|
||||||
* Check for 64M SDRAM Memory Size |
|
||||||
*/ |
|
||||||
size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); |
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check for 16M SDRAM Memory Size |
|
||||||
*/ |
|
||||||
if (size != SDRAM_64M_MAX_SIZE) { |
|
||||||
#endif |
|
||||||
size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); |
|
||||||
udelay (1000); |
|
||||||
#if 0 |
|
||||||
} |
|
||||||
|
|
||||||
memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
udelay(10000); |
|
||||||
|
|
||||||
|
|
||||||
#if 0 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Also, map other memory to correct position |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Map the 8M Intel Flash device to chip select 1 |
|
||||||
*/ |
|
||||||
memctl->memc_or1 = CONFIG_SYS_OR1; |
|
||||||
memctl->memc_br1 = CONFIG_SYS_BR1; |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg |
|
||||||
* to chip select 3 |
|
||||||
*/ |
|
||||||
memctl->memc_or3 = CONFIG_SYS_OR3; |
|
||||||
memctl->memc_br3 = CONFIG_SYS_BR3; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Map chip selects 4, 5, 6, & 7 for external expansion connector |
|
||||||
*/ |
|
||||||
memctl->memc_or4 = CONFIG_SYS_OR4; |
|
||||||
memctl->memc_br4 = CONFIG_SYS_BR4; |
|
||||||
|
|
||||||
memctl->memc_or5 = CONFIG_SYS_OR5; |
|
||||||
memctl->memc_br5 = CONFIG_SYS_BR5; |
|
||||||
|
|
||||||
memctl->memc_or6 = CONFIG_SYS_OR6; |
|
||||||
memctl->memc_br6 = CONFIG_SYS_BR6; |
|
||||||
|
|
||||||
memctl->memc_or7 = CONFIG_SYS_OR7; |
|
||||||
memctl->memc_br7 = CONFIG_SYS_BR7; |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
return (size); |
|
||||||
} |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check memory range for valid RAM. A simple memory test determines |
|
||||||
* the actually available RAM size between addresses `base' and |
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
|
||||||
* - short between address lines |
|
||||||
* - short between data lines |
|
||||||
*/ |
|
||||||
|
|
||||||
static long int dram_size (long int mbmr_value, long int *base, long int maxsize) |
|
||||||
{ |
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
|
|
||||||
memctl->memc_mbmr = mbmr_value; |
|
||||||
|
|
||||||
return (get_ram_size(base, maxsize)); |
|
||||||
} |
|
||||||
@ -1,82 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000-2010 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
|
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.text : |
|
||||||
{ |
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
|
||||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
|
||||||
|
|
||||||
*(.text*) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
|
||||||
} |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
KEEP(*(.got2)) |
|
||||||
KEEP(*(.got)) |
|
||||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
KEEP(*(.fixup)) |
|
||||||
} |
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data*) |
|
||||||
*(.sdata*) |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
. = .; |
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
. = .; |
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(256); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(256); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss (NOLOAD) : |
|
||||||
{ |
|
||||||
*(.bss*) |
|
||||||
*(.sbss*) |
|
||||||
*(COMMON) |
|
||||||
. = ALIGN(4); |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,551 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* MuLogic B.V. |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* Simple Network Magic Corporation |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/* various debug settings */ |
|
||||||
#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ |
|
||||||
#undef CONFIG_SILENT_CONSOLE /* silent console */ |
|
||||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ |
|
||||||
#undef DEBUG_FLASH /* debug flash code */ |
|
||||||
#undef FLASH_DEBUG /* debug fash code */ |
|
||||||
#undef DEBUG_ENV /* debug environment code */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ |
|
||||||
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
|
||||||
#define CONFIG_QS823 1 /* ...on a QS823 module */ |
|
||||||
#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
|
||||||
|
|
||||||
/* Select the target clock speed */ |
|
||||||
#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ |
|
||||||
#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ |
|
||||||
#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ |
|
||||||
#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ |
|
||||||
#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_16MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 512 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_33MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 1024 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_50MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 1525 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_66MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 2048 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_80MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 2441 |
|
||||||
#endif |
|
||||||
|
|
||||||
/* choose flash size, 4Mb or 8Mb */ |
|
||||||
#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ |
|
||||||
#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ |
|
||||||
|
|
||||||
#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ |
|
||||||
|
|
||||||
#undef CONFIG_8xx_CONS_SMC1 |
|
||||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
|
||||||
#undef CONFIG_8xx_CONS_NONE |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ |
|
||||||
|
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ |
|
||||||
|
|
||||||
/* Define default IP addresses */ |
|
||||||
#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ |
|
||||||
#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ |
|
||||||
|
|
||||||
/* message to say directly after booting */ |
|
||||||
#define CONFIG_PREBOOT "echo '';" \ |
|
||||||
"echo 'type:';" \
|
|
||||||
"echo 'run boot_nfs to boot to NFS';" \
|
|
||||||
"echo 'run boot_flash to boot to flash';" \
|
|
||||||
"echo '';" \
|
|
||||||
"echo 'run flash_rootfs to install a new rootfs';" \
|
|
||||||
"echo 'run flash_env to clear the env sector';" \
|
|
||||||
"echo 'run flash_rw to clear the rw fs';" \
|
|
||||||
"echo 'run flash_uboot to install a new u-boot';" \
|
|
||||||
"echo 'run flash_kernel to install a new kernel';" |
|
||||||
|
|
||||||
/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ |
|
||||||
#define CONFIG_BOOTDELAY 5 |
|
||||||
#define CONFIG_BOOTCOMMAND "run boot_nfs" |
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ |
|
||||||
|
|
||||||
/* Our flash filesystem looks like this
|
|
||||||
* |
|
||||||
* 4Mb board: |
|
||||||
* ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) |
|
||||||
* ffec 0000 - ffed ffff read-write filesystem (ext2) |
|
||||||
* ffee 0000 - ffef ffff environment |
|
||||||
* fff0 0000 - fff1 ffff u-boot |
|
||||||
* fff2 0000 - ffff ffff linux kernel |
|
||||||
* |
|
||||||
* 8Mb board: |
|
||||||
* ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) |
|
||||||
* ffec 0000 - ffed ffff read-write filesystem (ext2) |
|
||||||
* ffee 0000 - ffef ffff environment |
|
||||||
* fff0 0000 - fff1 ffff u-boot |
|
||||||
* fff2 0000 - ffff ffff linux kernel |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
/* environment for 4Mb board */ |
|
||||||
#ifdef CONFIG_FLASH_4MB |
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"serial#=QS823\0" \
|
|
||||||
"hostname=qs823\0" \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"ethaddr=00:01:02:B4:36:56\0" \
|
|
||||||
"rootpath=/exports/rootfs\0" \
|
|
||||||
"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
|
|
||||||
/* fill in variables */ \
|
|
||||||
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
|
|
||||||
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
/* commands */ \
|
|
||||||
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
|
|
||||||
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
|
|
||||||
/* reinstall flash parts */ \
|
|
||||||
"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
|
|
||||||
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
|
|
||||||
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
|
|
||||||
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
|
|
||||||
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" |
|
||||||
#endif /* CONFIG_FLASH_4MB */ |
|
||||||
|
|
||||||
/* environment for 8Mb board */ |
|
||||||
#ifdef CONFIG_FLASH_8MB |
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"serial#=QS823\0" \
|
|
||||||
"hostname=qs823\0" \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"ethaddr=00:01:02:B4:36:56\0" \
|
|
||||||
"rootpath=/exports/rootfs\0" \
|
|
||||||
"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
|
|
||||||
/* fill in variables */ \
|
|
||||||
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
|
|
||||||
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
/* commands */ \
|
|
||||||
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
|
|
||||||
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
|
|
||||||
/* reinstall flash parts */ \
|
|
||||||
"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
|
|
||||||
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
|
|
||||||
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
|
|
||||||
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
|
|
||||||
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" |
|
||||||
#endif /* CONFIG_FLASH_8MB */ |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
#undef CONFIG_STATUS_LED /* Status LED disabled */ |
|
||||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
|
|
||||||
#undef CONFIG_MAC_PARTITION |
|
||||||
#undef CONFIG_DOS_PARTITION |
|
||||||
|
|
||||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#define CONFIG_CMD_BDI |
|
||||||
#define CONFIG_CMD_BOOTD |
|
||||||
#define CONFIG_CMD_CONSOLE |
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_SAVEENV |
|
||||||
#define CONFIG_CMD_FLASH |
|
||||||
#define CONFIG_CMD_IMI |
|
||||||
#define CONFIG_CMD_IMMAP |
|
||||||
#define CONFIG_CMD_MEMORY |
|
||||||
#define CONFIG_CMD_NET |
|
||||||
#define CONFIG_CMD_RUN |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Environment variable storage is in FLASH, one sector before U-boot |
|
||||||
*/ |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 /* 8kb */ |
|
||||||
#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_IMMR 0xFF000000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ |
|
||||||
|
|
||||||
#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ |
|
||||||
#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
|
||||||
#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TODO flash parameters |
|
||||||
* FLASH organization for Intel Strataflash |
|
||||||
*/ |
|
||||||
#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9 |
|
||||||
* SYPCR can only be written once after reset! |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef CONFIG_WATCHDOG |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/* MF (Multiplication Factor of SPLL) */ |
|
||||||
/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */ |
|
||||||
#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) |
|
||||||
#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) |
|
||||||
#define CONFIG_SYS_BRGCLK_PRESCALE 1 |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_66MHZ) |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) |
|
||||||
#define CONFIG_SYS_BRGCLK_PRESCALE 4 |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_80MHZ) |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) |
|
||||||
#define CONFIG_SYS_BRGCLK_PRESCALE 4 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define SCCR_MASK CONFIG_SYS_SCCR |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Debug Enable Register |
|
||||||
* 0x73E67C0F - All interrupts handled by BDM |
|
||||||
* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
#define CONFIG_SYS_DER 0x73E67C0F |
|
||||||
#define CONFIG_SYS_DER 0x0082400F |
|
||||||
|
|
||||||
#------------------------------------------------------------------------- |
|
||||||
# Program the Debug Enable Register (DER). This register provides the user |
|
||||||
# with the reason for entering into the debug mode. We want all conditions |
|
||||||
# to end up as an exception. We don't want to enter into debug mode for |
|
||||||
# any condition. See the back of of the Development Support section of the |
|
||||||
# MPC860 User Manual for a description of this register. |
|
||||||
#------------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_DER 0 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Memory Controller Initialization Constants |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR0 and OR0 (AMD dual FLASH devices) |
|
||||||
* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM |
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH |
|
||||||
|
|
||||||
/*
|
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) |
|
||||||
* flash that resides on the QS823. |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ |
|
||||||
/* represents a minumum 32K block size. */ |
|
||||||
#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) |
|
||||||
#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V) |
|
||||||
|
|
||||||
/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ |
|
||||||
/* which defines a 8 Mbyte memory block. */ |
|
||||||
#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) |
|
||||||
/* 0101 = Add a 5 clock cycle wait state */ |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) |
|
||||||
/* 0011 = Add a 3 clock cycle wait state */ |
|
||||||
/* 29.8ns clock * (3 + 2) = 149ns cycle time */ |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) |
|
||||||
/* 0010 = Add a 2 clock cycle wait state */ |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR1 and OR1 (SDRAM) |
|
||||||
* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define SDRAM_BASE 0x00000000 /* SDRAM bank */ |
|
||||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
|
||||||
|
|
||||||
/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
|
|
||||||
* represents a 128 Mbyte block the DRAM in |
|
||||||
* this address base. |
|
||||||
*/ |
|
||||||
#define vOR1_AM ((0xF800 << 16) + (0 << 15)) |
|
||||||
#define vBR1_BA ((0x0000 << 16) + (0 << 15)) |
|
||||||
#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) |
|
||||||
#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) |
|
||||||
|
|
||||||
/* Machine A Mode Register */ |
|
||||||
|
|
||||||
/* PTA Periodic Timer A */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_80MHZ) |
|
||||||
#define vMAMR_PTA (19 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_66MHZ) |
|
||||||
#define vMAMR_PTA (16 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_50MHZ) |
|
||||||
#define vMAMR_PTA (195 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_33MHZ) |
|
||||||
#define vMAMR_PTA (131 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) |
|
||||||
#define vMAMR_PTA (65 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
/* For boards with 16M of SDRAM */ |
|
||||||
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ |
|
||||||
#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ |
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
|
||||||
|
|
||||||
/* For boards with 32M of SDRAM */ |
|
||||||
#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ |
|
||||||
#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ |
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
|
||||||
|
|
||||||
|
|
||||||
/* Memory Periodic Timer Prescaler Register */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) |
|
||||||
/* Divide by 32 */ |
|
||||||
#define CONFIG_SYS_MPTPR 0x02 |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) |
|
||||||
/* Divide by 16 */ |
|
||||||
#define CONFIG_SYS_MPTPR 0x04 |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR2 and OR2 (Unused) |
|
||||||
* Base address = 0xF020_0000 - 0xF020_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR2_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR2_PRELIM 0xF0200000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR3 and OR3 (External Bus CS3) |
|
||||||
* Base address = 0xF030_0000 - 0xF030_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR3_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR3_PRELIM 0xF0300000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4 and OR4 (External Bus CS3) |
|
||||||
* Base address = 0xF040_0000 - 0xF040_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR4_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR4_PRELIM 0xF0400000 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4 and OR4 (External Bus CS3) |
|
||||||
* Base address = 0xF050_0000 - 0xF050_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR5_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR5_PRELIM 0xF0500000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR6 and OR6 (Unused) |
|
||||||
* Base address = 0xF060_0000 - 0xF060_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR6_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR6_PRELIM 0xF0600000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR7 and OR7 (Unused) |
|
||||||
* Base address = 0xF070_0000 - 0xF070_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR7_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR7_PRELIM 0xF0700000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Sanity checks |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) |
|
||||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
@ -1,551 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* MuLogic B.V. |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* Simple Network Magic Corporation |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/* various debug settings */ |
|
||||||
#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ |
|
||||||
#undef CONFIG_SILENT_CONSOLE /* silent console */ |
|
||||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ |
|
||||||
#undef DEBUG_FLASH /* debug flash code */ |
|
||||||
#undef FLASH_DEBUG /* debug fash code */ |
|
||||||
#undef DEBUG_ENV /* debug environment code */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ |
|
||||||
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
|
||||||
#define CONFIG_QS850 1 /* ...on a QS850 module */ |
|
||||||
#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
|
||||||
|
|
||||||
/* Select the target clock speed */ |
|
||||||
#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ |
|
||||||
#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ |
|
||||||
#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ |
|
||||||
#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ |
|
||||||
#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_16MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 512 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_33MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 1024 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_50MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 1525 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_66MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 2048 |
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_CLOCK_80MHZ |
|
||||||
#define CONFIG_CLOCK_MULT 2441 |
|
||||||
#endif |
|
||||||
|
|
||||||
/* choose flash size, 4Mb or 8Mb */ |
|
||||||
#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ |
|
||||||
#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ |
|
||||||
|
|
||||||
#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ |
|
||||||
|
|
||||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
|
||||||
#undef CONFIG_8xx_CONS_SMC2 |
|
||||||
#undef CONFIG_8xx_CONS_NONE |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ |
|
||||||
|
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ |
|
||||||
|
|
||||||
/* Define default IP addresses */ |
|
||||||
#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ |
|
||||||
#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ |
|
||||||
|
|
||||||
/* message to say directly after booting */ |
|
||||||
#define CONFIG_PREBOOT "echo '';" \ |
|
||||||
"echo 'type:';" \
|
|
||||||
"echo 'run boot_nfs to boot to NFS';" \
|
|
||||||
"echo 'run boot_flash to boot to flash';" \
|
|
||||||
"echo '';" \
|
|
||||||
"echo 'run flash_rootfs to install a new rootfs';" \
|
|
||||||
"echo 'run flash_env to clear the env sector';" \
|
|
||||||
"echo 'run flash_rw to clear the rw fs';" \
|
|
||||||
"echo 'run flash_uboot to install a new u-boot';" \
|
|
||||||
"echo 'run flash_kernel to install a new kernel';" |
|
||||||
|
|
||||||
/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ |
|
||||||
#define CONFIG_BOOTDELAY 5 |
|
||||||
#define CONFIG_BOOTCOMMAND "run boot_nfs" |
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ |
|
||||||
|
|
||||||
/* Our flash filesystem looks like this
|
|
||||||
* |
|
||||||
* 4Mb board: |
|
||||||
* ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) |
|
||||||
* ffec 0000 - ffed ffff read-write filesystem (ext2) |
|
||||||
* ffee 0000 - ffef ffff environment |
|
||||||
* fff0 0000 - fff1 ffff u-boot |
|
||||||
* fff2 0000 - ffff ffff linux kernel |
|
||||||
* |
|
||||||
* 8Mb board: |
|
||||||
* ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) |
|
||||||
* ffec 0000 - ffed ffff read-write filesystem (ext2) |
|
||||||
* ffee 0000 - ffef ffff environment |
|
||||||
* fff0 0000 - fff1 ffff u-boot |
|
||||||
* fff2 0000 - ffff ffff linux kernel |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
/* environment for 4Mb board */ |
|
||||||
#ifdef CONFIG_FLASH_4MB |
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"serial#=QS850\0" \
|
|
||||||
"hostname=qs850\0" \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"ethaddr=00:01:02:B4:36:56\0" \
|
|
||||||
"rootpath=/exports/rootfs\0" \
|
|
||||||
"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
|
|
||||||
/* fill in variables */ \
|
|
||||||
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
|
|
||||||
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
/* commands */ \
|
|
||||||
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
|
|
||||||
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
|
|
||||||
/* reinstall flash parts */ \
|
|
||||||
"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
|
|
||||||
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
|
|
||||||
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
|
|
||||||
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
|
|
||||||
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" |
|
||||||
#endif /* CONFIG_FLASH_4MB */ |
|
||||||
|
|
||||||
/* environment for 8Mb board */ |
|
||||||
#ifdef CONFIG_FLASH_8MB |
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"serial#=QS850\0" \
|
|
||||||
"hostname=qs850\0" \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"ethaddr=00:01:02:B4:36:56\0" \
|
|
||||||
"rootpath=/exports/rootfs\0" \
|
|
||||||
"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
|
|
||||||
/* fill in variables */ \
|
|
||||||
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
|
|
||||||
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
|
|
||||||
/* commands */ \
|
|
||||||
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
|
|
||||||
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
|
|
||||||
/* reinstall flash parts */ \
|
|
||||||
"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
|
|
||||||
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
|
|
||||||
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
|
|
||||||
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
|
|
||||||
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" |
|
||||||
#endif /* CONFIG_FLASH_8MB */ |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
#undef CONFIG_STATUS_LED /* Status LED disabled */ |
|
||||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
#undef CONFIG_MAC_PARTITION |
|
||||||
#undef CONFIG_DOS_PARTITION |
|
||||||
|
|
||||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_CMD_BDI |
|
||||||
#define CONFIG_CMD_BOOTD |
|
||||||
#define CONFIG_CMD_CONSOLE |
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_SAVEENV |
|
||||||
#define CONFIG_CMD_FLASH |
|
||||||
#define CONFIG_CMD_IMI |
|
||||||
#define CONFIG_CMD_IMMAP |
|
||||||
#define CONFIG_CMD_MEMORY |
|
||||||
#define CONFIG_CMD_NET |
|
||||||
#define CONFIG_CMD_RUN |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Environment variable storage is in FLASH, one sector before U-boot |
|
||||||
*/ |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 /* 8kb */ |
|
||||||
#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_IMMR 0xFF000000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ |
|
||||||
|
|
||||||
#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ |
|
||||||
#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
|
||||||
#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TODO flash parameters |
|
||||||
* FLASH organization for Intel Strataflash |
|
||||||
*/ |
|
||||||
#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9 |
|
||||||
* SYPCR can only be written once after reset! |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef CONFIG_WATCHDOG |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/* MF (Multiplication Factor of SPLL) */ |
|
||||||
/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ |
|
||||||
#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) |
|
||||||
#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) |
|
||||||
#define CONFIG_SYS_BRGCLK_PRESCALE 1 |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_66MHZ) |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) |
|
||||||
#define CONFIG_SYS_BRGCLK_PRESCALE 4 |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_80MHZ) |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) |
|
||||||
#define CONFIG_SYS_BRGCLK_PRESCALE 4 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define SCCR_MASK CONFIG_SYS_SCCR |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Debug Enable Register |
|
||||||
* 0x73E67C0F - All interrupts handled by BDM |
|
||||||
* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
#define CONFIG_SYS_DER 0x73E67C0F |
|
||||||
#define CONFIG_SYS_DER 0x0082400F |
|
||||||
|
|
||||||
#------------------------------------------------------------------------- |
|
||||||
# Program the Debug Enable Register (DER). This register provides the user |
|
||||||
# with the reason for entering into the debug mode. We want all conditions |
|
||||||
# to end up as an exception. We don't want to enter into debug mode for |
|
||||||
# any condition. See the back of of the Development Support section of the |
|
||||||
# MPC860 User Manual for a description of this register. |
|
||||||
#------------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_DER 0 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Memory Controller Initialization Constants |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR0 and OR0 (AMD dual FLASH devices) |
|
||||||
* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM |
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH |
|
||||||
|
|
||||||
/*
|
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) |
|
||||||
* flash that resides on the QS850. |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ |
|
||||||
/* represents a minumum 32K block size. */ |
|
||||||
#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) |
|
||||||
#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V) |
|
||||||
|
|
||||||
/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ |
|
||||||
/* which defines a 8 Mbyte memory block. */ |
|
||||||
#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) |
|
||||||
/* 0101 = Add a 5 clock cycle wait state */ |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) |
|
||||||
/* 0011 = Add a 3 clock cycle wait state */ |
|
||||||
/* 29.8ns clock * (3 + 2) = 149ns cycle time */ |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) |
|
||||||
/* 0010 = Add a 2 clock cycle wait state */ |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR1 and OR1 (SDRAM) |
|
||||||
* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define SDRAM_BASE 0x00000000 /* SDRAM bank */ |
|
||||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
|
||||||
|
|
||||||
/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
|
|
||||||
* represents a 128 Mbyte block the DRAM in |
|
||||||
* this address base. |
|
||||||
*/ |
|
||||||
#define vOR1_AM ((0xF800 << 16) + (0 << 15)) |
|
||||||
#define vBR1_BA ((0x0000 << 16) + (0 << 15)) |
|
||||||
#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) |
|
||||||
#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) |
|
||||||
|
|
||||||
/* Machine A Mode Register */ |
|
||||||
|
|
||||||
/* PTA Periodic Timer A */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_80MHZ) |
|
||||||
#define vMAMR_PTA (19 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_66MHZ) |
|
||||||
#define vMAMR_PTA (16 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_50MHZ) |
|
||||||
#define vMAMR_PTA (195 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_33MHZ) |
|
||||||
#define vMAMR_PTA (131 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) |
|
||||||
#define vMAMR_PTA (65 << 24) |
|
||||||
#endif |
|
||||||
|
|
||||||
/* For boards with 16M of SDRAM */ |
|
||||||
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ |
|
||||||
#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ |
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
|
||||||
|
|
||||||
/* For boards with 32M of SDRAM */ |
|
||||||
#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ |
|
||||||
#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ |
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
|
||||||
|
|
||||||
|
|
||||||
/* Memory Periodic Timer Prescaler Register */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) |
|
||||||
/* Divide by 32 */ |
|
||||||
#define CONFIG_SYS_MPTPR 0x02 |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) |
|
||||||
/* Divide by 16 */ |
|
||||||
#define CONFIG_SYS_MPTPR 0x04 |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR2 and OR2 (Unused) |
|
||||||
* Base address = 0xF020_0000 - 0xF020_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR2_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR2_PRELIM 0xF0200000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR3 and OR3 (External Bus CS3) |
|
||||||
* Base address = 0xF030_0000 - 0xF030_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR3_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR3_PRELIM 0xF0300000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4 and OR4 (External Bus CS3) |
|
||||||
* Base address = 0xF040_0000 - 0xF040_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR4_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR4_PRELIM 0xF0400000 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4 and OR4 (External Bus CS3) |
|
||||||
* Base address = 0xF050_0000 - 0xF050_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR5_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR5_PRELIM 0xF0500000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR6 and OR6 (Unused) |
|
||||||
* Base address = 0xF060_0000 - 0xF060_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR6_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR6_PRELIM 0xF0600000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR7 and OR7 (Unused) |
|
||||||
* Base address = 0xF070_0000 - 0xF070_0FFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_OR7_PRELIM 0xFFF00000 |
|
||||||
#define CONFIG_SYS_BR7_PRELIM 0xF0700000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Sanity checks |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) |
|
||||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
@ -1,390 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* MuLogic B.V. |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* Simple Network Magic Corporation |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/* various debug settings */ |
|
||||||
#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ |
|
||||||
#undef CONFIG_SILENT_CONSOLE /* silent console */ |
|
||||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ |
|
||||||
#undef DEBUG_FLASH /* debug flash code */ |
|
||||||
#undef FLASH_DEBUG /* debug fash code */ |
|
||||||
#undef DEBUG_ENV /* debug environment code */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ |
|
||||||
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
|
||||||
#define CONFIG_QS860T 1 /* ...on a QS860T module */ |
|
||||||
|
|
||||||
/* Start address of 512K Socketed Flash */ |
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
|
||||||
|
|
||||||
#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ |
|
||||||
#define CONFIG_MII |
|
||||||
#define FEC_INTERRUPT SIU_LEVEL1 |
|
||||||
#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ |
|
||||||
#define CONFIG_SYS_DISCOVER_PHY |
|
||||||
|
|
||||||
#undef CONFIG_8xx_CONS_SMC1 |
|
||||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ |
|
||||||
#undef CONFIG_8xx_CONS_NONE |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
|
||||||
|
|
||||||
/* Pass clocks to Linux 2.4.18 in Hz */ |
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ |
|
||||||
|
|
||||||
#define CONFIG_PREBOOT "echo;" \ |
|
||||||
"echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \
|
|
||||||
"echo" |
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS |
|
||||||
/* TODO compare against CADM860 */ |
|
||||||
#define CONFIG_BOOTCOMMAND "bootp; " \ |
|
||||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
|
||||||
"bootm" |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
|
|
||||||
#undef CONFIG_STATUS_LED /* Status LED disabled */ |
|
||||||
|
|
||||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_MAC_PARTITION |
|
||||||
#define CONFIG_DOS_PARTITION |
|
||||||
|
|
||||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_REGINFO |
|
||||||
#define CONFIG_CMD_IMMAP |
|
||||||
#define CONFIG_CMD_ASKENV |
|
||||||
#define CONFIG_CMD_NET |
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
|
|
||||||
|
|
||||||
/* TODO */ |
|
||||||
#if 0 |
|
||||||
/* Look at these */ |
|
||||||
CONFIG_IPADDR |
|
||||||
CONFIG_SERVERIP |
|
||||||
CONFIG_I2C |
|
||||||
CONFIG_SPI |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment variable storage is in NVRAM |
|
||||||
*/ |
|
||||||
#define CONFIG_ENV_IS_IN_NVRAM 1 |
|
||||||
#define CONFIG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ |
|
||||||
#define CONFIG_ENV_ADDR 0xD100E000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
/* TODO - size? */ |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_IMMR 0xF0000000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFFF00000 |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
|
|
||||||
/* TODO flash parameters */ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization for Intel Strataflash |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_16BIT 1 /* 16-bit wide flash memory */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
#undef CONFIG_ENV_IS_IN_FLASH |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9 |
|
||||||
* SYPCR can only be written once after reset! |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_WATCHDOG) |
|
||||||
#define CONFIG_SYS_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SYPCR 0xFFFFFF88 |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SIUMCR 0x00620000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TBSCR 0x00C3 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PISCR 0x0082 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PLPRCR 0x0090D000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define SCCR_MASK SCCR_EBDF11 |
|
||||||
#define CONFIG_SYS_SCCR 0x02000000 |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Debug Enable Register |
|
||||||
* 0x73E67C0F - All interrupts handled by BDM |
|
||||||
* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
#define CONFIG_SYS_DER 0x73E67C0F |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_DER 0x0082400F |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Memory Controller Initialization Constants |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR0 and OR0 (AMD 512K Socketed FLASH) |
|
||||||
* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM |
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH |
|
||||||
|
|
||||||
#define FLASH_BASE0_PRELIM 0xFFF00001 |
|
||||||
#define CONFIG_SYS_OR0_PRELIM 0xFFF80D42 |
|
||||||
#define CONFIG_SYS_BR0_PRELIM 0xFFF00401 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR1 and OR1 (Intel 8M StrataFLASH) |
|
||||||
* Base address = 0xD000_0000 - 0xD07F_FFFF |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_BASE1_PRELIM 0xD0000000 |
|
||||||
#define CONFIG_SYS_OR1_PRELIM 0xFF800D42 |
|
||||||
#define CONFIG_SYS_BR1_PRELIM 0xD0000801 |
|
||||||
/* #define CONFIG_SYS_OR1 0xFF800D42 */ |
|
||||||
/* #define CONFIG_SYS_BR1 0xD0000801 */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR2 and OR2 (SDRAM) |
|
||||||
* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) |
|
||||||
* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define SDRAM_BASE 0x00000000 /* SDRAM bank */ |
|
||||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
|
||||||
|
|
||||||
/* SDRAM timing */ |
|
||||||
#define SDRAM_TIMING 0x00000A00 |
|
||||||
|
|
||||||
/* For boards with 16M of SDRAM */ |
|
||||||
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ |
|
||||||
#define CONFIG_SYS_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ |
|
||||||
|
|
||||||
/* For boards with 64M of SDRAM */ |
|
||||||
#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ |
|
||||||
/* TODO - determine real value */ |
|
||||||
#define CONFIG_SYS_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) |
|
||||||
#define CONFIG_SYS_BR2 (SDRAM_BASE | 0x000000C1) |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR3 and OR3 (NVRAM, Sipex, NAND Flash) |
|
||||||
* Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) |
|
||||||
* Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) |
|
||||||
* Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) |
|
||||||
* Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM 0xFFC00DF6 |
|
||||||
#define CONFIG_SYS_BR3_PRELIM 0xD1000401 |
|
||||||
/* #define CONFIG_SYS_OR3 0xFFC00DF6 */ |
|
||||||
/* #define CONFIG_SYS_BR3 0xD1000401 */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4 and OR4 (Unused) |
|
||||||
* Base address = 0xE000_0000 - 0xE3FF_FFFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR4_PRELIM 0xFF000000 |
|
||||||
#define CONFIG_SYS_BR4_PRELIM 0xE0000000 |
|
||||||
/* #define CONFIG_SYS_OR4 0xFF000000 */ |
|
||||||
/* #define CONFIG_SYS_BR4 0xE0000000 */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR5 and OR5 (Expansion bus) |
|
||||||
* Base address = 0xE400_0000 - 0xE7FF_FFFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR5_PRELIM 0xFF000000 |
|
||||||
#define CONFIG_SYS_BR5_PRELIM 0xE4000000 |
|
||||||
/* #define CONFIG_SYS_OR5 0xFF000000 */ |
|
||||||
/* #define CONFIG_SYS_BR5 0xE4000000 */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR6 and OR6 (Expansion bus) |
|
||||||
* Base address = 0xE800_0000 - 0xEBFF_FFFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR6_PRELIM 0xFF000000 |
|
||||||
#define CONFIG_SYS_BR6_PRELIM 0xE8000000 |
|
||||||
/* #define CONFIG_SYS_OR6 0xFF000000 */ |
|
||||||
/* #define CONFIG_SYS_BR6 0xE8000000 */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR7 and OR7 (Expansion bus) |
|
||||||
* Base address = 0xEC00_0000 - 0xEFFF_FFFF |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR7_PRELIM 0xFF000000 |
|
||||||
#define CONFIG_SYS_BR7_PRELIM 0xE8000000 |
|
||||||
/* #define CONFIG_SYS_OR7 0xFF000000 */ |
|
||||||
/* #define CONFIG_SYS_BR7 0xE8000000 */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Sanity checks |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) |
|
||||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
Loading…
Reference in new issue