Add support for Motorola MPC8266ADS board
* Patch by Kyle Harris, 19 Feb 2003:
patches for the Intel lubbock board:
memsetup.S - general cleanup (based on Robert's csb226 code)
flash.c - overhaul, actually works now
lubbock.c - fix init funcs to return proper value
* Patch by Kenneth Johansson, 26 Feb 2003:
- Fixed off by one in RFTA calculation.
- No need to abort when LDF is lower than we can program it's only
minimum timing so clamp it to what we can do.
- Takes function pointer to function for reading the spd_nvram. Usefull
for faking data or hardcode a module without the nvram.
- fix other user for above change
- fix some comments.
* Patches by Brian Waite, 26 Feb 2003:
- fix port for evb64260 board
- fix PCI for evb64260 board
- fix PCI scan
* Patch by Reinhard Meyer, 1 Mar 2003:
Add support for EMK TOP860 Module
* Patch by Yuli Barcohen, 02 Mar 2003:
Add SPD EEPROM support for MPC8260ADS board
master
wdenk
22 years ago
parent
43d9616cff
commit
db2f721ffc
@ -0,0 +1,40 @@ |
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#
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# (C) Copyright 2000
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $^
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,490 @@ |
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/*
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* (C) Copyright 2003 |
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* EMK Elektronik GmbH <www.emk-elektronik.de> |
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* Reinhard Meyer <r.meyer@emk-elektronik.de> |
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* |
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* copied from the BMW Port - seems that its similiar enough |
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* to be easily adaped ;) --- Well, it turned out to become a |
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* merger between parts of the EMKstax Flash routines and the |
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* BMW funtion frames... |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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#define FLASH_WORD_SIZE unsigned short |
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#define FLASH_WORD_WIDTH (sizeof (FLASH_WORD_SIZE)) |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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/*****************************************************************************
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* software product ID entry/exit |
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*****************************************************************************/ |
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static void FlashProductIdMode ( |
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volatile FLASH_WORD_SIZE *b, |
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int on_off) |
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{ |
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b[0x5555] = 0xaa; |
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b[0x2aaa] = 0x55; |
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b[0x5555] = on_off ? 0x90 : 0xf0; |
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} |
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/*****************************************************************************
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* sector erase start |
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*****************************************************************************/ |
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static void FlashSectorErase ( |
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volatile FLASH_WORD_SIZE *b, |
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volatile FLASH_WORD_SIZE *a) |
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{ |
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b[0x5555] = 0xaa; |
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b[0x2aaa] = 0x55; |
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b[0x5555] = 0x80; |
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b[0x5555] = 0xaa; |
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b[0x2aaa] = 0x55; |
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a[0] = 0x30; |
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} |
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/*****************************************************************************
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* program a word |
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*****************************************************************************/ |
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static void FlashProgWord ( |
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volatile FLASH_WORD_SIZE *b, |
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volatile FLASH_WORD_SIZE *a, |
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FLASH_WORD_SIZE v) |
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{ |
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b[0x5555] = 0xaa; |
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b[0x2aaa] = 0x55; |
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b[0x5555] = 0xa0; |
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a[0] = v; |
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} |
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/*****************************************************************************
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* reset bank, back to read mode |
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*****************************************************************************/ |
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static void FlashReset (volatile FLASH_WORD_SIZE *b) |
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{ |
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b[0] = 0xf0; |
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} |
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/*****************************************************************************
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* identify FLASH chip |
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* this code is a stripped version of the FlashGetType() function in EMKstax |
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*****************************************************************************/ |
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unsigned long flash_init (void) |
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{ |
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volatile FLASH_WORD_SIZE * const flash = (volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE; |
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FLASH_WORD_SIZE manu, dev; |
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flash_info_t * const pflinfo = &flash_info[0]; |
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int j; |
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/* get Id Bytes */ |
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FlashProductIdMode (flash, 1); |
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manu = flash[0]; |
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dev = flash[1]; |
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FlashProductIdMode (flash, 0); |
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pflinfo->size = 0; |
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pflinfo->sector_count = 0; |
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pflinfo->flash_id = 0xffffffff; |
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pflinfo->portwidth = FLASH_CFI_16BIT; |
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pflinfo->chipwidth = FLASH_CFI_BY16; |
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switch (manu&0xff) |
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{ |
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case 0x01: /* AMD */ |
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pflinfo->flash_id = FLASH_MAN_AMD; |
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switch (dev&0xff) |
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{ |
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case 0x49: |
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pflinfo->size = 0x00200000; |
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pflinfo->sector_count = 35; |
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pflinfo->flash_id |= FLASH_AM160B; |
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pflinfo->start[0] = CFG_FLASH_BASE; |
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pflinfo->start[1] = CFG_FLASH_BASE + 0x4000; |
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pflinfo->start[2] = CFG_FLASH_BASE + 0x6000; |
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pflinfo->start[3] = CFG_FLASH_BASE + 0x8000; |
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for (j = 4; j < 35; j++) |
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{ |
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pflinfo->start[j] = CFG_FLASH_BASE + 0x00010000 * (j-3); |
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} |
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break; |
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case 0xf9: |
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pflinfo->size = 0x00400000; |
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pflinfo->sector_count = 71; |
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pflinfo->flash_id |= FLASH_AM320B; |
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pflinfo->start[0] = CFG_FLASH_BASE; |
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pflinfo->start[1] = CFG_FLASH_BASE + 0x4000; |
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pflinfo->start[2] = CFG_FLASH_BASE + 0x6000; |
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pflinfo->start[3] = CFG_FLASH_BASE + 0x8000; |
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for (j = 0; j < 8; j++) |
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{ |
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pflinfo->start[j] = CFG_FLASH_BASE + 0x00002000 * (j); |
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} |
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for (j = 8; j < 71; j++) |
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{ |
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pflinfo->start[j] = CFG_FLASH_BASE + 0x00010000 * (j-7); |
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} |
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break; |
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default: |
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printf ("unknown AMD dev=%x ", dev); |
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pflinfo->flash_id |= FLASH_UNKNOWN; |
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} |
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break; |
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default: |
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printf ("unknown manu=%x ", manu); |
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} |
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return pflinfo->size; |
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} |
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/*****************************************************************************
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* print info about a FLASH |
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*****************************************************************************/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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static const char unk[] = "Unknown"; |
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unsigned int i; |
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const char *mfct=unk, |
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*type=unk; |
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if(info->flash_id != FLASH_UNKNOWN) |
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{ |
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switch (info->flash_id & FLASH_VENDMASK) |
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{ |
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case FLASH_MAN_AMD: |
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mfct = "AMD"; |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) |
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{ |
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case FLASH_AM160B: |
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type = "AM29LV160B (16 Mbit, bottom boot sect)"; |
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break; |
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case FLASH_AM320B: |
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type = "AM29LV320B (32 Mbit, bottom boot sect)"; |
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break; |
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} |
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} |
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printf ( |
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"\n Brand: %s Type: %s\n" |
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" Size: %lu KB in %d Sectors\n", |
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mfct, |
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type, |
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info->size >> 10, |
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info->sector_count |
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); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; i++) |
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{ |
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unsigned long size; |
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unsigned int erased; |
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unsigned long *flash = (unsigned long *) info->start[i]; |
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/*
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* Check if whole sector is erased |
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*/ |
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size = |
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(i != (info->sector_count - 1)) ? |
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(info->start[i + 1] - info->start[i]) >> 2 : |
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(info->start[0] + info->size - info->start[i]) >> 2; |
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for ( |
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flash = (unsigned long *) info->start[i], erased = 1; |
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(flash != (unsigned long *) info->start[i] + size) && erased; |
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flash++ |
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) |
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erased = *flash == ~0x0UL; |
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printf ( |
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"%s %08lX %s %s", |
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(i % 5) ? "" : "\n ", |
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info->start[i], |
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erased ? "E" : " ", |
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info->protect[i] ? "RO" : " " |
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); |
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} |
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puts ("\n"); |
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return; |
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} |
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/*****************************************************************************
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* erase one or more sectors |
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*****************************************************************************/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); |
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int flag, |
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prot, |
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sect, |
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l_sect; |
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ulong start, |
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now, |
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last; |
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if ((s_first < 0) || (s_first > s_last)) |
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{ |
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if (info->flash_id == FLASH_UNKNOWN) |
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{ |
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printf ("- missing\n"); |
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} |
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else |
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{ |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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if ((info->flash_id == FLASH_UNKNOWN) || |
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(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) |
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{ |
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printf ("Can't erase unknown flash type - aborted\n"); |
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return 1; |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) |
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{ |
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if (info->protect[sect]) |
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{ |
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prot++; |
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} |
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} |
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if (prot) |
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{ |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} |
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else |
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{ |
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printf ("\n"); |
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} |
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l_sect = -1; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last; sect++) |
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{ |
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if (info->protect[sect] == 0) |
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{ /* not protected */ |
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FlashSectorErase ((FLASH_WORD_SIZE *)info->start[0], (FLASH_WORD_SIZE *)info->start[sect]); |
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l_sect = sect; |
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} |
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} |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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/*
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* We wait for the last triggered sector |
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*/ |
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if (l_sect < 0) |
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goto DONE; |
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start = get_timer (0); |
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last = start; |
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addr = (FLASH_WORD_SIZE *)info->start[l_sect]; |
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while ((addr[0] & 0x0080) != 0x0080) |
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{ |
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if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) |
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{ |
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printf ("Timeout\n"); |
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return 1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) |
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{ /* every second */ |
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serial_putc ('.'); |
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last = now; |
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} |
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} |
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DONE: |
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/* reset to read mode */ |
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FlashReset ((FLASH_WORD_SIZE *)info->start[0]); |
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printf (" done\n"); |
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return 0; |
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} |
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|
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/*****************************************************************************
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*****************************************************************************/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, |
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wp, |
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data; |
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int i, |
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l, |
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rc; |
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|
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wp = (addr & ~(FLASH_WORD_WIDTH-1)); /* get lower word aligned address */ |
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|
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/*
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* handle unaligned start bytes, if there are... |
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*/ |
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if ((l = addr - wp) != 0) |
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{ |
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data = 0; |
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|
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/* get the current before the new data into our data word */ |
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for (i=0, cp=wp; i<l; ++i, ++cp) |
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{ |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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|
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/* now merge the to be programmed values */ |
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for (; i<4 && cnt>0; ++i, ++cp, --cnt) |
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{ |
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data = (data << 8) | *src++; |
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} |
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|
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/* get the current after the new data into our data word */ |
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for (; cnt==0 && i<FLASH_WORD_WIDTH; ++i, ++cp) |
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{ |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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|
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/* now write the combined word */ |
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if ((rc = write_word (info, wp, data)) != 0) |
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{ |
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return (rc); |
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} |
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wp += FLASH_WORD_WIDTH; |
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} |
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|
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/*
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* handle word aligned part |
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*/ |
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while (cnt >= FLASH_WORD_WIDTH) |
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{ |
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data = 0; |
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for (i=0; i<FLASH_WORD_WIDTH; ++i) |
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{ |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_word (info, wp, data)) != 0) |
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{ |
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return (rc); |
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} |
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wp += FLASH_WORD_WIDTH; |
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cnt -= FLASH_WORD_WIDTH; |
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} |
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|
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if (cnt == 0) |
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{ |
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return (0); |
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} |
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|
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/*
|
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* handle unaligned tail bytes, if there are... |
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*/ |
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data = 0; |
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|
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/* now merge the to be programmed values */ |
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for (i=0, cp=wp; i<FLASH_WORD_WIDTH && cnt>0; ++i, ++cp) |
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{ |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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|
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/* get the current after the new data into our data word */ |
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for (; i<FLASH_WORD_WIDTH; ++i, ++cp) |
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{ |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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|
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/* now write the combined word */ |
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return (write_word (info, wp, data)); |
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} |
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|
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/*****************************************************************************
|
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* Write a word to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*****************************************************************************/ |
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static int write_word (flash_info_t *info, ulong dest, ulong data) |
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{ |
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; |
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volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; |
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FLASH_WORD_SIZE data2 = data; |
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ulong start; |
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int flag; |
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|
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/* Check if Flash is (sufficiently) erased */ |
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if ((*dest2 & data2) != data2) |
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{ |
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return (2); |
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} |
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|
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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|
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FlashProgWord (addr2, dest2, data2); |
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|
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts (); |
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|
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/* data polling for D7 */ |
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start = get_timer (0); |
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while ((*dest2 & 0x0080) != (data2 & 0x0080)) |
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{ |
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if (get_timer (start) > CFG_FLASH_WRITE_TOUT) |
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{ |
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return (1); |
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} |
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} |
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|
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return (0); |
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} |
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|
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/*-----------------------------------------------------------------------
|
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*/ |
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|
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@ -0,0 +1,187 @@ |
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/*
|
||||
* (C) Copyright 2003 |
||||
* EMK Elektronik GmbH <www.emk-elektronik.de> |
||||
* Reinhard Meyer <r.meyer@emk-elektronik.de> |
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* |
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* Board specific routines for the TOP860 |
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* |
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* - initialisation |
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* - interface to VPD data (mac address, clock speeds) |
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* - memory controller |
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* - serial io initialisation |
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* - ethernet io initialisation |
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* |
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* ----------------------------------------------------------------- |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <commproc.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
/*****************************************************************************
|
||||
* UPM table for 60ns EDO RAM at 25 MHz bus/external clock |
||||
*****************************************************************************/ |
||||
static const uint edo_60ns_25MHz_tbl[] = { |
||||
|
||||
/* single read (offset 0x00 in upm ram) */ |
||||
0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00, |
||||
0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05, |
||||
/* burst read (offset 0x08 in upm ram) */ |
||||
0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40, |
||||
0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48, |
||||
0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05, |
||||
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
||||
/* single write (offset 0x18 in upm ram) */ |
||||
0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07, |
||||
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
||||
/* burst write (offset 0x20 in upm ram) */ |
||||
0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c, |
||||
0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c, |
||||
0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05, |
||||
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
||||
/* refresh (offset 0x30 in upm ram) */ |
||||
0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04, |
||||
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
||||
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, |
||||
/* exception (offset 0x3C in upm ram) */ |
||||
0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05, |
||||
}; |
||||
|
||||
/*****************************************************************************
|
||||
* Print Board Identity |
||||
*****************************************************************************/ |
||||
int checkboard (void) |
||||
{ |
||||
puts ("Board:"CONFIG_IDENT_STRING"\n"); |
||||
return (0); |
||||
} |
||||
|
||||
/*****************************************************************************
|
||||
* Initialize DRAM controller |
||||
*****************************************************************************/ |
||||
long int initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
/*
|
||||
* Only initialize memory controller when running from FLASH. |
||||
* When running from RAM, don't touch it. |
||||
*/ |
||||
if ((ulong) initdram & 0xff000000) |
||||
{ |
||||
volatile uint *addr1, *addr2; |
||||
uint i, j; |
||||
|
||||
upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, |
||||
sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); |
||||
memctl->memc_mptpr = 0x0200; |
||||
memctl->memc_mamr = 0x0ca20330; |
||||
memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM; |
||||
memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V; |
||||
/*
|
||||
* Do 8 read accesses to DRAM |
||||
*/ |
||||
addr1 = (volatile uint*) 0; |
||||
addr2 = (volatile uint*) 0x00400000; |
||||
for (i=0, j=0; i<8; i++) |
||||
j = addr1[0]; |
||||
|
||||
/*
|
||||
* Now check whether we got 4MB or 16MB populated |
||||
*/ |
||||
addr1[0] = 0x12345678; |
||||
addr1[1] = 0x9abcdef0; |
||||
addr2[0] = 0xfeedc0de; |
||||
addr2[1] = 0x47110815; |
||||
if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) |
||||
{ |
||||
/* only 4MB populated */ |
||||
memctl->memc_or2 = -(CFG_DRAM_MAX/4) | OR_CSNT_SAM; |
||||
} |
||||
} |
||||
|
||||
return -(memctl->memc_or2 & 0xffff0000); |
||||
} |
||||
|
||||
/*****************************************************************************
|
||||
* otherinits after RAM is there and we are relocated to RAM |
||||
* note: though this is an int function, nobody cares for the result! |
||||
*****************************************************************************/ |
||||
int misc_init_r (void) |
||||
{ |
||||
/* read 'factory' part of EEPROM */ |
||||
uchar buf[81]; |
||||
uchar *p; |
||||
uint length; |
||||
uint addr; |
||||
uint len; |
||||
|
||||
/* get length first */ |
||||
addr = CFG_FACT_OFFSET; |
||||
if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) |
||||
{ |
||||
bailout: |
||||
printf ("cannot read factory configuration\n"); |
||||
printf ("be sure to set ethaddr yourself!\n"); |
||||
return 0; |
||||
} |
||||
length = buf[0] + (buf[1]<<8); |
||||
addr += 2; |
||||
|
||||
/* sanity check */ |
||||
if (length < 20 || length > CFG_FACT_SIZE-2) |
||||
goto bailout; |
||||
|
||||
/* read lines */ |
||||
while (length > 0) |
||||
{ |
||||
/* read one line */ |
||||
len = length > 80 ? 80 : length; |
||||
if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len)) |
||||
goto bailout; |
||||
/* mark end of buffer */ |
||||
buf[len] = 0; |
||||
/* search end of line */ |
||||
for (p=buf; *p && *p != 0x0a; p++) ; |
||||
if (!*p) |
||||
goto bailout; |
||||
*p++ = 0; |
||||
/* advance to next line start */ |
||||
length -= p-buf; |
||||
addr += p-buf; |
||||
/*printf ("%s\n", buf);*/ |
||||
/* search for our specific entry */ |
||||
if (!strncmp ((char *)buf, "[RLA/lan/Ethernet] ", 19)) |
||||
{ |
||||
setenv ("ethaddr", buf+19); |
||||
}
|
||||
else if (!strncmp ((char *)buf, "[BOARD/SERIAL] ", 15)) |
||||
{ |
||||
setenv ("serial#", buf+15); |
||||
}
|
||||
else if (!strncmp ((char *)buf, "[BOARD/TYPE] ", 13)) |
||||
{ |
||||
setenv ("board_id", buf+13); |
||||
}
|
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
||||
@ -0,0 +1,132 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
||||
@ -0,0 +1,46 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o flash.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $^
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,32 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# mpc8260ads board
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xfff00000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
|
||||
@ -0,0 +1,509 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com |
||||
* Add support the Sharp chips on the mpc8260ads. |
||||
* I started with board/ip860/flash.c and made changes I found in |
||||
* the MTD project by David Schleef. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) |
||||
# ifndef CFG_ENV_ADDR |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
||||
# endif |
||||
# ifndef CFG_ENV_SIZE |
||||
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
||||
# endif |
||||
# ifndef CFG_ENV_SECT_SIZE |
||||
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE |
||||
# endif |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data); |
||||
static int clear_block_lock_bit(vu_long * addr); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
#ifndef CONFIG_MPC8260ADS |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; |
||||
#endif |
||||
unsigned long size; |
||||
int i; |
||||
|
||||
/* Init: enable write,
|
||||
* or we cannot even write flash commands |
||||
*/ |
||||
#ifndef CONFIG_MPC8260ADS |
||||
bcsr->bd_ctrl |= BD_CTRL_FLWE; |
||||
#endif |
||||
|
||||
|
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
|
||||
/* set the default sector offset */ |
||||
} |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
|
||||
size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size, size<<20); |
||||
} |
||||
|
||||
#ifndef CONFIG_MPC8260ADS |
||||
/* Remap FLASH according to real size */ |
||||
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); |
||||
memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | |
||||
(memctl->memc_br1 & ~(BR_BA_MSK)); |
||||
#endif |
||||
/* Re-do sizing to get full correct info */ |
||||
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
||||
|
||||
flash_info[0].size = size; |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, |
||||
&flash_info[0]); |
||||
#endif |
||||
return (size); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_INTEL: printf ("Intel "); break; |
||||
case FLASH_MAN_SHARP: printf ("Sharp "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); |
||||
break; |
||||
case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); |
||||
break; |
||||
case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); |
||||
break; |
||||
case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); |
||||
break; |
||||
default: printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
||||
{ |
||||
short i; |
||||
ulong value; |
||||
ulong base = (ulong)addr; |
||||
ulong sector_offset; |
||||
|
||||
/* Write "Intelligent Identifier" command: read Manufacturer ID */ |
||||
*addr = 0x90909090; |
||||
|
||||
value = addr[0] & 0x00FF00FF; |
||||
switch (value) { |
||||
case MT_MANUFACT: /* SHARP, MT or => Intel */ |
||||
case INTEL_ALT_MANU: |
||||
info->flash_id = FLASH_MAN_INTEL; |
||||
break; |
||||
default: |
||||
printf("unknown manufacturer: %x\n", (unsigned int)value); |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
value = addr[1]; /* device ID */ |
||||
|
||||
switch (value) { |
||||
case (INTEL_ID_28F016S): |
||||
info->flash_id += FLASH_28F016SV; |
||||
info->sector_count = 32; |
||||
info->size = 0x00400000; |
||||
sector_offset = 0x20000; |
||||
break; /* => 2x2 MB */ |
||||
|
||||
case (INTEL_ID_28F160S3): |
||||
info->flash_id += FLASH_28F160S3; |
||||
info->sector_count = 32; |
||||
info->size = 0x00400000; |
||||
sector_offset = 0x20000; |
||||
break; /* => 2x2 MB */ |
||||
|
||||
case (INTEL_ID_28F320S3): |
||||
info->flash_id += FLASH_28F320S3; |
||||
info->sector_count = 64; |
||||
info->size = 0x00800000; |
||||
sector_offset = 0x20000; |
||||
break; /* => 2x4 MB */ |
||||
|
||||
case SHARP_ID_28F016SCL: |
||||
case SHARP_ID_28F016SCZ: |
||||
info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; |
||||
info->sector_count = 32; |
||||
info->size = 0x00800000; |
||||
sector_offset = 0x40000; |
||||
break; /* => 4x2 MB */ |
||||
|
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
/* set up sector start address table */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base; |
||||
base += sector_offset; |
||||
/* don't know how to check sector protection */ |
||||
info->protect[i] = 0; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
addr = (vu_long *)info->start[0]; |
||||
|
||||
*addr = 0xFFFFFF; /* reset bank to read array mode */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
int flag, prot, sect; |
||||
ulong start, now, last; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) |
||||
&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
/* Make Sure Block Lock Bit is not set. */ |
||||
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ |
||||
return 1; |
||||
} |
||||
|
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
vu_long *addr = (vu_long *)(info->start[sect]); |
||||
|
||||
last = start = get_timer (0); |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Reset Array */ |
||||
*addr = 0xffffffff; |
||||
/* Clear Status Register */ |
||||
*addr = 0x50505050; |
||||
/* Single Block Erase Command */ |
||||
*addr = 0x20202020; |
||||
/* Confirm */ |
||||
*addr = 0xD0D0D0D0; |
||||
|
||||
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { |
||||
/* Resume Command, as per errata update */ |
||||
*addr = 0xD0D0D0D0; |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
while ((*addr & 0x80808080) != 0x80808080) { |
||||
if(*addr & 0x20202020){ |
||||
printf("Error in Block Erase - Lock Bit may be set!\n"); |
||||
printf("Status Register = 0x%X\n", (uint)*addr); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
return 1; |
||||
} |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
/* reset to read mode */ |
||||
*addr = 0xFFFFFFFF; |
||||
} |
||||
} |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long *)dest; |
||||
ulong start, csr; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Write Command */ |
||||
*addr = 0x10101010; |
||||
|
||||
/* Write Data */ |
||||
*addr = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
flag = 0; |
||||
while (((csr = *addr) & 0x80808080) != 0x80808080) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
flag = 1; |
||||
break; |
||||
} |
||||
} |
||||
if (csr & 0x40404040) { |
||||
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); |
||||
flag = 1; |
||||
} |
||||
|
||||
/* Clear Status Registers Command */ |
||||
*addr = 0x50505050; |
||||
/* Reset to read array mode */ |
||||
*addr = 0xFFFFFFFF; |
||||
|
||||
return (flag); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clear Block Lock Bit, returns: |
||||
* 0 - OK |
||||
* 1 - Timeout |
||||
*/ |
||||
|
||||
static int clear_block_lock_bit(vu_long * addr) |
||||
{ |
||||
ulong start, now; |
||||
|
||||
/* Reset Array */ |
||||
*addr = 0xffffffff; |
||||
/* Clear Status Register */ |
||||
*addr = 0x50505050; |
||||
|
||||
*addr = 0x60606060; |
||||
*addr = 0xd0d0d0d0; |
||||
|
||||
start = get_timer (0); |
||||
while(*addr != 0x80808080){ |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout on clearing Block Lock Bit\n"); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,565 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Modified during 2001 by |
||||
* Advanced Communications Technologies (Australia) Pty. Ltd. |
||||
* Howard Walker, Tuong Vu-Dinh |
||||
* |
||||
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com |
||||
* Added support for the 16M dram simm on the 8260ads boards |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <i2c.h> |
||||
#include <mpc8260.h> |
||||
|
||||
/*
|
||||
* PBI Page Based Interleaving |
||||
* PSDMR_PBI page based interleaving |
||||
* 0 bank based interleaving |
||||
* External Address Multiplexing (EAMUX) adds a clock to address cycles |
||||
* (this can help with marginal board layouts) |
||||
* PSDMR_EAMUX adds a clock |
||||
* 0 no extra clock |
||||
* Buffer Command (BUFCMD) adds a clock to command cycles. |
||||
* PSDMR_BUFCMD adds a clock |
||||
* 0 no extra clock |
||||
*/ |
||||
#define CONFIG_PBI 0 |
||||
#define PESSIMISTIC_SDRAM 0 |
||||
#define EAMUX 0 /* EST requires EAMUX */ |
||||
#define BUFCMD 0 |
||||
|
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
||||
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
||||
/* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */ |
||||
/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ |
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ |
||||
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ |
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
|
||||
typedef struct bscr_ { |
||||
unsigned long bcsr0; |
||||
unsigned long bcsr1; |
||||
unsigned long bcsr2; |
||||
unsigned long bcsr3; |
||||
unsigned long bcsr4; |
||||
unsigned long bcsr5; |
||||
unsigned long bcsr6; |
||||
unsigned long bcsr7; |
||||
} bcsr_t; |
||||
|
||||
void reset_phy(void) |
||||
{ |
||||
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; |
||||
|
||||
/* reset the FEC port */ |
||||
bcsr->bcsr1 &= ~FETH_RST; |
||||
bcsr->bcsr1 |= FETH_RST; |
||||
} |
||||
|
||||
|
||||
int board_pre_init (void) |
||||
{ |
||||
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; |
||||
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts ("Board: Motorola MPC8266ADS\n"); |
||||
return 0; |
||||
} |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
/* Autoinit part stolen from board/sacsng/sacsng.c */ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8260_t *memctl = &immap->im_memctl; |
||||
volatile uchar c = 0xff; |
||||
volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); |
||||
uint psdmr = CFG_PSDMR; |
||||
int i; |
||||
|
||||
uint psrt = 14; /* for no SPD */ |
||||
uint chipselects = 1; /* for no SPD */ |
||||
uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ |
||||
uint or = CFG_OR2_PRELIM; /* for no SPD */ |
||||
uint data_width; |
||||
uint rows; |
||||
uint banks; |
||||
uint cols; |
||||
uint caslatency; |
||||
uint width; |
||||
uint rowst; |
||||
uint sdam; |
||||
uint bsma; |
||||
uint sda10; |
||||
u_char spd_size; |
||||
u_char data; |
||||
u_char cksum; |
||||
int j; |
||||
|
||||
/* Keep the compiler from complaining about potentially uninitialized vars */ |
||||
data_width = chipselects = rows = banks = cols = caslatency = psrt = 0; |
||||
|
||||
/*
|
||||
* Read the SDRAM SPD EEPROM via I2C. |
||||
*/ |
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
|
||||
i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); |
||||
spd_size = data; |
||||
cksum = data; |
||||
for(j = 1; j < 64; j++)
|
||||
{ /* read only the checksummed bytes */ |
||||
/* note: the I2C address autoincrements when alen == 0 */ |
||||
i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); |
||||
/*printf("addr %d = 0x%02x\n", j, data);*/ |
||||
if(j == 5) chipselects = data & 0x0F; |
||||
else if(j == 6) data_width = data; |
||||
else if(j == 7) data_width |= data << 8; |
||||
else if(j == 3) rows = data & 0x0F; |
||||
else if(j == 4) cols = data & 0x0F; |
||||
else if(j == 12)
|
||||
{ |
||||
/*
|
||||
* Refresh rate: this assumes the prescaler is set to |
||||
* approximately 1uSec per tick. |
||||
*/ |
||||
switch(data & 0x7F)
|
||||
{ |
||||
default: |
||||
case 0: psrt = 16; /* 15.625uS */ break; |
||||
case 1: psrt = 2; /* 3.9uS */ break; |
||||
case 2: psrt = 6; /* 7.8uS */ break; |
||||
case 3: psrt = 29; /* 31.3uS */ break; |
||||
case 4: psrt = 60; /* 62.5uS */ break; |
||||
case 5: psrt = 120; /* 125uS */ break; |
||||
} |
||||
} |
||||
else if(j == 17) banks = data; |
||||
else if(j == 18)
|
||||
{ |
||||
caslatency = 3; /* default CL */ |
||||
# if(PESSIMISTIC_SDRAM) |
||||
if((data & 0x04) != 0) caslatency = 3; |
||||
else if((data & 0x02) != 0) caslatency = 2; |
||||
else if((data & 0x01) != 0) caslatency = 1; |
||||
# else |
||||
if((data & 0x01) != 0) caslatency = 1; |
||||
else if((data & 0x02) != 0) caslatency = 2; |
||||
else if((data & 0x04) != 0) caslatency = 3; |
||||
# endif |
||||
else
|
||||
{ |
||||
printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", |
||||
data); |
||||
} |
||||
} |
||||
else if(j == 63)
|
||||
{ |
||||
if(data != cksum)
|
||||
{ |
||||
printf ("WARNING: Configuration data checksum failure:" |
||||
" is 0x%02x, calculated 0x%02x\n", |
||||
data, cksum); |
||||
} |
||||
} |
||||
cksum += data; |
||||
} |
||||
|
||||
/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ |
||||
if(caslatency < 2) { |
||||
printf("CL was %d, forcing to 2\n", caslatency); |
||||
caslatency = 2; |
||||
} |
||||
if(rows > 14) { |
||||
printf("This doesn't look good, rows = %d, should be <= 14\n", rows); |
||||
rows = 14; |
||||
} |
||||
if(cols > 11) { |
||||
printf("This doesn't look good, columns = %d, should be <= 11\n", cols); |
||||
cols = 11; |
||||
} |
||||
|
||||
if((data_width != 64) && (data_width != 72)) |
||||
{ |
||||
printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", |
||||
data_width); |
||||
} |
||||
width = 3; /* 2^3 = 8 bytes = 64 bits wide */ |
||||
/*
|
||||
* Convert banks into log2(banks) |
||||
*/ |
||||
if (banks == 2) banks = 1; |
||||
else if(banks == 4) banks = 2; |
||||
else if(banks == 8) banks = 3; |
||||
|
||||
|
||||
sdram_size = 1 << (rows + cols + banks + width); |
||||
|
||||
#if(CONFIG_PBI == 0) /* bank-based interleaving */ |
||||
rowst = ((32 - 6) - (rows + cols + width)) * 2; |
||||
#else |
||||
rowst = 32 - (rows + banks + cols + width); |
||||
#endif |
||||
|
||||
or = ~(sdram_size - 1) | /* SDAM address mask */ |
||||
((banks-1) << 13) | /* banks per device */ |
||||
(rowst << 9) | /* rowst */ |
||||
((rows - 9) << 6); /* numr */ |
||||
|
||||
|
||||
/*printf("memctl->memc_or2 = 0x%08x\n", or);*/ |
||||
|
||||
/*
|
||||
* SDAM specifies the number of columns that are multiplexed |
||||
* (reference AN2165/D), defined to be (columns - 6) for page |
||||
* interleave, (columns - 8) for bank interleave. |
||||
* |
||||
* BSMA is 14 - max(rows, cols). The bank select lines come |
||||
* into play above the highest "address" line going into the |
||||
* the SDRAM. |
||||
*/ |
||||
#if(CONFIG_PBI == 0) /* bank-based interleaving */ |
||||
sdam = cols - 8; |
||||
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); |
||||
sda10 = sdam + 2; |
||||
#else |
||||
sdam = cols - 6; |
||||
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); |
||||
sda10 = sdam; |
||||
#endif |
||||
#if(PESSIMISTIC_SDRAM) |
||||
psdmr = (CONFIG_PBI |\
|
||||
PSDMR_RFEN |\
|
||||
PSDMR_RFRC_16_CLK |\
|
||||
PSDMR_PRETOACT_8W |\
|
||||
PSDMR_ACTTORW_8W |\
|
||||
PSDMR_WRC_4C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD) |\
|
||||
caslatency |\
|
||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
|
||||
(sdam << 24) |\
|
||||
(bsma << 21) |\
|
||||
(sda10 << 18); |
||||
#else |
||||
psdmr = (CONFIG_PBI |\
|
||||
PSDMR_RFEN |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
|
||||
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
|
||||
PSDMR_WRC_1C | /* 1 clock + 7nSec */ |
||||
EAMUX |\
|
||||
BUFCMD) |\
|
||||
caslatency |\
|
||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
|
||||
(sdam << 24) |\
|
||||
(bsma << 21) |\
|
||||
(sda10 << 18); |
||||
#endif |
||||
/*printf("psdmr = 0x%08x\n", psdmr);*/ |
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): |
||||
* |
||||
* "At system reset, initialization software must set up the |
||||
* programmable parameters in the memory controller banks registers |
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured, |
||||
* system software should execute the following initialization sequence |
||||
* for each SDRAM device. |
||||
* |
||||
* 1. Issue a PRECHARGE-ALL-BANKS command |
||||
* 2. Issue eight CBR REFRESH commands |
||||
* 3. Issue a MODE-SET command to initialize the mode register |
||||
* |
||||
* Quote from Micron MT48LC8M16A2 data sheet: |
||||
* |
||||
* "...the SDRAM requires a 100uS delay prior to issuing any |
||||
* command other than a COMMAND INHIBIT or NOP. Starting at some |
||||
* point during this 100uS period and continuing at least through |
||||
* the end of this period, COMMAND INHIBIT or NOP commands should |
||||
* be applied." |
||||
* |
||||
* "Once the 100uS delay has been satisfied with at least one COMMAND |
||||
* INHIBIT or NOP command having been applied, a /PRECHARGE command/ |
||||
* should be applied. All banks must then be precharged, thereby |
||||
* placing the device in the all banks idle state." |
||||
* |
||||
* "Once in the idle state, /two/ AUTO REFRESH cycles must be |
||||
* performed. After the AUTO REFRESH cycles are complete, the |
||||
* SDRAM is ready for mode register programming." |
||||
* |
||||
* (/emphasis/ mine, gvb) |
||||
* |
||||
* The way I interpret this, Micron start up sequence is: |
||||
* 1. Issue a PRECHARGE-BANK command (initial precharge) |
||||
* 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") |
||||
* 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands |
||||
* 4. Issue a MODE-SET command to initialize the mode register |
||||
* |
||||
* -------- |
||||
* |
||||
* The initial commands are executed by setting P/LSDMR[OP] and |
||||
* accessing the SDRAM with a single-byte transaction." |
||||
* |
||||
* The appropriate BRx/ORx registers have already been set when we |
||||
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. |
||||
*/ |
||||
#if 1 |
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
memctl->memc_psrt = psrt; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; |
||||
for (i = 0; i < 8; i++) |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; |
||||
*ramaddr = c; |
||||
|
||||
/*
|
||||
* Do it a second time for the second set of chips if the DIMM has |
||||
* two chip selects (double sided). |
||||
*/ |
||||
if(chipselects > 1)
|
||||
{ |
||||
ramaddr += sdram_size; |
||||
|
||||
memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; |
||||
memctl->memc_or3 = or; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; |
||||
for (i = 0; i < 8; i++) |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; |
||||
*ramaddr = c; |
||||
} |
||||
#endif |
||||
/*
|
||||
printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR); |
||||
printf("memctl->memc_psrt = 0x%08x\n", psrt); |
||||
|
||||
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA); |
||||
printf("ramaddr = 0x%08x\n", ramaddr); |
||||
|
||||
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR); |
||||
|
||||
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW); |
||||
|
||||
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN); |
||||
|
||||
immap->im_siu_conf.sc_ppc_acr = 0x00000002; |
||||
immap->im_siu_conf.sc_ppc_alrh = 0x01267893; |
||||
immap->im_siu_conf.sc_tescr1 = 0x00004000; |
||||
*/ |
||||
#if 0 |
||||
/* init sdram dimm */ |
||||
ramaddr = (uchar *)CFG_SDRAM_BASE; |
||||
memctl->memc_psrt = 0x00000010; |
||||
immap->im_memctl.memc_or2 = 0xFF000CA0; |
||||
immap->im_memctl.memc_br2 = 0x00000041; |
||||
memctl->memc_psdmr = 0x296EB452; |
||||
*ramaddr = c; |
||||
memctl->memc_psdmr = 0x096EB452; |
||||
for (i = 0; i < 8; i++) |
||||
*ramaddr = c; |
||||
|
||||
memctl->memc_psdmr = 0x196EB452; |
||||
*ramaddr = c; |
||||
memctl->memc_psdmr = 0x416EB452; |
||||
*ramaddr = c; |
||||
#endif |
||||
/* print info */ |
||||
printf("SDRAM configuration read from SPD\n"); |
||||
printf("\tSize per side = %dMB\n", sdram_size >> 20); |
||||
printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width); |
||||
printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency); |
||||
printf("\tTotal size: "); |
||||
|
||||
return (sdram_size * chipselects); |
||||
/*return (16 * 1024 * 1024);*/ |
||||
} |
||||
@ -0,0 +1,117 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8260/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
||||
@ -0,0 +1,411 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stuart Hughes <stuarth@lineo.com> |
||||
* This file is based on similar values for other boards found in other |
||||
* U-Boot config files, and some that I found in the mpc8260ads manual. |
||||
* |
||||
* Note: my board is a PILOT rev. |
||||
* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
/* allow serial and ethaddr to be overwritten */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else */ |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - Select bus for bd/buffers (see 28-13) |
||||
* - Half duplex |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR 0 |
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
/* other options */ |
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 |
||||
|
||||
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FDC | \
|
||||
CFG_CMD_FDOS | \
|
||||
CFG_CMD_HWFLOW | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PCMCIA | \
|
||||
CFG_CMD_SCSI | \
|
||||
CFG_CMD_SPI | \
|
||||
CFG_CMD_VFD | \
|
||||
CFG_CMD_USB ) ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
/* for versions < 2.4.5-pre5 */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
#define CFG_FLASH_BASE 0xff800000 |
||||
#define FLASH_BASE 0xff800000 |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ |
||||
#define CFG_FLASH_SIZE 8 |
||||
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
|
||||
/* this is stuff came out of the Motorola docs */ |
||||
/* Only change this if you also change the Hardware configuration Word */ |
||||
#define CFG_DEFAULT_IMMR 0x0F010000 |
||||
|
||||
/*
|
||||
#define CFG_IMMR 0x04700000 |
||||
#define CFG_BCSR 0x04500000 |
||||
*/ |
||||
|
||||
/* Set IMMR to 0xF0000000 or above to boot Linux */ |
||||
#define CFG_IMMR 0xF0000000 |
||||
#define CFG_BCSR 0x04500000 |
||||
|
||||
/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
|
||||
*/ |
||||
/*#define CONFIG_VERY_BIG_RAM 1*/ |
||||
|
||||
/* What should be the base address of SDRAM DIMM and how big is
|
||||
* it (in Mbytes)? This will normally auto-configure via the SPD. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 16 |
||||
|
||||
#define SDRAM_SPD_ADDR 0x50 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BR2,BR3 - Base Register |
||||
* Ref: Section 10.3.1 on page 10-14 |
||||
* OR2,OR3 - Option Register |
||||
* Ref: Section 10.3.2 on page 10-16 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
/* Bank 2,3 - SDRAM DIMM
|
||||
*/ |
||||
|
||||
/* The BR2 is configured as follows:
|
||||
* |
||||
* - Base address of 0x00000000 |
||||
* - 64 bit port size (60x bus only) |
||||
* - Data errors checking is disabled |
||||
* - Read and write access |
||||
* - SDRAM 60x bus |
||||
* - Access are handled by the memory controller according to MSEL |
||||
* - Not used for atomic operations |
||||
* - No data pipelining is done |
||||
* - Valid |
||||
*/ |
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_BR3_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
/* With a 64 MB DIMM, the OR2 is configured as follows:
|
||||
* |
||||
* - 64 MB |
||||
* - 4 internal banks per device |
||||
* - Row start address bit is A8 with PSDMR[PBI] = 0 |
||||
* - 12 row address lines |
||||
* - Back-to-back page mode |
||||
* - Internal bank interleaving within save device enabled |
||||
*/ |
||||
#if (CFG_SDRAM_SIZE == 64) |
||||
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A8 |\
|
||||
ORxS_NUMR_12) |
||||
#elif (CFG_SDRAM_SIZE == 16) |
||||
#define CFG_OR2_PRELIM (0xFF000CA0) |
||||
#else |
||||
#error "INVALID SDRAM CONFIGURATION" |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PSDMR - 60x Bus SDRAM Mode Register |
||||
* Ref: Section 10.3.3 on page 10-21 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#if (CFG_SDRAM_SIZE == 64) |
||||
/* With a 64 MB DIMM, the PSDMR is configured as follows:
|
||||
* |
||||
* - Bank Based Interleaving, |
||||
* - Refresh Enable, |
||||
* - Address Multiplexing where A5 is output on A14 pin |
||||
* (A6 on A15, and so on), |
||||
* - use address pins A14-A16 as bank select, |
||||
* - A9 is output on SDA10 during an ACTIVATE command, |
||||
* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, |
||||
* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command |
||||
* is 3 clocks, |
||||
* - earliest timing for READ/WRITE command after ACTIVATE command is |
||||
* 2 clocks, |
||||
* - earliest timing for PRECHARGE after last data was read is 1 clock, |
||||
* - earliest timing for PRECHARGE after last data was written is 1 clock, |
||||
* - CAS Latency is 2. |
||||
*/ |
||||
#define CFG_PSDMR (PSDMR_RFEN |\ |
||||
PSDMR_SDAM_A14_IS_A5 |\
|
||||
PSDMR_BSMA_A14_A16 |\
|
||||
PSDMR_SDA10_PBI0_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_3W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
#elif (CFG_SDRAM_SIZE == 16) |
||||
/* With a 16 MB DIMM, the PSDMR is configured as follows:
|
||||
* |
||||
* configuration parameters found in Motorola documentation |
||||
*/ |
||||
#define CFG_PSDMR (0x016EB452) |
||||
#else |
||||
#error "INVALID SDRAM CONFIGURATION" |
||||
#endif |
||||
|
||||
|
||||
#define RS232EN_1 0x02000002 |
||||
#define RS232EN_2 0x01000001 |
||||
#define FETHIEN 0x08000008 |
||||
#define FETH_RST 0x04000004 |
||||
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
|
||||
/* 0x0EA28205 */ |
||||
/*#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
|
||||
( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
|
||||
( HRCW_BMS | HRCW_APPC10 ) |\
|
||||
( HRCW_MODCK_H0101 ) \
|
||||
) |
||||
*/ |
||||
|
||||
/* This value should actually be situated in the first 256 bytes of the FLASH
|
||||
which on the standard MPC8266ADS board is at address 0xFF800000 |
||||
The linker script places it at 0xFFF00000 instead. |
||||
|
||||
It still works, however, as long as the ADS board jumper JP3 is set to
|
||||
position 2-3 so the board is using the BCSR as Hardware Configuration Word
|
||||
|
||||
If you want to use the one defined here instead, ust copy the first 256 bytes from
|
||||
0xfff00000 to 0xff800000 (for 8MB flash)
|
||||
|
||||
- Rune |
||||
|
||||
*/ |
||||
#define CFG_HRCW_MASTER 0x0cb23645 |
||||
|
||||
/* no slaves */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
# define CFG_ENV_IS_IN_FLASH 1 |
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
# define CFG_ENV_SECT_SIZE 0x40000 |
||||
#else |
||||
# define CFG_ENV_IS_IN_NVRAM 1 |
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
# define CFG_ENV_SIZE 0x200 |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
|
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) |
||||
|
||||
#define CFG_HID2 0 |
||||
|
||||
#define CFG_SYPCR 0xFFFFFFC3 |
||||
#define CFG_BCR 0x100C0000 |
||||
#define CFG_SIUMCR 0x0A200000 |
||||
#define CFG_SCCR 0x00000000 |
||||
#define CFG_BR0_PRELIM 0xFF801801 |
||||
#define CFG_OR0_PRELIM 0xFF800836 |
||||
#define CFG_BR1_PRELIM 0x04501801 |
||||
#define CFG_OR1_PRELIM 0xFFFF8010 |
||||
|
||||
#define CFG_RMR 0 |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
#define CFG_RCCR 0 |
||||
/*#define CFG_PSDMR 0x016EB452*/ |
||||
#define CFG_MPTPR 0x00001900 |
||||
#define CFG_PSRT 0x00000021 |
||||
|
||||
#define CFG_RESET_ADDRESS 0x04400000 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,439 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* EMK Elektronik GmbH <www.emk-elektronik.de> |
||||
* Reinhard Meyer <r.meyer@emk-elektronik.de> |
||||
* |
||||
* Configuation settings for the TOP860 board. |
||||
* |
||||
* ----------------------------------------------------------------- |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
/*
|
||||
* TOP860 is a simple module: |
||||
* 16-bit wide FLASH on CS0 (2MB or more) |
||||
* 32-bit wide DRAM on CS2 (either 4MB or 16MB) |
||||
* FEC with Am79C874 100-Base-T and Fiber Optic |
||||
* Ports available, but we choose SMC1 for Console |
||||
* 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set |
||||
* 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock |
||||
* |
||||
* This config has been copied from MBX.h / MBX860T.h |
||||
*/ |
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CPU and BOARD type |
||||
*/ |
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
||||
#define CONFIG_MPC860T 1 /* even better... an FEC! */ |
||||
#define CONFIG_TOP860 1 /* ...on a TOP860 module */ |
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_IDENT_STRING " EMK TOP860" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CLOCK settings |
||||
*/ |
||||
#define CONFIG_SYSCLK 49152000 |
||||
#define CFG_XTAL 32768 |
||||
#define CONFIG_EBDF 1 |
||||
#define CONFIG_COM 3 |
||||
#define CONFIG_RTC_MPC8xx |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical memory map as defined by EMK |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ |
||||
#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */ |
||||
#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */ |
||||
#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */ |
||||
#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* derived values |
||||
*/ |
||||
#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL) |
||||
#define CFG_CPUCLOCK CONFIG_SYSCLK |
||||
#define CFG_BRGCLOCK CONFIG_SYSCLK |
||||
#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF) |
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_CFI |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Command interpreter |
||||
*/ |
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
/*
|
||||
* Allow partial commands to be matched to uniqueness. |
||||
*/ |
||||
#define CFG_MATCH_PARTIAL_CMD |
||||
|
||||
/*
|
||||
* List of available monitor commands. Use the system default list |
||||
* plus add some of the "non-standard" commands back in. |
||||
* See ./cmd_confdefs.h |
||||
*/ |
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_IMMAP | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_BEDBUG \
|
||||
) |
||||
|
||||
#define CONFIG_AUTOSCRIPT 1 |
||||
#define CFG_LOADS_BAUD_CHANGE 1 |
||||
#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ |
||||
|
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory Test Command |
||||
*/ |
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment handler |
||||
* only the first 6k in EEPROM are available for user. Of that we use 256b |
||||
*/ |
||||
#define CONFIG_SOFT_I2C |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ |
||||
#define CFG_ENV_OFFSET 0x1000 |
||||
#define CFG_ENV_SIZE 0x0700 |
||||
#define CFG_I2C_EEPROM_ADDR 0x57 |
||||
#define CFG_FACT_OFFSET 0x1800 |
||||
#define CFG_FACT_SIZE 0x0800 |
||||
#define CFG_I2C_FACT_ADDR 0x57 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_SIZE 0x2000 |
||||
#define CFG_I2C_SPEED 100000 |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#if defined (CONFIG_SOFT_I2C) |
||||
#define SDA 0x00010 |
||||
#define SCL 0x00020 |
||||
#define DIR immr->im_cpm.cp_pbdir |
||||
#define DAT immr->im_cpm.cp_pbdat |
||||
#define PAR immr->im_cpm.cp_pbpar |
||||
#define ODR immr->im_cpm.cp_pbodr |
||||
#define I2C_INIT {PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);} |
||||
#define I2C_READ ((DAT&SDA)?1:0) |
||||
#define I2C_SDA(x) {if(x)DAT|=SDA;else DAT&=~SDA;} |
||||
#define I2C_SCL(x) {if(x)DAT|=SCL;else DAT&=~SCL;} |
||||
#define I2C_DELAY {udelay(5);} |
||||
#define I2C_ACTIVE {DIR|=SDA;} |
||||
#define I2C_TRISTATE {DIR&=~SDA;} |
||||
#endif |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* defines we need to get FEC running |
||||
*/ |
||||
#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ |
||||
#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ |
||||
#define FEC_ENET 1 /* eth.c needs it that way... */ |
||||
#define CFG_DISCOVER_PHY 1 |
||||
#define CONFIG_MII 1 |
||||
#define CONFIG_PHY_ADDR 31 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* adresses |
||||
*/ |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x80000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ |
||||
#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) |
||||
#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Debug Enable Register |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 /* used in start.S */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* set up PLPRCR (PLL, Low-Power, and Reset Control Register) |
||||
* 12 MF calculated Multiplication factor |
||||
* 4 0 0000 |
||||
* 1 SPLSS 0 System PLL lock status sticky |
||||
* 1 TEXPS 1 Timer expired status |
||||
* 1 0 0 |
||||
* 1 TMIST 0 Timers interrupt status |
||||
* 1 0 0 |
||||
* 1 CSRC 0 Clock source (0=DFNH, 1=DFNL) |
||||
* 2 LPM 00 Low-power modes |
||||
* 1 CSR 0 Checkstop reset enable |
||||
* 1 LOLRE 0 Loss-of-lock reset enable |
||||
* 1 FIOPD 0 Force I/O pull down |
||||
* 5 0 00000
|
||||
*/ |
||||
#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* set up SYPCR: |
||||
* 16 SWTC 0xffff Software watchdog timer count |
||||
* 8 BMT 0xff Bus monitor timing |
||||
* 1 BME 1 Bus monitor enable |
||||
* 3 0 000 |
||||
* 1 SWF 1 Software watchdog freeze |
||||
* 1 SWE 0/1 Software watchdog enable |
||||
* 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET) |
||||
* 1 SWP 0/1 Software watchdog prescale (1=/2048) |
||||
*/ |
||||
#if defined (CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* set up SIUMCR |
||||
* 1 EARB 0 External arbitration |
||||
* 3 EARP 000 External arbitration request priority |
||||
* 4 0 0000 |
||||
* 1 DSHW 0 Data show cycles |
||||
* 2 DBGC 00 Debug pin configuration |
||||
* 2 DBPC 00 Debug port pins configuration |
||||
* 1 0 0 |
||||
* 1 FRC 0 FRZ pin configuration |
||||
* 1 DLK 0 Debug register lock |
||||
* 1 OPAR 0 Odd parity |
||||
* 1 PNCS 0 Parity enable for non memory controller regions |
||||
* 1 DPC 0 Data parity pins configuration |
||||
* 1 MPRE 0 Multiprocessor reservation enable |
||||
* 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT) |
||||
* 1 AEME 0 Async external master enable |
||||
* 1 SEME 0 Sync external master enable |
||||
* 1 BSC 0 Byte strobe configuration |
||||
* 1 GB5E 0 GPL_B5 enable |
||||
* 1 B2DD 0 Bank 2 double drive
|
||||
* 1 B3DD 0 Bank 3 double drive
|
||||
* 4 0 0000 |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_MLRC11) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* set up SCCR (System Clock and Reset Control Register) |
||||
* 1 0 0 |
||||
* 2 COM 11 Clock output module (00=full, 01=half, 11=off) |
||||
* 3 0 000 |
||||
* 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2) |
||||
* 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512) |
||||
* 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK) |
||||
* 1 CRQEN 0 CPM request enable |
||||
* 1 PRQEN 0 Power management request enable |
||||
* 2 0 00 |
||||
* 2 EBDF xx External bus division factor |
||||
* 2 0 00 |
||||
* 2 DFSYNC 00 Division factor for SYNCLK |
||||
* 2 DFBRG 00 Division factor for BRGCLK |
||||
* 3 DFNL 000 Division factor low frequency |
||||
* 3 DFNH 000 Division factor high frequency |
||||
* 5 0 00000 |
||||
*/ |
||||
#define SCCR_MASK 0 |
||||
#if CONFIG_EBDF |
||||
#define CFG_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) |
||||
#else |
||||
#define CFG_SCCR (SCCR_COM11 | SCCR_TBS) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chip Select 0 - FLASH |
||||
*----------------------------------------------------------------------- |
||||
* Preliminary Values |
||||
*/ |
||||
/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) |
||||
#define CFG_OR0_PRELIM (-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* misc |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*
|
||||
* Set the autoboot delay in seconds. A delay of -1 disables autoboot |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
/*
|
||||
* Pass the clock frequency to the Linux kernel in units of MHz |
||||
*/ |
||||
#define CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
#define CONFIG_PREBOOT \ |
||||
"echo;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#undef CONFIG_BOOTP_MASK |
||||
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ |
||||
CONFIG_BOOTP_BOOTFILESIZE \
|
||||
) |
||||
|
||||
|
||||
/*
|
||||
* Set default IP stuff just to get bootstrap entries into the |
||||
* environment so that we can autoscript the full default environment. |
||||
*/ |
||||
#define CONFIG_ETHADDR 9a:52:63:15:85:25 |
||||
#define CONFIG_SERVERIP 10.0.4.200 |
||||
#define CONFIG_IPADDR 10.0.4.111 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Defaults for Autoscript |
||||
*/ |
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
#define CFG_TFTP_LOADADDR 0x00100000 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,78 @@ |
||||
/*
|
||||
* Copyright (C) 2003 Arabella Software Ltd. |
||||
* Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* Serial Presence Detect (SPD) EEPROM format according to the |
||||
* Intel's PC SDRAM Serial Presence Detect (SPD) Specification, |
||||
* revision 1.2B, November 1999 |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, but |
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
||||
* General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef _SPD_H_ |
||||
#define _SPD_H_ |
||||
|
||||
typedef struct spd_eeprom_s { |
||||
unsigned char info_size; /* # of bytes written into serial memory */ |
||||
unsigned char chip_size; /* Total # of bytes of SPD memory device */ |
||||
unsigned char mem_type; /* Fundamental memory type (FPM, EDO, SDRAM...) */ |
||||
unsigned char nrow_addr; /* # of Row Addresses on this assembly */ |
||||
unsigned char ncol_addr; /* # of Column Addresses on this assembly */ |
||||
unsigned char nrows; /* # of Module Rows on this assembly */ |
||||
unsigned char dataw_lsb; /* Data Width of this assembly */ |
||||
unsigned char dataw_msb; /* ... Data Width continuation */ |
||||
unsigned char voltage; /* Voltage interface standard of this assembly */ |
||||
unsigned char clk_cycle; /* SDRAM Cycle time at CL=X */ |
||||
unsigned char clk_access; /* SDRAM Access from Clock at CL=X */ |
||||
unsigned char config; /* DIMM Configuration type (non-parity, ECC) */ |
||||
unsigned char refresh; /* Refresh Rate/Type */ |
||||
unsigned char primw; /* Primary SDRAM Width */ |
||||
unsigned char ecw; /* Error Checking SDRAM width */ |
||||
unsigned char min_delay; /* Min Clock Delay for Back to Back Random Address */ |
||||
unsigned char burstl; /* Burst Lengths Supported */ |
||||
unsigned char nbanks; /* # of Banks on Each SDRAM Device */ |
||||
unsigned char cas_lat; /* CAS# Latencies Supported */ |
||||
unsigned char cs_lat; /* CS# Latency */ |
||||
unsigned char write_lat; /* Write Latency (also called Write Recovery time) */ |
||||
unsigned char mod_attr; /* SDRAM Module Attributes */ |
||||
unsigned char dev_attr; /* SDRAM Device Attributes */ |
||||
unsigned char clk_cycle2; /* Min SDRAM Cycle time at CL=X-1 */ |
||||
unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1 */ |
||||
unsigned char clk_cycle3; /* Min SDRAM Cycle time at CL=X-2 */ |
||||
unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2 */ |
||||
unsigned char trp; /* Min Row Precharge Time (tRP) */ |
||||
unsigned char trrd; /* Min Row Active to Row Active (tRRD) */ |
||||
unsigned char trcd; /* Min RAS to CAS Delay (tRCD) */ |
||||
unsigned char tras; /* Minimum RAS Pulse Width (tRAS) */ |
||||
unsigned char row_dens; /* Density of each row on module */ |
||||
unsigned char ca_setup; /* Command and Address signal input setup time */ |
||||
unsigned char ca_hold; /* Command and Address signal input hold time */ |
||||
unsigned char data_setup; /* Data signal input setup time */ |
||||
unsigned char data_hold; /* Data signal input hold time */ |
||||
unsigned char sset[26]; /* Superset Information (may be used in future) */ |
||||
unsigned char spd_rev; /* SPD Data Revision Code */ |
||||
unsigned char cksum; /* Checksum for bytes 0-62 */ |
||||
unsigned char mid[8]; /* Manufacturer's JEDEC ID code per JEP-108E */ |
||||
unsigned char mloc; /* Manufacturing Location */ |
||||
unsigned char mpart[18]; /* Manufacturer's Part Number */ |
||||
unsigned char rev[2]; /* Revision Code */ |
||||
unsigned char mdate[2]; /* Manufacturing Date */ |
||||
unsigned char sernum[4]; /* Assembly Serial Number */ |
||||
unsigned char mspec[27]; /* Manufacturer Specific Data */ |
||||
unsigned char freq; /* Intel specification frequency */ |
||||
unsigned char intel_cas; /* Intel Specification CAS# Latency support */ |
||||
} spd_eeprom_t; |
||||
|
||||
#endif /* _SPD_H_ */ |
||||
@ -0,0 +1,6 @@ |
||||
#ifndef _SPD_SDRAM_H_ |
||||
#define _SPD_SDRAM_H_ |
||||
|
||||
long int spd_sdram(int(read_spd)(uint addr)); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue