This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: Heiko Schocher <hs@denx.de>master
Heiko Schocher
16 years ago
committed by
Wolfgang Denk
parent
3feb647f3f
commit
de0443614a
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,24 @@ |
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#
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# (C) Copyright 2008
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# Heiko Schocher, DENX Software Engineering, hs@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xF0000000
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@ -0,0 +1,153 @@ |
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* Copyright (C) 2007 Logic Product Development, Inc. |
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* Peter Barada <peterb@logicpd.com> |
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* |
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* Copyright (C) 2007 MontaVista Software, Inc. |
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* Anton Vorontsov <avorontsov@ru.mvista.com> |
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* |
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* (C) Copyright 2008 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <asm/io.h> |
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#include <asm/mmu.h> |
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#include <pci.h> |
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#include <libfdt.h> |
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const qe_iop_conf_t qe_iop_conf_tab[] = { |
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/* port pin dir open_drain assign */ |
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/* MDIO */ |
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{0, 1, 3, 0, 2}, /* MDIO */ |
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{0, 2, 1, 0, 1}, /* MDC */ |
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/* UCC4 - UEC */ |
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{1, 14, 1, 0, 1}, /* TxD0 */ |
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{1, 15, 1, 0, 1}, /* TxD1 */ |
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{1, 20, 2, 0, 1}, /* RxD0 */ |
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{1, 21, 2, 0, 1}, /* RxD1 */ |
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{1, 18, 1, 0, 1}, /* TX_EN */ |
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{1, 26, 2, 0, 1}, /* RX_DV */ |
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{1, 27, 2, 0, 1}, /* RX_ER */ |
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{1, 24, 2, 0, 1}, /* COL */ |
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{1, 25, 2, 0, 1}, /* CRS */ |
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{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ |
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{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ |
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/* DUART - UART2 */ |
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{5, 0, 1, 0, 2}, /* UART2_SOUT */ |
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{5, 2, 1, 0, 1}, /* UART2_RTS */ |
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{5, 3, 2, 0, 2}, /* UART2_SIN */ |
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{5, 1, 2, 0, 3}, /* UART2_CTS */ |
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/* END of table */ |
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{0, 0, 0, 0, QE_IOP_TAB_END}, |
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}; |
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int board_early_init_r (void) |
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{ |
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void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); |
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u32 val; |
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/*
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* Because of errata in the UCCs, we have to write to the reserved |
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* registers to slow the clocks down. |
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*/ |
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val = in_be32 (reg); |
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/* UCC1 */ |
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val |= 0x00003000; |
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/* UCC2 */ |
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val |= 0x0c000000; |
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out_be32 (reg, val); |
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/* enable the PHY on the PIGGY */ |
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setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01); |
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return 0; |
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} |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CONFIG_SYS_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { |
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if (ddr_size & 1) |
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return -1; |
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} |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; |
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; |
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; |
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; |
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udelay (200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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return msize; |
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} |
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phys_size_t initdram (int board_type) |
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{ |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
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extern void ddr_enable_ecc (unsigned int dram_size); |
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#endif |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize = 0; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
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msize = fixed_sdram (); |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
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/*
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* Initialize DDR ECC byte |
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*/ |
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ddr_enable_ecc (msize * 1024 * 1024); |
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#endif |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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int checkboard (void) |
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{ |
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puts ("Board: Keymile kmeter1\n"); |
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return 0; |
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} |
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup (void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup (blob, bd); |
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} |
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#endif |
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@ -0,0 +1,91 @@ |
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Keymile kmeter1 Board |
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----------------------------------------- |
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1. Alternative Boot EEPROM |
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Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot |
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configuration from a serial EEPROM. During the development and debugging |
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phase it might be helpful to apply an alternative boot configuration in |
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a simple way. Therefore it is an alternative boot eeprom on the PIGGY, |
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which can be activated by setting the "ST" jumper on the PIGGY board. |
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2. Memory Map |
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BaseAddr PortSz Size Device |
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----------- ------ ----- ------ |
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0x0000_0000 64 bit 256MB DDR |
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0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 |
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0xa000_0000 8 bit 256MB PAXE on CS3 |
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0xe000_0000 2MB Int Mem Reg Space |
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0xf000_0000 16 bit 256MB FLASH on CS0 |
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DDR-SDRAM: |
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The current realization is made with four 16-bits memory devices. |
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Mounting options have been foreseen for device architectures from |
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4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices |
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thus resulting in a total capacity of 256MBytes. |
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3. Compilation |
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Assuming you're using BASH shell: |
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export CROSS_COMPILE=your-cross-compile-prefix |
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cd u-boot |
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make distclean |
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make kmeter1_config |
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make |
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4. Downloading and Flashing Images |
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4.0 Download over serial line using Kermit: |
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loadb |
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[Drop to kermit: |
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^\c |
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send <u-boot-bin-image> |
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c |
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] |
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Or via tftp: |
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tftp 10000 u-boot.bin |
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=> run load |
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Using FSL UEC0 device |
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TFTP from server 192.168.1.1; our IP address is 192.168.205.4 |
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Filename '/tftpboot/kmeter1/u-boot.bin'. |
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Load address: 0x200000 |
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Loading: ############## |
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done |
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Bytes transferred = 204204 (31dac hex) |
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=> |
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4.1 Reflash U-boot Image using U-boot |
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=> run update |
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..... done |
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Un-Protected 5 sectors |
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..... done |
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Erased 5 sectors |
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Copy to Flash... done |
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..... done |
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Protected 5 sectors |
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Total of 204204 bytes were the same |
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Saving Environment to Flash... |
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. done |
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Un-Protected 1 sectors |
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. done |
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Un-Protected 1 sectors |
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Erasing Flash... |
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. done |
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Erased 1 sectors |
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Writing to Flash... done |
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. done |
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Protected 1 sectors |
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. done |
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Protected 1 sectors |
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=> |
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5. Notes |
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1) The console baudrate for kmeter1 is 115200bps. |
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@ -0,0 +1,523 @@ |
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* Copyright (C) 2007 Logic Product Development, Inc. |
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* Peter Barada <peterb@logicpd.com> |
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* |
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* Copyright (C) 2007 MontaVista Software, Inc. |
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* Anton Vorontsov <avorontsov@ru.mvista.com> |
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* |
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* (C) Copyright 2008 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_E300 1 /* E300 family */ |
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#define CONFIG_QE 1 /* Has QE */ |
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#define CONFIG_MPC83XX 1 /* MPC83XX family */ |
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#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
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#define CONFIG_KMETER1 1 /* KMETER1 board specific */ |
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/*
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* System Clock Setup |
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*/ |
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#define CONFIG_83XX_CLKIN 66000000 |
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#define CONFIG_SYS_CLK_FREQ 66000000 |
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#define CONFIG_83XX_PCICLK 66000000 |
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/*
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* Hardware Reset Configuration Word |
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*/ |
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#define CONFIG_SYS_HRCW_LOW (\ |
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HRCWL_CSB_TO_CLKIN_4X1 | \
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HRCWL_CORE_TO_CSB_2X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X6 ) |
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#define CONFIG_SYS_HRCW_HIGH (\ |
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_NORMAL | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LDP_CLEAR ) |
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/*
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* System IO Config |
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*/ |
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#define CONFIG_SYS_SICRH 0x00000006 |
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#define CONFIG_SYS_SICRL 0x00000000 |
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#define CONFIG_BOARD_EARLY_INIT_R |
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/*
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* IMMR new address |
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*/ |
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#define CONFIG_SYS_IMMR 0xE0000000 |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
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#define CFG_83XX_DDR_USES_CS0 |
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#undef CONFIG_DDR_ECC |
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/*
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* DDRCDR - DDR Control Driver Register |
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*/ |
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|
||||||
|
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Manually set up DDR parameters |
||||||
|
*/ |
||||||
|
#define CONFIG_DDR_II |
||||||
|
#define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
||||||
|
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
||||||
|
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ |
||||||
|
CSCONFIG_ROW_BIT_13 | \
|
||||||
|
CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ |
||||||
|
SDRAM_CFG_SREN) |
||||||
|
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
||||||
|
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
||||||
|
#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
||||||
|
(0x406 << SDRAM_INTERVAL_REFINT_SHIFT)) |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_MODE 0x04440242 |
||||||
|
#define CONFIG_SYS_DDR_MODE2 0x00800000 |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
||||||
|
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
|
||||||
|
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
|
||||||
|
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
|
||||||
|
(0 << TIMING_CFG0_WWT_SHIFT) | \
|
||||||
|
(0 << TIMING_CFG0_RRT_SHIFT) | \
|
||||||
|
(0 << TIMING_CFG0_WRT_SHIFT) | \
|
||||||
|
(0 << TIMING_CFG0_RWT_SHIFT)) |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \ |
||||||
|
( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
|
||||||
|
( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
|
||||||
|
( 2 << TIMING_CFG1_WRREC_SHIFT) | \
|
||||||
|
( 2 << TIMING_CFG1_REFREC_SHIFT) | \
|
||||||
|
( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
|
||||||
|
( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
|
||||||
|
( 2 << TIMING_CFG1_PRETOACT_SHIFT)) |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
||||||
|
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
|
||||||
|
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
|
||||||
|
(1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
|
||||||
|
(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
|
||||||
|
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
|
||||||
|
(4 << TIMING_CFG2_CPO_SHIFT)) |
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory test |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ |
||||||
|
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ |
||||||
|
#define CONFIG_SYS_MEMTEST_END 0x00F00000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* The reserved memory |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||||
|
#define CONFIG_SYS_FLASH_BASE 0xF0000000 |
||||||
|
#define CONFIG_SYS_FLASH_BASE_1 0xF2000000 |
||||||
|
#define CONFIG_SYS_PIGGY_BASE 0x80000000 |
||||||
|
#define CONFIG_SYS_PAXE_BASE 0xA0000000 |
||||||
|
#define CONFIG_SYS_PAXE_SIZE 256 |
||||||
|
|
||||||
|
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
||||||
|
#define CONFIG_SYS_RAMBOOT |
||||||
|
#else |
||||||
|
#undef CONFIG_SYS_RAMBOOT |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||||
|
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Initial RAM Base Address Setup |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||||
|
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
||||||
|
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||||
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Local Bus Configuration & Clock Setup |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Init Local Bus Memory Controller: |
||||||
|
* |
||||||
|
* Bank Bus Machine PortSz Size Device |
||||||
|
* ---- --- ------- ------ ----- ------ |
||||||
|
* 0 Local GPCM 16 bit 256MB FLASH |
||||||
|
* 1 Local GPCM 8 bit 256KB GPIO/PIGGY |
||||||
|
* 3 Local GPCM 8 bit 256MB PAXE |
||||||
|
* |
||||||
|
*/ |
||||||
|
/*
|
||||||
|
* FLASH on the Local Bus |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
||||||
|
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||||
|
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ |
||||||
|
#define CONFIG_SYS_FLASH_PROTECTION 1 |
||||||
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ |
||||||
|
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ |
||||||
|
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||||
|
BR_V) |
||||||
|
|
||||||
|
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ |
||||||
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||||
|
OR_GPCM_SCY_5 | \
|
||||||
|
OR_GPCM_TRLX | OR_GPCM_EAD) |
||||||
|
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ |
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
||||||
|
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } |
||||||
|
|
||||||
|
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||||
|
|
||||||
|
/*
|
||||||
|
* PRIO1/PIGGY on the local bus CS1 |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ |
||||||
|
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ |
||||||
|
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
|
||||||
|
BR_V) |
||||||
|
#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \ |
||||||
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||||
|
OR_GPCM_SCY_2 | \
|
||||||
|
OR_GPCM_TRLX | OR_GPCM_EAD) |
||||||
|
|
||||||
|
/*
|
||||||
|
* PAXE on the local bus CS3 |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ |
||||||
|
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ |
||||||
|
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
|
||||||
|
BR_V) |
||||||
|
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ |
||||||
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||||
|
OR_GPCM_SCY_2 | \
|
||||||
|
OR_GPCM_TRLX | OR_GPCM_EAD) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial Port |
||||||
|
*/ |
||||||
|
#define CONFIG_CONS_INDEX 1 |
||||||
|
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||||
|
#define CONFIG_SYS_NS16550 |
||||||
|
#define CONFIG_SYS_NS16550_SERIAL |
||||||
|
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||||
|
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||||
|
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||||
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,} |
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
||||||
|
|
||||||
|
/* Pass open firmware flat tree */ |
||||||
|
#define CONFIG_OF_LIBFDT 1 |
||||||
|
#define CONFIG_OF_BOARD_SETUP 1 |
||||||
|
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||||
|
|
||||||
|
/*
|
||||||
|
* General PCI |
||||||
|
* Addresses are mapped 1-1. |
||||||
|
*/ |
||||||
|
#undef CONFIG_PCI /* No PCI */ |
||||||
|
|
||||||
|
#ifndef CONFIG_NET_MULTI |
||||||
|
#define CONFIG_NET_MULTI 1 |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* QE UEC ethernet configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_UEC_ETH |
||||||
|
#define CONFIG_ETHPRIME "FSL UEC0" |
||||||
|
|
||||||
|
#define CONFIG_UEC_ETH1 /* GETH1 */ |
||||||
|
#define UEC_VERBOSE_DEBUG 1 |
||||||
|
|
||||||
|
#ifdef CONFIG_UEC_ETH1 |
||||||
|
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ |
||||||
|
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ |
||||||
|
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 |
||||||
|
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH |
||||||
|
#define CONFIG_SYS_UEC1_PHY_ADDR 0 |
||||||
|
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_RAMBOOT |
||||||
|
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||||
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
||||||
|
#define CONFIG_ENV_SIZE 0x20000 |
||||||
|
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) |
||||||
|
|
||||||
|
/* Address and size of Redundant Environment Sector */ |
||||||
|
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
||||||
|
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||||
|
|
||||||
|
#else /* CFG_RAMBOOT */ |
||||||
|
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
||||||
|
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||||
|
#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||||
|
#define CONFIG_ENV_SIZE 0x2000 |
||||||
|
#endif /* CFG_RAMBOOT */ |
||||||
|
|
||||||
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||||
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options |
||||||
|
*/ |
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE |
||||||
|
#define CONFIG_BOOTP_BOOTPATH |
||||||
|
#define CONFIG_BOOTP_GATEWAY |
||||||
|
#define CONFIG_BOOTP_HOSTNAME |
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration. |
||||||
|
*/ |
||||||
|
#include <config_cmd_default.h> |
||||||
|
|
||||||
|
#define CONFIG_CMD_ASKENV |
||||||
|
#define CONFIG_CMD_DHCP |
||||||
|
#define CONFIG_CMD_NFS |
||||||
|
#define CONFIG_CMD_MII |
||||||
|
#define CONFIG_CMD_PING |
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) |
||||||
|
#define CONFIG_CMD_PCI |
||||||
|
#endif |
||||||
|
|
||||||
|
#if defined(CFG_RAMBOOT) |
||||||
|
#undef CONFIG_CMD_ENV |
||||||
|
#undef CONFIG_CMD_LOADS |
||||||
|
#endif |
||||||
|
|
||||||
|
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_HUSH_PARSER |
||||||
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
||||||
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||||
|
#else |
||||||
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||||
|
#endif |
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||||
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||||
|
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_HZ 1000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data |
||||||
|
* have to be in the first 8 MB of memory, since this is |
||||||
|
* the maximum mapped by the Linux kernel during initialization. |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Core HID Setup |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||||
|
#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
||||||
|
#define CONFIG_SYS_HID2 HID2_HBE |
||||||
|
|
||||||
|
/*
|
||||||
|
* MMU Setup |
||||||
|
*/ |
||||||
|
|
||||||
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
||||||
|
|
||||||
|
/* DDR: cache cacheable */ |
||||||
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ |
||||||
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||||
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||||
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||||
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||||
|
|
||||||
|
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||||
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
||||||
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||||
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||||
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||||
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||||
|
|
||||||
|
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ |
||||||
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||||
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP) |
||||||
|
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ |
||||||
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||||
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||||
|
|
||||||
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||||
|
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||||
|
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||||
|
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ |
||||||
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||||
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||||
|
|
||||||
|
/* Stack in dcache: cacheable, no memory coherence */ |
||||||
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
||||||
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||||
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
||||||
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
||||||
|
|
||||||
|
/* PAXE: icache cacheable, but dcache-inhibit and guarded */ |
||||||
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||||
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP) |
||||||
|
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ |
||||||
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||||
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
||||||
|
|
||||||
|
#ifdef CONFIG_PCI |
||||||
|
/* PCI MEM space: cacheable */ |
||||||
|
#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||||
|
#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||||
|
#define CFG_DBAT6L CFG_IBAT6L |
||||||
|
#define CFG_DBAT6U CFG_IBAT6U |
||||||
|
/* PCI MMIO space: cache-inhibit and guarded */ |
||||||
|
#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
||||||
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||||
|
#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||||
|
#define CFG_DBAT7L CFG_IBAT7L |
||||||
|
#define CFG_DBAT7U CFG_IBAT7U |
||||||
|
#else /* CONFIG_PCI */ |
||||||
|
#define CONFIG_SYS_IBAT6L (0) |
||||||
|
#define CONFIG_SYS_IBAT6U (0) |
||||||
|
#define CONFIG_SYS_IBAT7L (0) |
||||||
|
#define CONFIG_SYS_IBAT7U (0) |
||||||
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||||
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||||
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||||
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||||
|
#endif /* CONFIG_PCI */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions |
||||||
|
* |
||||||
|
* Boot Flags |
||||||
|
*/ |
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||||
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment Configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
|
||||||
|
#if defined(CONFIG_UEC_ETH) |
||||||
|
#define CONFIG_HAS_ETH0 |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
||||||
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||||
|
"netdev=eth0\0" \
|
||||||
|
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=${serverip}:${rootpath}\0" \
|
||||||
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||||
|
"addip=setenv bootargs ${bootargs} " \
|
||||||
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||||
|
":${hostname}:${netdev}:off panic=1\0" \
|
||||||
|
"addtty=setenv bootargs ${bootargs}" \
|
||||||
|
" console=ttyS0,${baudrate}\0" \
|
||||||
|
"fdt_addr=f0080000\0" \
|
||||||
|
"kernel_addr=f00a0000\0" \
|
||||||
|
"ramdisk_addr=f03a0000\0" \
|
||||||
|
"kernel_addr_r=400000\0" \
|
||||||
|
"fdt_addr_r=800000\0" \
|
||||||
|
"ramdisk_addr_r=810000\0" \
|
||||||
|
"flash_self=run ramargs addip addtty;" \
|
||||||
|
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||||
|
"flash_nfs=run nfsargs addip addtty;" \
|
||||||
|
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
||||||
|
"net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \
|
||||||
|
"tftp ${fdt_addr_r} ${fdt_file}; " \
|
||||||
|
"run nfsargs addip addtty;" \
|
||||||
|
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||||
|
"fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \
|
||||||
|
"boot_file=/tftpboot/kmeter1/uImage\0" \
|
||||||
|
"ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
|
||||||
|
"u-boot=/tftpboot/kmeter1/u-boot.bin\0" \
|
||||||
|
"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||||
|
"load=tftp $loadaddr ${u-boot}\0" \
|
||||||
|
"update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \
|
||||||
|
"erase " MK_STR(TEXT_BASE) " +$filesize;" \
|
||||||
|
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
|
||||||
|
"protect on " MK_STR(TEXT_BASE) " +$filesize;" \
|
||||||
|
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
|
||||||
|
"setenv filesize;saveenv\0" \
|
||||||
|
"upd=run load update\0" \
|
||||||
|
"loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
|
||||||
|
"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
|
||||||
|
"loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \
|
||||||
|
"unlock=yes\0" \
|
||||||
|
"" |
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "run net_nfs" |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue